1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp | FileCheck %s
6 define arm_aapcs_vfpcc <2 x i32> @stest_f64i32(<2 x double> %x) {
7 ; CHECK-LABEL: stest_f64i32:
8 ; CHECK: @ %bb.0: @ %entry
9 ; CHECK-NEXT: .save {r4, r5, r7, lr}
10 ; CHECK-NEXT: push {r4, r5, r7, lr}
11 ; CHECK-NEXT: .vsave {d8, d9}
12 ; CHECK-NEXT: vpush {d8, d9}
13 ; CHECK-NEXT: vmov q4, q0
14 ; CHECK-NEXT: vmov r0, r1, d8
15 ; CHECK-NEXT: bl __aeabi_d2lz
16 ; CHECK-NEXT: mov r4, r0
17 ; CHECK-NEXT: mov r5, r1
18 ; CHECK-NEXT: vmov r0, r1, d9
19 ; CHECK-NEXT: bl __aeabi_d2lz
20 ; CHECK-NEXT: adr r3, .LCPI0_0
21 ; CHECK-NEXT: mvn r12, #-2147483648
22 ; CHECK-NEXT: vldrw.u32 q0, [r3]
23 ; CHECK-NEXT: subs.w r3, r4, r12
24 ; CHECK-NEXT: sbcs r3, r5, #0
25 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r0
26 ; CHECK-NEXT: csetm r3, lt
27 ; CHECK-NEXT: subs.w r0, r0, r12
28 ; CHECK-NEXT: sbcs r0, r1, #0
29 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r1
30 ; CHECK-NEXT: mov.w r5, #0
31 ; CHECK-NEXT: csetm r0, lt
32 ; CHECK-NEXT: bfi r5, r3, #0, #8
33 ; CHECK-NEXT: mov.w r12, #-1
34 ; CHECK-NEXT: bfi r5, r0, #8, #8
35 ; CHECK-NEXT: movs r2, #0
36 ; CHECK-NEXT: vmsr p0, r5
37 ; CHECK-NEXT: adr r4, .LCPI0_1
38 ; CHECK-NEXT: vpsel q0, q1, q0
39 ; CHECK-NEXT: vldrw.u32 q1, [r4]
40 ; CHECK-NEXT: vmov r0, r1, d0
41 ; CHECK-NEXT: vmov r3, r5, d1
42 ; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
43 ; CHECK-NEXT: sbcs.w r0, r12, r1
44 ; CHECK-NEXT: csetm r0, lt
45 ; CHECK-NEXT: bfi r2, r0, #0, #8
46 ; CHECK-NEXT: rsbs.w r0, r3, #-2147483648
47 ; CHECK-NEXT: sbcs.w r0, r12, r5
48 ; CHECK-NEXT: csetm r0, lt
49 ; CHECK-NEXT: bfi r2, r0, #8, #8
50 ; CHECK-NEXT: vmsr p0, r2
51 ; CHECK-NEXT: vpsel q0, q0, q1
52 ; CHECK-NEXT: vpop {d8, d9}
53 ; CHECK-NEXT: pop {r4, r5, r7, pc}
54 ; CHECK-NEXT: .p2align 4
55 ; CHECK-NEXT: @ %bb.1:
56 ; CHECK-NEXT: .LCPI0_0:
57 ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
58 ; CHECK-NEXT: .long 0 @ 0x0
59 ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
60 ; CHECK-NEXT: .long 0 @ 0x0
61 ; CHECK-NEXT: .LCPI0_1:
62 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
63 ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
64 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
65 ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
67 %conv = fptosi <2 x double> %x to <2 x i64>
68 %0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>
69 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>
70 %1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648>
71 %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>
72 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
76 define arm_aapcs_vfpcc <2 x i32> @utest_f64i32(<2 x double> %x) {
77 ; CHECK-LABEL: utest_f64i32:
78 ; CHECK: @ %bb.0: @ %entry
79 ; CHECK-NEXT: .save {r4, r5, r7, lr}
80 ; CHECK-NEXT: push {r4, r5, r7, lr}
81 ; CHECK-NEXT: .vsave {d8, d9}
82 ; CHECK-NEXT: vpush {d8, d9}
83 ; CHECK-NEXT: vmov q4, q0
84 ; CHECK-NEXT: vmov r0, r1, d8
85 ; CHECK-NEXT: bl __aeabi_d2ulz
86 ; CHECK-NEXT: mov r4, r0
87 ; CHECK-NEXT: mov r5, r1
88 ; CHECK-NEXT: vmov r0, r1, d9
89 ; CHECK-NEXT: bl __aeabi_d2ulz
90 ; CHECK-NEXT: subs.w r3, r4, #-1
91 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r0
92 ; CHECK-NEXT: sbcs r3, r5, #0
93 ; CHECK-NEXT: mov.w r2, #0
94 ; CHECK-NEXT: csetm r3, lo
95 ; CHECK-NEXT: subs.w r0, r0, #-1
96 ; CHECK-NEXT: sbcs r0, r1, #0
97 ; CHECK-NEXT: bfi r2, r3, #0, #8
98 ; CHECK-NEXT: csetm r0, lo
99 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
100 ; CHECK-NEXT: bfi r2, r0, #8, #8
101 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r1
102 ; CHECK-NEXT: vmsr p0, r2
103 ; CHECK-NEXT: vpsel q0, q1, q0
104 ; CHECK-NEXT: vpop {d8, d9}
105 ; CHECK-NEXT: pop {r4, r5, r7, pc}
107 %conv = fptoui <2 x double> %x to <2 x i64>
108 %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
109 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
110 %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
114 define arm_aapcs_vfpcc <2 x i32> @ustest_f64i32(<2 x double> %x) {
115 ; CHECK-LABEL: ustest_f64i32:
116 ; CHECK: @ %bb.0: @ %entry
117 ; CHECK-NEXT: .save {r4, r5, r7, lr}
118 ; CHECK-NEXT: push {r4, r5, r7, lr}
119 ; CHECK-NEXT: .vsave {d8, d9}
120 ; CHECK-NEXT: vpush {d8, d9}
121 ; CHECK-NEXT: vmov q4, q0
122 ; CHECK-NEXT: vmov r0, r1, d8
123 ; CHECK-NEXT: bl __aeabi_d2lz
124 ; CHECK-NEXT: mov r4, r0
125 ; CHECK-NEXT: mov r5, r1
126 ; CHECK-NEXT: vmov r0, r1, d9
127 ; CHECK-NEXT: bl __aeabi_d2lz
128 ; CHECK-NEXT: subs.w r3, r4, #-1
129 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r0
130 ; CHECK-NEXT: sbcs r3, r5, #0
131 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r1
132 ; CHECK-NEXT: csetm r3, lt
133 ; CHECK-NEXT: subs.w r0, r0, #-1
134 ; CHECK-NEXT: mov.w r5, #0
135 ; CHECK-NEXT: sbcs r0, r1, #0
136 ; CHECK-NEXT: bfi r5, r3, #0, #8
137 ; CHECK-NEXT: csetm r0, lt
138 ; CHECK-NEXT: bfi r5, r0, #8, #8
139 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
140 ; CHECK-NEXT: vmsr p0, r5
141 ; CHECK-NEXT: movs r2, #0
142 ; CHECK-NEXT: vpsel q0, q1, q0
143 ; CHECK-NEXT: vmov.i32 q1, #0x0
144 ; CHECK-NEXT: vmov r0, r1, d0
145 ; CHECK-NEXT: vmov r3, r5, d1
146 ; CHECK-NEXT: rsbs r0, r0, #0
147 ; CHECK-NEXT: sbcs.w r0, r2, r1
148 ; CHECK-NEXT: csetm r0, lt
149 ; CHECK-NEXT: rsbs r1, r3, #0
150 ; CHECK-NEXT: sbcs.w r1, r2, r5
151 ; CHECK-NEXT: bfi r2, r0, #0, #8
152 ; CHECK-NEXT: csetm r0, lt
153 ; CHECK-NEXT: bfi r2, r0, #8, #8
154 ; CHECK-NEXT: vmsr p0, r2
155 ; CHECK-NEXT: vpsel q0, q0, q1
156 ; CHECK-NEXT: vpop {d8, d9}
157 ; CHECK-NEXT: pop {r4, r5, r7, pc}
159 %conv = fptosi <2 x double> %x to <2 x i64>
160 %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
161 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
162 %1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer
163 %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer
164 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
168 define arm_aapcs_vfpcc <4 x i32> @stest_f32i32(<4 x float> %x) {
169 ; CHECK-LABEL: stest_f32i32:
170 ; CHECK: @ %bb.0: @ %entry
171 ; CHECK-NEXT: vcvt.s32.f32 q0, q0
174 %conv = fptosi <4 x float> %x to <4 x i64>
175 %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
176 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
177 %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
178 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
179 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
183 define arm_aapcs_vfpcc <4 x i32> @utest_f32i32(<4 x float> %x) {
184 ; CHECK-LABEL: utest_f32i32:
185 ; CHECK: @ %bb.0: @ %entry
186 ; CHECK-NEXT: vcvt.u32.f32 q0, q0
189 %conv = fptoui <4 x float> %x to <4 x i64>
190 %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
191 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
192 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
196 define arm_aapcs_vfpcc <4 x i32> @ustest_f32i32(<4 x float> %x) {
197 ; CHECK-LABEL: ustest_f32i32:
198 ; CHECK: @ %bb.0: @ %entry
199 ; CHECK-NEXT: vcvt.u32.f32 q0, q0
202 %conv = fptosi <4 x float> %x to <4 x i64>
203 %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
204 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
205 %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer
206 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer
207 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
211 define arm_aapcs_vfpcc <4 x i32> @stest_f16i32(<4 x half> %x) {
212 ; CHECK-LABEL: stest_f16i32:
213 ; CHECK: @ %bb.0: @ %entry
214 ; CHECK-NEXT: .save {r4, r5, r7, lr}
215 ; CHECK-NEXT: push {r4, r5, r7, lr}
216 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
217 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
218 ; CHECK-NEXT: vmov.u16 r0, q0[3]
219 ; CHECK-NEXT: vmov q4, q0
220 ; CHECK-NEXT: bl __fixhfdi
221 ; CHECK-NEXT: mov r4, r0
222 ; CHECK-NEXT: vmov.u16 r0, q4[0]
223 ; CHECK-NEXT: bl __fixhfdi
224 ; CHECK-NEXT: mov r5, r0
225 ; CHECK-NEXT: vmov.u16 r0, q4[2]
226 ; CHECK-NEXT: bl __fixhfdi
227 ; CHECK-NEXT: vmov q5[2], q5[0], r5, r0
228 ; CHECK-NEXT: vmov.u16 r0, q4[1]
229 ; CHECK-NEXT: bl __fixhfdi
230 ; CHECK-NEXT: vmov q5[3], q5[1], r0, r4
231 ; CHECK-NEXT: vmov q0, q5
232 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
233 ; CHECK-NEXT: pop {r4, r5, r7, pc}
235 %conv = fptosi <4 x half> %x to <4 x i64>
236 %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
237 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
238 %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
239 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
240 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
244 define arm_aapcs_vfpcc <4 x i32> @utesth_f16i32(<4 x half> %x) {
245 ; CHECK-LABEL: utesth_f16i32:
246 ; CHECK: @ %bb.0: @ %entry
247 ; CHECK-NEXT: .save {r4, r5, r7, lr}
248 ; CHECK-NEXT: push {r4, r5, r7, lr}
249 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
250 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
251 ; CHECK-NEXT: vmov.u16 r0, q0[3]
252 ; CHECK-NEXT: vmov q4, q0
253 ; CHECK-NEXT: bl __fixunshfdi
254 ; CHECK-NEXT: mov r4, r0
255 ; CHECK-NEXT: vmov.u16 r0, q4[0]
256 ; CHECK-NEXT: bl __fixunshfdi
257 ; CHECK-NEXT: mov r5, r0
258 ; CHECK-NEXT: vmov.u16 r0, q4[2]
259 ; CHECK-NEXT: bl __fixunshfdi
260 ; CHECK-NEXT: vmov q5[2], q5[0], r5, r0
261 ; CHECK-NEXT: vmov.u16 r0, q4[1]
262 ; CHECK-NEXT: bl __fixunshfdi
263 ; CHECK-NEXT: vmov q5[3], q5[1], r0, r4
264 ; CHECK-NEXT: vmov q0, q5
265 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
266 ; CHECK-NEXT: pop {r4, r5, r7, pc}
268 %conv = fptoui <4 x half> %x to <4 x i64>
269 %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
270 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
271 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
275 define arm_aapcs_vfpcc <4 x i32> @ustest_f16i32(<4 x half> %x) {
276 ; CHECK-LABEL: ustest_f16i32:
277 ; CHECK: @ %bb.0: @ %entry
278 ; CHECK-NEXT: .save {r4, r5, r6, lr}
279 ; CHECK-NEXT: push {r4, r5, r6, lr}
280 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
281 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
282 ; CHECK-NEXT: vmov.u16 r0, q0[3]
283 ; CHECK-NEXT: vmov q4, q0
284 ; CHECK-NEXT: bl __fixhfdi
285 ; CHECK-NEXT: mov r4, r0
286 ; CHECK-NEXT: vmov.u16 r0, q4[2]
287 ; CHECK-NEXT: mov r5, r1
288 ; CHECK-NEXT: bl __fixhfdi
289 ; CHECK-NEXT: rsbs r2, r0, #0
290 ; CHECK-NEXT: mov.w r6, #0
291 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
292 ; CHECK-NEXT: sbcs.w r0, r6, r1
293 ; CHECK-NEXT: csetm r0, lt
294 ; CHECK-NEXT: movs r1, #0
295 ; CHECK-NEXT: bfi r1, r0, #0, #8
296 ; CHECK-NEXT: rsbs r0, r4, #0
297 ; CHECK-NEXT: sbcs.w r0, r6, r5
298 ; CHECK-NEXT: vmov.i32 q5, #0x0
299 ; CHECK-NEXT: csetm r0, lt
300 ; CHECK-NEXT: bfi r1, r0, #8, #8
301 ; CHECK-NEXT: vmov.u16 r0, q4[1]
302 ; CHECK-NEXT: vmsr p0, r1
303 ; CHECK-NEXT: vpsel q6, q0, q5
304 ; CHECK-NEXT: bl __fixhfdi
305 ; CHECK-NEXT: mov r4, r0
306 ; CHECK-NEXT: vmov.u16 r0, q4[0]
307 ; CHECK-NEXT: mov r5, r1
308 ; CHECK-NEXT: bl __fixhfdi
309 ; CHECK-NEXT: rsbs r2, r0, #0
310 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
311 ; CHECK-NEXT: sbcs.w r0, r6, r1
312 ; CHECK-NEXT: csetm r0, lt
313 ; CHECK-NEXT: rsbs r1, r4, #0
314 ; CHECK-NEXT: sbcs.w r1, r6, r5
315 ; CHECK-NEXT: bfi r6, r0, #0, #8
316 ; CHECK-NEXT: csetm r0, lt
317 ; CHECK-NEXT: bfi r6, r0, #8, #8
318 ; CHECK-NEXT: vmsr p0, r6
319 ; CHECK-NEXT: vpsel q0, q0, q5
320 ; CHECK-NEXT: vmov.f32 s1, s2
321 ; CHECK-NEXT: vmov.f32 s2, s24
322 ; CHECK-NEXT: vmov.f32 s3, s26
323 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
324 ; CHECK-NEXT: pop {r4, r5, r6, pc}
326 %conv = fptosi <4 x half> %x to <4 x i64>
327 %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
328 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
329 %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer
330 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer
331 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
337 define arm_aapcs_vfpcc <2 x i16> @stest_f64i16(<2 x double> %x) {
338 ; CHECK-LABEL: stest_f64i16:
339 ; CHECK: @ %bb.0: @ %entry
340 ; CHECK-NEXT: .save {r4, r5, r7, lr}
341 ; CHECK-NEXT: push {r4, r5, r7, lr}
342 ; CHECK-NEXT: .vsave {d8, d9}
343 ; CHECK-NEXT: vpush {d8, d9}
344 ; CHECK-NEXT: vmov q4, q0
345 ; CHECK-NEXT: vmov r0, r1, d9
346 ; CHECK-NEXT: bl __aeabi_d2lz
347 ; CHECK-NEXT: mov r4, r0
348 ; CHECK-NEXT: mov r5, r1
349 ; CHECK-NEXT: vmov r0, r1, d8
350 ; CHECK-NEXT: bl __aeabi_d2lz
351 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
352 ; CHECK-NEXT: movw r4, #32767
353 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
354 ; CHECK-NEXT: adr.w r12, .LCPI9_0
355 ; CHECK-NEXT: vmov r1, r2, d0
356 ; CHECK-NEXT: vldrw.u32 q1, [r12]
357 ; CHECK-NEXT: vmov r3, r5, d1
358 ; CHECK-NEXT: movw lr, #32768
359 ; CHECK-NEXT: movt lr, #65535
360 ; CHECK-NEXT: mov.w r12, #-1
361 ; CHECK-NEXT: movs r0, #0
362 ; CHECK-NEXT: subs r1, r1, r4
363 ; CHECK-NEXT: sbcs r1, r2, #0
364 ; CHECK-NEXT: mov.w r2, #0
365 ; CHECK-NEXT: csetm r1, lt
366 ; CHECK-NEXT: bfi r2, r1, #0, #8
367 ; CHECK-NEXT: subs r1, r3, r4
368 ; CHECK-NEXT: sbcs r1, r5, #0
369 ; CHECK-NEXT: adr r4, .LCPI9_1
370 ; CHECK-NEXT: csetm r1, lt
371 ; CHECK-NEXT: bfi r2, r1, #8, #8
372 ; CHECK-NEXT: vmsr p0, r2
373 ; CHECK-NEXT: vpsel q0, q0, q1
374 ; CHECK-NEXT: vldrw.u32 q1, [r4]
375 ; CHECK-NEXT: vmov r1, r2, d0
376 ; CHECK-NEXT: vmov r3, r5, d1
377 ; CHECK-NEXT: subs.w r1, lr, r1
378 ; CHECK-NEXT: sbcs.w r1, r12, r2
379 ; CHECK-NEXT: csetm r1, lt
380 ; CHECK-NEXT: bfi r0, r1, #0, #8
381 ; CHECK-NEXT: subs.w r1, lr, r3
382 ; CHECK-NEXT: sbcs.w r1, r12, r5
383 ; CHECK-NEXT: csetm r1, lt
384 ; CHECK-NEXT: bfi r0, r1, #8, #8
385 ; CHECK-NEXT: vmsr p0, r0
386 ; CHECK-NEXT: vpsel q0, q0, q1
387 ; CHECK-NEXT: vpop {d8, d9}
388 ; CHECK-NEXT: pop {r4, r5, r7, pc}
389 ; CHECK-NEXT: .p2align 4
390 ; CHECK-NEXT: @ %bb.1:
391 ; CHECK-NEXT: .LCPI9_0:
392 ; CHECK-NEXT: .long 32767 @ 0x7fff
393 ; CHECK-NEXT: .long 0 @ 0x0
394 ; CHECK-NEXT: .long 32767 @ 0x7fff
395 ; CHECK-NEXT: .long 0 @ 0x0
396 ; CHECK-NEXT: .LCPI9_1:
397 ; CHECK-NEXT: .long 4294934528 @ 0xffff8000
398 ; CHECK-NEXT: .long 0 @ 0x0
399 ; CHECK-NEXT: .long 4294934528 @ 0xffff8000
400 ; CHECK-NEXT: .long 0 @ 0x0
402 %conv = fptosi <2 x double> %x to <2 x i32>
403 %0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767>
404 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>
405 %1 = icmp sgt <2 x i32> %spec.store.select, <i32 -32768, i32 -32768>
406 %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>
407 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
411 define arm_aapcs_vfpcc <2 x i16> @utest_f64i16(<2 x double> %x) {
412 ; CHECK-LABEL: utest_f64i16:
413 ; CHECK: @ %bb.0: @ %entry
414 ; CHECK-NEXT: .save {r4, r5, r7, lr}
415 ; CHECK-NEXT: push {r4, r5, r7, lr}
416 ; CHECK-NEXT: .vsave {d8, d9}
417 ; CHECK-NEXT: vpush {d8, d9}
418 ; CHECK-NEXT: vmov q4, q0
419 ; CHECK-NEXT: vmov r0, r1, d9
420 ; CHECK-NEXT: bl __aeabi_d2ulz
421 ; CHECK-NEXT: mov r4, r0
422 ; CHECK-NEXT: mov r5, r1
423 ; CHECK-NEXT: vmov r0, r1, d8
424 ; CHECK-NEXT: bl __aeabi_d2ulz
425 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
426 ; CHECK-NEXT: movw r4, #65535
427 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
428 ; CHECK-NEXT: movs r5, #0
429 ; CHECK-NEXT: vmov r0, r1, d0
430 ; CHECK-NEXT: vmov.i64 q1, #0xffff
431 ; CHECK-NEXT: vmov r2, r3, d1
432 ; CHECK-NEXT: subs r0, r0, r4
433 ; CHECK-NEXT: sbcs r0, r1, #0
434 ; CHECK-NEXT: csetm r0, lo
435 ; CHECK-NEXT: bfi r5, r0, #0, #8
436 ; CHECK-NEXT: subs r0, r2, r4
437 ; CHECK-NEXT: sbcs r0, r3, #0
438 ; CHECK-NEXT: csetm r0, lo
439 ; CHECK-NEXT: bfi r5, r0, #8, #8
440 ; CHECK-NEXT: vmsr p0, r5
441 ; CHECK-NEXT: vpsel q0, q0, q1
442 ; CHECK-NEXT: vpop {d8, d9}
443 ; CHECK-NEXT: pop {r4, r5, r7, pc}
445 %conv = fptoui <2 x double> %x to <2 x i32>
446 %0 = icmp ult <2 x i32> %conv, <i32 65535, i32 65535>
447 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
448 %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>
452 define arm_aapcs_vfpcc <2 x i16> @ustest_f64i16(<2 x double> %x) {
453 ; CHECK-LABEL: ustest_f64i16:
454 ; CHECK: @ %bb.0: @ %entry
455 ; CHECK-NEXT: .save {r4, r5, r7, lr}
456 ; CHECK-NEXT: push {r4, r5, r7, lr}
457 ; CHECK-NEXT: .vsave {d8, d9}
458 ; CHECK-NEXT: vpush {d8, d9}
459 ; CHECK-NEXT: vmov q4, q0
460 ; CHECK-NEXT: vmov r0, r1, d9
461 ; CHECK-NEXT: bl __aeabi_d2lz
462 ; CHECK-NEXT: mov r4, r0
463 ; CHECK-NEXT: mov r5, r1
464 ; CHECK-NEXT: vmov r0, r1, d8
465 ; CHECK-NEXT: bl __aeabi_d2lz
466 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
467 ; CHECK-NEXT: movw r4, #65535
468 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
469 ; CHECK-NEXT: vmov.i64 q1, #0xffff
470 ; CHECK-NEXT: vmov r1, r2, d0
471 ; CHECK-NEXT: movs r0, #0
472 ; CHECK-NEXT: vmov r3, r5, d1
473 ; CHECK-NEXT: subs r1, r1, r4
474 ; CHECK-NEXT: sbcs r1, r2, #0
475 ; CHECK-NEXT: mov.w r2, #0
476 ; CHECK-NEXT: csetm r1, lt
477 ; CHECK-NEXT: bfi r2, r1, #0, #8
478 ; CHECK-NEXT: subs r1, r3, r4
479 ; CHECK-NEXT: sbcs r1, r5, #0
480 ; CHECK-NEXT: csetm r1, lt
481 ; CHECK-NEXT: bfi r2, r1, #8, #8
482 ; CHECK-NEXT: vmsr p0, r2
483 ; CHECK-NEXT: vpsel q0, q0, q1
484 ; CHECK-NEXT: vmov.i32 q1, #0x0
485 ; CHECK-NEXT: vmov r1, r2, d0
486 ; CHECK-NEXT: vmov r3, r5, d1
487 ; CHECK-NEXT: rsbs r1, r1, #0
488 ; CHECK-NEXT: sbcs.w r1, r0, r2
489 ; CHECK-NEXT: csetm r1, lt
490 ; CHECK-NEXT: rsbs r2, r3, #0
491 ; CHECK-NEXT: sbcs.w r2, r0, r5
492 ; CHECK-NEXT: bfi r0, r1, #0, #8
493 ; CHECK-NEXT: csetm r1, lt
494 ; CHECK-NEXT: bfi r0, r1, #8, #8
495 ; CHECK-NEXT: vmsr p0, r0
496 ; CHECK-NEXT: vpsel q0, q0, q1
497 ; CHECK-NEXT: vpop {d8, d9}
498 ; CHECK-NEXT: pop {r4, r5, r7, pc}
500 %conv = fptosi <2 x double> %x to <2 x i32>
501 %0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>
502 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
503 %1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer
504 %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer
505 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
509 define arm_aapcs_vfpcc <4 x i16> @stest_f32i16(<4 x float> %x) {
510 ; CHECK-LABEL: stest_f32i16:
511 ; CHECK: @ %bb.0: @ %entry
512 ; CHECK-NEXT: vcvt.s32.f32 q0, q0
513 ; CHECK-NEXT: vqmovnb.s32 q0, q0
514 ; CHECK-NEXT: vmovlb.s16 q0, q0
517 %conv = fptosi <4 x float> %x to <4 x i32>
518 %0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767>
519 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
520 %1 = icmp sgt <4 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
521 %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
522 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
526 define arm_aapcs_vfpcc <4 x i16> @utest_f32i16(<4 x float> %x) {
527 ; CHECK-LABEL: utest_f32i16:
528 ; CHECK: @ %bb.0: @ %entry
529 ; CHECK-NEXT: vcvt.u32.f32 q0, q0
530 ; CHECK-NEXT: vqmovnb.u32 q0, q0
531 ; CHECK-NEXT: vmovlb.u16 q0, q0
534 %conv = fptoui <4 x float> %x to <4 x i32>
535 %0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
536 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
537 %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
541 define arm_aapcs_vfpcc <4 x i16> @ustest_f32i16(<4 x float> %x) {
542 ; CHECK-LABEL: ustest_f32i16:
543 ; CHECK: @ %bb.0: @ %entry
544 ; CHECK-NEXT: vmov.i32 q1, #0xffff
545 ; CHECK-NEXT: vcvt.s32.f32 q0, q0
546 ; CHECK-NEXT: vmov.i32 q2, #0x0
547 ; CHECK-NEXT: vmin.s32 q0, q0, q1
548 ; CHECK-NEXT: vmax.s32 q0, q0, q2
551 %conv = fptosi <4 x float> %x to <4 x i32>
552 %0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
553 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
554 %1 = icmp sgt <4 x i32> %spec.store.select, zeroinitializer
555 %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> zeroinitializer
556 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
560 define arm_aapcs_vfpcc <8 x i16> @stest_f16i16(<8 x half> %x) {
561 ; CHECK-LABEL: stest_f16i16:
562 ; CHECK: @ %bb.0: @ %entry
563 ; CHECK-NEXT: vcvt.s16.f16 q0, q0
566 %conv = fptosi <8 x half> %x to <8 x i32>
567 %0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
568 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
569 %1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>
570 %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>
571 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
575 define arm_aapcs_vfpcc <8 x i16> @utesth_f16i16(<8 x half> %x) {
576 ; CHECK-LABEL: utesth_f16i16:
577 ; CHECK: @ %bb.0: @ %entry
578 ; CHECK-NEXT: vmovx.f16 s6, s2
579 ; CHECK-NEXT: vcvt.u32.f16 s12, s2
580 ; CHECK-NEXT: vmovx.f16 s2, s0
581 ; CHECK-NEXT: vcvt.u32.f16 s0, s0
582 ; CHECK-NEXT: vcvt.u32.f16 s14, s2
583 ; CHECK-NEXT: vmov r0, s0
584 ; CHECK-NEXT: vmovx.f16 s4, s3
585 ; CHECK-NEXT: vmovx.f16 s10, s1
586 ; CHECK-NEXT: vcvt.u32.f16 s8, s3
587 ; CHECK-NEXT: vcvt.u32.f16 s5, s1
588 ; CHECK-NEXT: vmov.16 q0[0], r0
589 ; CHECK-NEXT: vmov r0, s14
590 ; CHECK-NEXT: vmov.16 q0[1], r0
591 ; CHECK-NEXT: vmov r0, s5
592 ; CHECK-NEXT: vcvt.u32.f16 s10, s10
593 ; CHECK-NEXT: vmov.16 q0[2], r0
594 ; CHECK-NEXT: vmov r0, s10
595 ; CHECK-NEXT: vcvt.u32.f16 s6, s6
596 ; CHECK-NEXT: vmov.16 q0[3], r0
597 ; CHECK-NEXT: vmov r0, s12
598 ; CHECK-NEXT: vmov.16 q0[4], r0
599 ; CHECK-NEXT: vmov r0, s6
600 ; CHECK-NEXT: vmov.16 q0[5], r0
601 ; CHECK-NEXT: vmov r0, s8
602 ; CHECK-NEXT: vcvt.u32.f16 s4, s4
603 ; CHECK-NEXT: vmov.16 q0[6], r0
604 ; CHECK-NEXT: vmov r0, s4
605 ; CHECK-NEXT: vmov.16 q0[7], r0
608 %conv = fptoui <8 x half> %x to <8 x i32>
609 %0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
610 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
611 %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
615 define arm_aapcs_vfpcc <8 x i16> @ustest_f16i16(<8 x half> %x) {
616 ; CHECK-LABEL: ustest_f16i16:
617 ; CHECK: @ %bb.0: @ %entry
618 ; CHECK-NEXT: .vsave {d8, d9}
619 ; CHECK-NEXT: vpush {d8, d9}
620 ; CHECK-NEXT: .pad #16
621 ; CHECK-NEXT: sub sp, #16
622 ; CHECK-NEXT: vmovx.f16 s6, s0
623 ; CHECK-NEXT: vcvt.s32.f16 s10, s0
624 ; CHECK-NEXT: vmovx.f16 s0, s3
625 ; CHECK-NEXT: vcvt.s32.f16 s5, s3
626 ; CHECK-NEXT: vcvt.s32.f16 s12, s0
627 ; CHECK-NEXT: vmovx.f16 s0, s2
628 ; CHECK-NEXT: vcvt.s32.f16 s7, s2
629 ; CHECK-NEXT: vcvt.s32.f16 s14, s0
630 ; CHECK-NEXT: vmov r1, s5
631 ; CHECK-NEXT: vmovx.f16 s4, s1
632 ; CHECK-NEXT: vmov r2, s7
633 ; CHECK-NEXT: vcvt.s32.f16 s8, s1
634 ; CHECK-NEXT: vmov q4[2], q4[0], r2, r1
635 ; CHECK-NEXT: vmov r1, s12
636 ; CHECK-NEXT: vmov r2, s14
637 ; CHECK-NEXT: vcvt.s32.f16 s4, s4
638 ; CHECK-NEXT: vmov q4[3], q4[1], r2, r1
639 ; CHECK-NEXT: vcvt.s32.f16 s6, s6
640 ; CHECK-NEXT: vmov r1, s8
641 ; CHECK-NEXT: vmov.i32 q0, #0x0
642 ; CHECK-NEXT: vmov r2, s10
643 ; CHECK-NEXT: mov r0, sp
644 ; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
645 ; CHECK-NEXT: vmov r1, s4
646 ; CHECK-NEXT: vmov r2, s6
647 ; CHECK-NEXT: vmax.s32 q3, q4, q0
648 ; CHECK-NEXT: vmov q2[3], q2[1], r2, r1
649 ; CHECK-NEXT: vstrh.32 q3, [r0, #8]
650 ; CHECK-NEXT: vmax.s32 q0, q2, q0
651 ; CHECK-NEXT: vstrh.32 q0, [r0]
652 ; CHECK-NEXT: vldrw.u32 q0, [r0]
653 ; CHECK-NEXT: add sp, #16
654 ; CHECK-NEXT: vpop {d8, d9}
657 %conv = fptosi <8 x half> %x to <8 x i32>
658 %0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
659 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
660 %1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer
661 %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer
662 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
668 define arm_aapcs_vfpcc <2 x i64> @stest_f64i64(<2 x double> %x) {
669 ; CHECK-LABEL: stest_f64i64:
670 ; CHECK: @ %bb.0: @ %entry
671 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
672 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
673 ; CHECK-NEXT: .vsave {d8, d9}
674 ; CHECK-NEXT: vpush {d8, d9}
675 ; CHECK-NEXT: vmov q4, q0
676 ; CHECK-NEXT: vmov r0, r1, d9
677 ; CHECK-NEXT: bl __fixdfti
678 ; CHECK-NEXT: vmov r12, lr, d8
679 ; CHECK-NEXT: subs.w r4, r0, #-1
680 ; CHECK-NEXT: mvn r9, #-2147483648
681 ; CHECK-NEXT: sbcs.w r4, r1, r9
682 ; CHECK-NEXT: sbcs r4, r2, #0
683 ; CHECK-NEXT: mov.w r7, #-1
684 ; CHECK-NEXT: sbcs r4, r3, #0
685 ; CHECK-NEXT: mov.w r10, #-2147483648
686 ; CHECK-NEXT: cset r4, lt
687 ; CHECK-NEXT: cmp r4, #0
688 ; CHECK-NEXT: csel r3, r3, r4, ne
689 ; CHECK-NEXT: csel r2, r2, r4, ne
690 ; CHECK-NEXT: csel r4, r0, r7, ne
691 ; CHECK-NEXT: csel r1, r1, r9, ne
692 ; CHECK-NEXT: rsbs r0, r4, #0
693 ; CHECK-NEXT: sbcs.w r0, r10, r1
694 ; CHECK-NEXT: sbcs.w r0, r7, r2
695 ; CHECK-NEXT: sbcs.w r0, r7, r3
696 ; CHECK-NEXT: cset r5, lt
697 ; CHECK-NEXT: cmp r5, #0
698 ; CHECK-NEXT: csel r8, r1, r10, ne
699 ; CHECK-NEXT: mov r0, r12
700 ; CHECK-NEXT: mov r1, lr
701 ; CHECK-NEXT: bl __fixdfti
702 ; CHECK-NEXT: subs.w r6, r0, #-1
703 ; CHECK-NEXT: sbcs.w r6, r1, r9
704 ; CHECK-NEXT: sbcs r6, r2, #0
705 ; CHECK-NEXT: sbcs r6, r3, #0
706 ; CHECK-NEXT: cset r6, lt
707 ; CHECK-NEXT: cmp r6, #0
708 ; CHECK-NEXT: csel r0, r0, r7, ne
709 ; CHECK-NEXT: csel r1, r1, r9, ne
710 ; CHECK-NEXT: csel r3, r3, r6, ne
711 ; CHECK-NEXT: csel r2, r2, r6, ne
712 ; CHECK-NEXT: rsbs r6, r0, #0
713 ; CHECK-NEXT: sbcs.w r6, r10, r1
714 ; CHECK-NEXT: sbcs.w r2, r7, r2
715 ; CHECK-NEXT: sbcs.w r2, r7, r3
716 ; CHECK-NEXT: cset r2, lt
717 ; CHECK-NEXT: cmp r2, #0
718 ; CHECK-NEXT: csel r1, r1, r10, ne
719 ; CHECK-NEXT: cmp r5, #0
720 ; CHECK-NEXT: csel r3, r4, r5, ne
721 ; CHECK-NEXT: cmp r2, #0
722 ; CHECK-NEXT: csel r0, r0, r2, ne
723 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
724 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
725 ; CHECK-NEXT: vpop {d8, d9}
726 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
728 %conv = fptosi <2 x double> %x to <2 x i128>
729 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
730 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
731 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
732 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
733 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
737 define arm_aapcs_vfpcc <2 x i64> @utest_f64i64(<2 x double> %x) {
738 ; CHECK-LABEL: utest_f64i64:
739 ; CHECK: @ %bb.0: @ %entry
740 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
741 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
742 ; CHECK-NEXT: .pad #4
743 ; CHECK-NEXT: sub sp, #4
744 ; CHECK-NEXT: .vsave {d8, d9}
745 ; CHECK-NEXT: vpush {d8, d9}
746 ; CHECK-NEXT: vmov q4, q0
747 ; CHECK-NEXT: vmov r0, r1, d9
748 ; CHECK-NEXT: bl __fixunsdfti
749 ; CHECK-NEXT: mov r5, r1
750 ; CHECK-NEXT: vmov r4, r1, d8
751 ; CHECK-NEXT: subs r2, #1
752 ; CHECK-NEXT: sbcs r2, r3, #0
753 ; CHECK-NEXT: cset r6, lo
754 ; CHECK-NEXT: cmp r6, #0
755 ; CHECK-NEXT: csel r7, r0, r6, ne
756 ; CHECK-NEXT: mov r0, r4
757 ; CHECK-NEXT: bl __fixunsdfti
758 ; CHECK-NEXT: subs r2, #1
759 ; CHECK-NEXT: sbcs r2, r3, #0
760 ; CHECK-NEXT: cset r2, lo
761 ; CHECK-NEXT: cmp r2, #0
762 ; CHECK-NEXT: csel r0, r0, r2, ne
763 ; CHECK-NEXT: cmp r6, #0
764 ; CHECK-NEXT: csel r3, r5, r6, ne
765 ; CHECK-NEXT: cmp r2, #0
766 ; CHECK-NEXT: csel r1, r1, r2, ne
767 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
768 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
769 ; CHECK-NEXT: vpop {d8, d9}
770 ; CHECK-NEXT: add sp, #4
771 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
773 %conv = fptoui <2 x double> %x to <2 x i128>
774 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
775 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
776 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
780 define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64(<2 x double> %x) {
781 ; CHECK-LABEL: ustest_f64i64:
782 ; CHECK: @ %bb.0: @ %entry
783 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
784 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
785 ; CHECK-NEXT: .pad #4
786 ; CHECK-NEXT: sub sp, #4
787 ; CHECK-NEXT: .vsave {d8, d9}
788 ; CHECK-NEXT: vpush {d8, d9}
789 ; CHECK-NEXT: vmov q4, q0
790 ; CHECK-NEXT: vmov r0, r1, d9
791 ; CHECK-NEXT: bl __fixdfti
792 ; CHECK-NEXT: vmov r12, lr, d8
793 ; CHECK-NEXT: subs r4, r2, #1
794 ; CHECK-NEXT: sbcs r4, r3, #0
795 ; CHECK-NEXT: mov.w r8, #1
796 ; CHECK-NEXT: cset r5, lt
797 ; CHECK-NEXT: movs r7, #0
798 ; CHECK-NEXT: cmp r5, #0
799 ; CHECK-NEXT: csel r0, r0, r5, ne
800 ; CHECK-NEXT: csel r3, r3, r5, ne
801 ; CHECK-NEXT: csel r2, r2, r8, ne
802 ; CHECK-NEXT: csel r4, r1, r5, ne
803 ; CHECK-NEXT: rsbs r1, r0, #0
804 ; CHECK-NEXT: sbcs.w r1, r7, r4
805 ; CHECK-NEXT: sbcs.w r1, r7, r2
806 ; CHECK-NEXT: sbcs.w r1, r7, r3
807 ; CHECK-NEXT: cset r6, lt
808 ; CHECK-NEXT: cmp r6, #0
809 ; CHECK-NEXT: csel r9, r0, r6, ne
810 ; CHECK-NEXT: mov r0, r12
811 ; CHECK-NEXT: mov r1, lr
812 ; CHECK-NEXT: bl __fixdfti
813 ; CHECK-NEXT: subs r5, r2, #1
814 ; CHECK-NEXT: sbcs r5, r3, #0
815 ; CHECK-NEXT: cset r5, lt
816 ; CHECK-NEXT: cmp r5, #0
817 ; CHECK-NEXT: csel r0, r0, r5, ne
818 ; CHECK-NEXT: csel r2, r2, r8, ne
819 ; CHECK-NEXT: csel r3, r3, r5, ne
820 ; CHECK-NEXT: csel r1, r1, r5, ne
821 ; CHECK-NEXT: rsbs r5, r0, #0
822 ; CHECK-NEXT: sbcs.w r5, r7, r1
823 ; CHECK-NEXT: sbcs.w r2, r7, r2
824 ; CHECK-NEXT: sbcs.w r2, r7, r3
825 ; CHECK-NEXT: cset r2, lt
826 ; CHECK-NEXT: cmp r2, #0
827 ; CHECK-NEXT: csel r0, r0, r2, ne
828 ; CHECK-NEXT: cmp r6, #0
829 ; CHECK-NEXT: csel r3, r4, r6, ne
830 ; CHECK-NEXT: cmp r2, #0
831 ; CHECK-NEXT: csel r1, r1, r2, ne
832 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
833 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
834 ; CHECK-NEXT: vpop {d8, d9}
835 ; CHECK-NEXT: add sp, #4
836 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
838 %conv = fptosi <2 x double> %x to <2 x i128>
839 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
840 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
841 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
842 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
843 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
847 define arm_aapcs_vfpcc <2 x i64> @stest_f32i64(<2 x float> %x) {
848 ; CHECK-LABEL: stest_f32i64:
849 ; CHECK: @ %bb.0: @ %entry
850 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
851 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
852 ; CHECK-NEXT: .pad #4
853 ; CHECK-NEXT: sub sp, #4
854 ; CHECK-NEXT: vmov r9, r0, d0
855 ; CHECK-NEXT: bl __fixsfti
856 ; CHECK-NEXT: subs.w r7, r0, #-1
857 ; CHECK-NEXT: mvn r10, #-2147483648
858 ; CHECK-NEXT: sbcs.w r7, r1, r10
859 ; CHECK-NEXT: mov.w r4, #-1
860 ; CHECK-NEXT: sbcs r7, r2, #0
861 ; CHECK-NEXT: mov.w r11, #-2147483648
862 ; CHECK-NEXT: sbcs r7, r3, #0
863 ; CHECK-NEXT: cset r7, lt
864 ; CHECK-NEXT: cmp r7, #0
865 ; CHECK-NEXT: csel r5, r0, r4, ne
866 ; CHECK-NEXT: csel r3, r3, r7, ne
867 ; CHECK-NEXT: csel r2, r2, r7, ne
868 ; CHECK-NEXT: csel r1, r1, r10, ne
869 ; CHECK-NEXT: rsbs r0, r5, #0
870 ; CHECK-NEXT: sbcs.w r0, r11, r1
871 ; CHECK-NEXT: sbcs.w r0, r4, r2
872 ; CHECK-NEXT: sbcs.w r0, r4, r3
873 ; CHECK-NEXT: cset r6, lt
874 ; CHECK-NEXT: mov r0, r9
875 ; CHECK-NEXT: cmp r6, #0
876 ; CHECK-NEXT: csel r8, r1, r11, ne
877 ; CHECK-NEXT: bl __fixsfti
878 ; CHECK-NEXT: subs.w r7, r0, #-1
879 ; CHECK-NEXT: sbcs.w r7, r1, r10
880 ; CHECK-NEXT: sbcs r7, r2, #0
881 ; CHECK-NEXT: sbcs r7, r3, #0
882 ; CHECK-NEXT: cset r7, lt
883 ; CHECK-NEXT: cmp r7, #0
884 ; CHECK-NEXT: csel r0, r0, r4, ne
885 ; CHECK-NEXT: csel r1, r1, r10, ne
886 ; CHECK-NEXT: csel r3, r3, r7, ne
887 ; CHECK-NEXT: csel r2, r2, r7, ne
888 ; CHECK-NEXT: rsbs r7, r0, #0
889 ; CHECK-NEXT: sbcs.w r7, r11, r1
890 ; CHECK-NEXT: sbcs.w r2, r4, r2
891 ; CHECK-NEXT: sbcs.w r2, r4, r3
892 ; CHECK-NEXT: cset r2, lt
893 ; CHECK-NEXT: cmp r2, #0
894 ; CHECK-NEXT: csel r1, r1, r11, ne
895 ; CHECK-NEXT: cmp r6, #0
896 ; CHECK-NEXT: csel r3, r5, r6, ne
897 ; CHECK-NEXT: cmp r2, #0
898 ; CHECK-NEXT: csel r0, r0, r2, ne
899 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
900 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
901 ; CHECK-NEXT: add sp, #4
902 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
904 %conv = fptosi <2 x float> %x to <2 x i128>
905 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
906 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
907 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
908 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
909 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
913 define arm_aapcs_vfpcc <2 x i64> @utest_f32i64(<2 x float> %x) {
914 ; CHECK-LABEL: utest_f32i64:
915 ; CHECK: @ %bb.0: @ %entry
916 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
917 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
918 ; CHECK-NEXT: .pad #4
919 ; CHECK-NEXT: sub sp, #4
920 ; CHECK-NEXT: vmov r4, r0, d0
921 ; CHECK-NEXT: bl __fixunssfti
922 ; CHECK-NEXT: mov r5, r1
923 ; CHECK-NEXT: subs r1, r2, #1
924 ; CHECK-NEXT: sbcs r1, r3, #0
925 ; CHECK-NEXT: cset r6, lo
926 ; CHECK-NEXT: cmp r6, #0
927 ; CHECK-NEXT: csel r7, r0, r6, ne
928 ; CHECK-NEXT: mov r0, r4
929 ; CHECK-NEXT: bl __fixunssfti
930 ; CHECK-NEXT: subs r2, #1
931 ; CHECK-NEXT: sbcs r2, r3, #0
932 ; CHECK-NEXT: cset r2, lo
933 ; CHECK-NEXT: cmp r2, #0
934 ; CHECK-NEXT: csel r0, r0, r2, ne
935 ; CHECK-NEXT: cmp r6, #0
936 ; CHECK-NEXT: csel r3, r5, r6, ne
937 ; CHECK-NEXT: cmp r2, #0
938 ; CHECK-NEXT: csel r1, r1, r2, ne
939 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
940 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
941 ; CHECK-NEXT: add sp, #4
942 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
944 %conv = fptoui <2 x float> %x to <2 x i128>
945 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
946 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
947 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
951 define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64(<2 x float> %x) {
952 ; CHECK-LABEL: ustest_f32i64:
953 ; CHECK: @ %bb.0: @ %entry
954 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
955 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
956 ; CHECK-NEXT: .pad #4
957 ; CHECK-NEXT: sub sp, #4
958 ; CHECK-NEXT: vmov r6, r0, d0
959 ; CHECK-NEXT: bl __fixsfti
960 ; CHECK-NEXT: subs r5, r2, #1
961 ; CHECK-NEXT: mov.w r8, #1
962 ; CHECK-NEXT: sbcs r5, r3, #0
963 ; CHECK-NEXT: cset r4, lt
964 ; CHECK-NEXT: cmp r4, #0
965 ; CHECK-NEXT: csel r0, r0, r4, ne
966 ; CHECK-NEXT: csel r3, r3, r4, ne
967 ; CHECK-NEXT: csel r5, r1, r4, ne
968 ; CHECK-NEXT: csel r2, r2, r8, ne
969 ; CHECK-NEXT: rsbs r1, r0, #0
970 ; CHECK-NEXT: mov.w r4, #0
971 ; CHECK-NEXT: sbcs.w r1, r4, r5
972 ; CHECK-NEXT: sbcs.w r1, r4, r2
973 ; CHECK-NEXT: sbcs.w r1, r4, r3
974 ; CHECK-NEXT: cset r7, lt
975 ; CHECK-NEXT: cmp r7, #0
976 ; CHECK-NEXT: csel r9, r0, r7, ne
977 ; CHECK-NEXT: mov r0, r6
978 ; CHECK-NEXT: bl __fixsfti
979 ; CHECK-NEXT: subs r6, r2, #1
980 ; CHECK-NEXT: sbcs r6, r3, #0
981 ; CHECK-NEXT: cset r6, lt
982 ; CHECK-NEXT: cmp r6, #0
983 ; CHECK-NEXT: csel r0, r0, r6, ne
984 ; CHECK-NEXT: csel r2, r2, r8, ne
985 ; CHECK-NEXT: csel r3, r3, r6, ne
986 ; CHECK-NEXT: csel r1, r1, r6, ne
987 ; CHECK-NEXT: rsbs r6, r0, #0
988 ; CHECK-NEXT: sbcs.w r6, r4, r1
989 ; CHECK-NEXT: sbcs.w r2, r4, r2
990 ; CHECK-NEXT: sbcs.w r2, r4, r3
991 ; CHECK-NEXT: cset r2, lt
992 ; CHECK-NEXT: cmp r2, #0
993 ; CHECK-NEXT: csel r0, r0, r2, ne
994 ; CHECK-NEXT: cmp r7, #0
995 ; CHECK-NEXT: csel r3, r5, r7, ne
996 ; CHECK-NEXT: cmp r2, #0
997 ; CHECK-NEXT: csel r1, r1, r2, ne
998 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
999 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
1000 ; CHECK-NEXT: add sp, #4
1001 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
1003 %conv = fptosi <2 x float> %x to <2 x i128>
1004 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
1005 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
1006 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
1007 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
1008 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
1009 ret <2 x i64> %conv6
1012 define arm_aapcs_vfpcc <2 x i64> @stest_f16i64(<2 x half> %x) {
1013 ; CHECK-LABEL: stest_f16i64:
1014 ; CHECK: @ %bb.0: @ %entry
1015 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
1016 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
1017 ; CHECK-NEXT: .vsave {d8, d9}
1018 ; CHECK-NEXT: vpush {d8, d9}
1019 ; CHECK-NEXT: vmov.u16 r0, q0[1]
1020 ; CHECK-NEXT: vmov q4, q0
1021 ; CHECK-NEXT: bl __fixhfti
1022 ; CHECK-NEXT: subs.w r7, r0, #-1
1023 ; CHECK-NEXT: mvn r9, #-2147483648
1024 ; CHECK-NEXT: sbcs.w r7, r1, r9
1025 ; CHECK-NEXT: mov.w r10, #-2147483648
1026 ; CHECK-NEXT: sbcs r7, r2, #0
1027 ; CHECK-NEXT: sbcs r7, r3, #0
1028 ; CHECK-NEXT: cset r7, lt
1029 ; CHECK-NEXT: cmp r7, #0
1030 ; CHECK-NEXT: csel r3, r3, r7, ne
1031 ; CHECK-NEXT: csel r2, r2, r7, ne
1032 ; CHECK-NEXT: mov.w r7, #-1
1033 ; CHECK-NEXT: csel r1, r1, r9, ne
1034 ; CHECK-NEXT: csel r4, r0, r7, ne
1035 ; CHECK-NEXT: rsbs r0, r4, #0
1036 ; CHECK-NEXT: sbcs.w r0, r10, r1
1037 ; CHECK-NEXT: sbcs.w r0, r7, r2
1038 ; CHECK-NEXT: sbcs.w r0, r7, r3
1039 ; CHECK-NEXT: cset r5, lt
1040 ; CHECK-NEXT: vmov.u16 r0, q4[0]
1041 ; CHECK-NEXT: cmp r5, #0
1042 ; CHECK-NEXT: csel r8, r1, r10, ne
1043 ; CHECK-NEXT: bl __fixhfti
1044 ; CHECK-NEXT: subs.w r6, r0, #-1
1045 ; CHECK-NEXT: sbcs.w r6, r1, r9
1046 ; CHECK-NEXT: sbcs r6, r2, #0
1047 ; CHECK-NEXT: sbcs r6, r3, #0
1048 ; CHECK-NEXT: cset r6, lt
1049 ; CHECK-NEXT: cmp r6, #0
1050 ; CHECK-NEXT: csel r0, r0, r7, ne
1051 ; CHECK-NEXT: csel r1, r1, r9, ne
1052 ; CHECK-NEXT: csel r3, r3, r6, ne
1053 ; CHECK-NEXT: csel r2, r2, r6, ne
1054 ; CHECK-NEXT: rsbs r6, r0, #0
1055 ; CHECK-NEXT: sbcs.w r6, r10, r1
1056 ; CHECK-NEXT: sbcs.w r2, r7, r2
1057 ; CHECK-NEXT: sbcs.w r2, r7, r3
1058 ; CHECK-NEXT: cset r2, lt
1059 ; CHECK-NEXT: cmp r2, #0
1060 ; CHECK-NEXT: csel r1, r1, r10, ne
1061 ; CHECK-NEXT: cmp r5, #0
1062 ; CHECK-NEXT: csel r3, r4, r5, ne
1063 ; CHECK-NEXT: cmp r2, #0
1064 ; CHECK-NEXT: csel r0, r0, r2, ne
1065 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
1066 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
1067 ; CHECK-NEXT: vpop {d8, d9}
1068 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
1070 %conv = fptosi <2 x half> %x to <2 x i128>
1071 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
1072 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
1073 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
1074 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
1075 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
1076 ret <2 x i64> %conv6
1079 define arm_aapcs_vfpcc <2 x i64> @utesth_f16i64(<2 x half> %x) {
1080 ; CHECK-LABEL: utesth_f16i64:
1081 ; CHECK: @ %bb.0: @ %entry
1082 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1083 ; CHECK-NEXT: push {r4, r5, r7, lr}
1084 ; CHECK-NEXT: .vsave {d8, d9}
1085 ; CHECK-NEXT: vpush {d8, d9}
1086 ; CHECK-NEXT: vmov.u16 r0, q0[1]
1087 ; CHECK-NEXT: vmov q4, q0
1088 ; CHECK-NEXT: bl __fixunshfti
1089 ; CHECK-NEXT: mov r4, r0
1090 ; CHECK-NEXT: vmov.u16 r0, q4[0]
1091 ; CHECK-NEXT: mov r5, r1
1092 ; CHECK-NEXT: bl __fixunshfti
1093 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
1094 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
1095 ; CHECK-NEXT: vpop {d8, d9}
1096 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1098 %conv = fptoui <2 x half> %x to <2 x i128>
1099 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
1100 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
1101 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
1102 ret <2 x i64> %conv6
1105 define arm_aapcs_vfpcc <2 x i64> @ustest_f16i64(<2 x half> %x) {
1106 ; CHECK-LABEL: ustest_f16i64:
1107 ; CHECK: @ %bb.0: @ %entry
1108 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
1109 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
1110 ; CHECK-NEXT: .pad #4
1111 ; CHECK-NEXT: sub sp, #4
1112 ; CHECK-NEXT: .vsave {d8, d9}
1113 ; CHECK-NEXT: vpush {d8, d9}
1114 ; CHECK-NEXT: vmov.u16 r0, q0[1]
1115 ; CHECK-NEXT: vmov q4, q0
1116 ; CHECK-NEXT: bl __fixhfti
1117 ; CHECK-NEXT: subs r5, r2, #1
1118 ; CHECK-NEXT: mov.w r8, #1
1119 ; CHECK-NEXT: sbcs r5, r3, #0
1120 ; CHECK-NEXT: mov.w r7, #0
1121 ; CHECK-NEXT: cset r5, lt
1122 ; CHECK-NEXT: cmp r5, #0
1123 ; CHECK-NEXT: csel r0, r0, r5, ne
1124 ; CHECK-NEXT: csel r3, r3, r5, ne
1125 ; CHECK-NEXT: csel r2, r2, r8, ne
1126 ; CHECK-NEXT: csel r4, r1, r5, ne
1127 ; CHECK-NEXT: rsbs r1, r0, #0
1128 ; CHECK-NEXT: sbcs.w r1, r7, r4
1129 ; CHECK-NEXT: sbcs.w r1, r7, r2
1130 ; CHECK-NEXT: sbcs.w r1, r7, r3
1131 ; CHECK-NEXT: cset r6, lt
1132 ; CHECK-NEXT: cmp r6, #0
1133 ; CHECK-NEXT: csel r9, r0, r6, ne
1134 ; CHECK-NEXT: vmov.u16 r0, q4[0]
1135 ; CHECK-NEXT: bl __fixhfti
1136 ; CHECK-NEXT: subs r5, r2, #1
1137 ; CHECK-NEXT: sbcs r5, r3, #0
1138 ; CHECK-NEXT: cset r5, lt
1139 ; CHECK-NEXT: cmp r5, #0
1140 ; CHECK-NEXT: csel r0, r0, r5, ne
1141 ; CHECK-NEXT: csel r2, r2, r8, ne
1142 ; CHECK-NEXT: csel r3, r3, r5, ne
1143 ; CHECK-NEXT: csel r1, r1, r5, ne
1144 ; CHECK-NEXT: rsbs r5, r0, #0
1145 ; CHECK-NEXT: sbcs.w r5, r7, r1
1146 ; CHECK-NEXT: sbcs.w r2, r7, r2
1147 ; CHECK-NEXT: sbcs.w r2, r7, r3
1148 ; CHECK-NEXT: cset r2, lt
1149 ; CHECK-NEXT: cmp r2, #0
1150 ; CHECK-NEXT: csel r0, r0, r2, ne
1151 ; CHECK-NEXT: cmp r6, #0
1152 ; CHECK-NEXT: csel r3, r4, r6, ne
1153 ; CHECK-NEXT: cmp r2, #0
1154 ; CHECK-NEXT: csel r1, r1, r2, ne
1155 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
1156 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
1157 ; CHECK-NEXT: vpop {d8, d9}
1158 ; CHECK-NEXT: add sp, #4
1159 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
1161 %conv = fptosi <2 x half> %x to <2 x i128>
1162 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
1163 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
1164 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
1165 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
1166 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
1167 ret <2 x i64> %conv6
1174 define arm_aapcs_vfpcc <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
1175 ; CHECK-LABEL: stest_f64i32_mm:
1176 ; CHECK: @ %bb.0: @ %entry
1177 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1178 ; CHECK-NEXT: push {r4, r5, r7, lr}
1179 ; CHECK-NEXT: .vsave {d8, d9}
1180 ; CHECK-NEXT: vpush {d8, d9}
1181 ; CHECK-NEXT: vmov q4, q0
1182 ; CHECK-NEXT: vmov r0, r1, d8
1183 ; CHECK-NEXT: bl __aeabi_d2lz
1184 ; CHECK-NEXT: mov r4, r0
1185 ; CHECK-NEXT: mov r5, r1
1186 ; CHECK-NEXT: vmov r0, r1, d9
1187 ; CHECK-NEXT: bl __aeabi_d2lz
1188 ; CHECK-NEXT: adr r3, .LCPI27_0
1189 ; CHECK-NEXT: mvn r12, #-2147483648
1190 ; CHECK-NEXT: vldrw.u32 q0, [r3]
1191 ; CHECK-NEXT: subs.w r3, r4, r12
1192 ; CHECK-NEXT: sbcs r3, r5, #0
1193 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r0
1194 ; CHECK-NEXT: csetm r3, lt
1195 ; CHECK-NEXT: subs.w r0, r0, r12
1196 ; CHECK-NEXT: sbcs r0, r1, #0
1197 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r1
1198 ; CHECK-NEXT: mov.w r5, #0
1199 ; CHECK-NEXT: csetm r0, lt
1200 ; CHECK-NEXT: bfi r5, r3, #0, #8
1201 ; CHECK-NEXT: mov.w r12, #-1
1202 ; CHECK-NEXT: bfi r5, r0, #8, #8
1203 ; CHECK-NEXT: movs r2, #0
1204 ; CHECK-NEXT: vmsr p0, r5
1205 ; CHECK-NEXT: adr r4, .LCPI27_1
1206 ; CHECK-NEXT: vpsel q0, q1, q0
1207 ; CHECK-NEXT: vldrw.u32 q1, [r4]
1208 ; CHECK-NEXT: vmov r0, r1, d0
1209 ; CHECK-NEXT: vmov r3, r5, d1
1210 ; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
1211 ; CHECK-NEXT: sbcs.w r0, r12, r1
1212 ; CHECK-NEXT: csetm r0, lt
1213 ; CHECK-NEXT: bfi r2, r0, #0, #8
1214 ; CHECK-NEXT: rsbs.w r0, r3, #-2147483648
1215 ; CHECK-NEXT: sbcs.w r0, r12, r5
1216 ; CHECK-NEXT: csetm r0, lt
1217 ; CHECK-NEXT: bfi r2, r0, #8, #8
1218 ; CHECK-NEXT: vmsr p0, r2
1219 ; CHECK-NEXT: vpsel q0, q0, q1
1220 ; CHECK-NEXT: vpop {d8, d9}
1221 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1222 ; CHECK-NEXT: .p2align 4
1223 ; CHECK-NEXT: @ %bb.1:
1224 ; CHECK-NEXT: .LCPI27_0:
1225 ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
1226 ; CHECK-NEXT: .long 0 @ 0x0
1227 ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
1228 ; CHECK-NEXT: .long 0 @ 0x0
1229 ; CHECK-NEXT: .LCPI27_1:
1230 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
1231 ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
1232 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
1233 ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
1235 %conv = fptosi <2 x double> %x to <2 x i64>
1236 %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)
1237 %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>)
1238 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
1239 ret <2 x i32> %conv6
1242 define arm_aapcs_vfpcc <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
1243 ; CHECK-LABEL: utest_f64i32_mm:
1244 ; CHECK: @ %bb.0: @ %entry
1245 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1246 ; CHECK-NEXT: push {r4, r5, r7, lr}
1247 ; CHECK-NEXT: .vsave {d8, d9}
1248 ; CHECK-NEXT: vpush {d8, d9}
1249 ; CHECK-NEXT: vmov q4, q0
1250 ; CHECK-NEXT: vmov r0, r1, d8
1251 ; CHECK-NEXT: bl __aeabi_d2ulz
1252 ; CHECK-NEXT: mov r4, r0
1253 ; CHECK-NEXT: mov r5, r1
1254 ; CHECK-NEXT: vmov r0, r1, d9
1255 ; CHECK-NEXT: bl __aeabi_d2ulz
1256 ; CHECK-NEXT: subs.w r3, r4, #-1
1257 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r0
1258 ; CHECK-NEXT: sbcs r3, r5, #0
1259 ; CHECK-NEXT: mov.w r2, #0
1260 ; CHECK-NEXT: csetm r3, lo
1261 ; CHECK-NEXT: subs.w r0, r0, #-1
1262 ; CHECK-NEXT: sbcs r0, r1, #0
1263 ; CHECK-NEXT: bfi r2, r3, #0, #8
1264 ; CHECK-NEXT: csetm r0, lo
1265 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
1266 ; CHECK-NEXT: bfi r2, r0, #8, #8
1267 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r1
1268 ; CHECK-NEXT: vmsr p0, r2
1269 ; CHECK-NEXT: vpsel q0, q1, q0
1270 ; CHECK-NEXT: vpop {d8, d9}
1271 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1273 %conv = fptoui <2 x double> %x to <2 x i64>
1274 %spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
1275 %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
1276 ret <2 x i32> %conv6
1279 define arm_aapcs_vfpcc <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
1280 ; CHECK-LABEL: ustest_f64i32_mm:
1281 ; CHECK: @ %bb.0: @ %entry
1282 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1283 ; CHECK-NEXT: push {r4, r5, r7, lr}
1284 ; CHECK-NEXT: .vsave {d8, d9}
1285 ; CHECK-NEXT: vpush {d8, d9}
1286 ; CHECK-NEXT: vmov q4, q0
1287 ; CHECK-NEXT: vmov r0, r1, d8
1288 ; CHECK-NEXT: bl __aeabi_d2lz
1289 ; CHECK-NEXT: mov r4, r0
1290 ; CHECK-NEXT: mov r5, r1
1291 ; CHECK-NEXT: vmov r0, r1, d9
1292 ; CHECK-NEXT: bl __aeabi_d2lz
1293 ; CHECK-NEXT: subs.w r3, r4, #-1
1294 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r0
1295 ; CHECK-NEXT: sbcs r3, r5, #0
1296 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r1
1297 ; CHECK-NEXT: csetm r3, lt
1298 ; CHECK-NEXT: subs.w r0, r0, #-1
1299 ; CHECK-NEXT: mov.w r5, #0
1300 ; CHECK-NEXT: sbcs r0, r1, #0
1301 ; CHECK-NEXT: bfi r5, r3, #0, #8
1302 ; CHECK-NEXT: csetm r0, lt
1303 ; CHECK-NEXT: bfi r5, r0, #8, #8
1304 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
1305 ; CHECK-NEXT: vmsr p0, r5
1306 ; CHECK-NEXT: movs r2, #0
1307 ; CHECK-NEXT: vpsel q0, q1, q0
1308 ; CHECK-NEXT: vmov.i32 q1, #0x0
1309 ; CHECK-NEXT: vmov r0, r1, d0
1310 ; CHECK-NEXT: vmov r3, r5, d1
1311 ; CHECK-NEXT: rsbs r0, r0, #0
1312 ; CHECK-NEXT: sbcs.w r0, r2, r1
1313 ; CHECK-NEXT: csetm r0, lt
1314 ; CHECK-NEXT: rsbs r1, r3, #0
1315 ; CHECK-NEXT: sbcs.w r1, r2, r5
1316 ; CHECK-NEXT: bfi r2, r0, #0, #8
1317 ; CHECK-NEXT: csetm r0, lt
1318 ; CHECK-NEXT: bfi r2, r0, #8, #8
1319 ; CHECK-NEXT: vmsr p0, r2
1320 ; CHECK-NEXT: vpsel q0, q0, q1
1321 ; CHECK-NEXT: vpop {d8, d9}
1322 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1324 %conv = fptosi <2 x double> %x to <2 x i64>
1325 %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
1326 %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer)
1327 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
1328 ret <2 x i32> %conv6
1331 define arm_aapcs_vfpcc <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
1332 ; CHECK-LABEL: stest_f32i32_mm:
1333 ; CHECK: @ %bb.0: @ %entry
1334 ; CHECK-NEXT: vcvt.s32.f32 q0, q0
1337 %conv = fptosi <4 x float> %x to <4 x i64>
1338 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
1339 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
1340 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
1341 ret <4 x i32> %conv6
1344 define arm_aapcs_vfpcc <4 x i32> @utest_f32i32_mm(<4 x float> %x) {
1345 ; CHECK-LABEL: utest_f32i32_mm:
1346 ; CHECK: @ %bb.0: @ %entry
1347 ; CHECK-NEXT: vcvt.u32.f32 q0, q0
1350 %conv = fptoui <4 x float> %x to <4 x i64>
1351 %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
1352 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
1353 ret <4 x i32> %conv6
1356 define arm_aapcs_vfpcc <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
1357 ; CHECK-LABEL: ustest_f32i32_mm:
1358 ; CHECK: @ %bb.0: @ %entry
1359 ; CHECK-NEXT: vcvt.u32.f32 q0, q0
1362 %conv = fptosi <4 x float> %x to <4 x i64>
1363 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
1364 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)
1365 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
1366 ret <4 x i32> %conv6
1369 define arm_aapcs_vfpcc <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
1370 ; CHECK-LABEL: stest_f16i32_mm:
1371 ; CHECK: @ %bb.0: @ %entry
1372 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1373 ; CHECK-NEXT: push {r4, r5, r7, lr}
1374 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1375 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
1376 ; CHECK-NEXT: vmov.u16 r0, q0[3]
1377 ; CHECK-NEXT: vmov q4, q0
1378 ; CHECK-NEXT: bl __fixhfdi
1379 ; CHECK-NEXT: mov r4, r0
1380 ; CHECK-NEXT: vmov.u16 r0, q4[0]
1381 ; CHECK-NEXT: bl __fixhfdi
1382 ; CHECK-NEXT: mov r5, r0
1383 ; CHECK-NEXT: vmov.u16 r0, q4[2]
1384 ; CHECK-NEXT: bl __fixhfdi
1385 ; CHECK-NEXT: vmov q5[2], q5[0], r5, r0
1386 ; CHECK-NEXT: vmov.u16 r0, q4[1]
1387 ; CHECK-NEXT: bl __fixhfdi
1388 ; CHECK-NEXT: vmov q5[3], q5[1], r0, r4
1389 ; CHECK-NEXT: vmov q0, q5
1390 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
1391 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1393 %conv = fptosi <4 x half> %x to <4 x i64>
1394 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
1395 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
1396 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
1397 ret <4 x i32> %conv6
1400 define arm_aapcs_vfpcc <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
1401 ; CHECK-LABEL: utesth_f16i32_mm:
1402 ; CHECK: @ %bb.0: @ %entry
1403 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1404 ; CHECK-NEXT: push {r4, r5, r7, lr}
1405 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1406 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
1407 ; CHECK-NEXT: vmov.u16 r0, q0[3]
1408 ; CHECK-NEXT: vmov q4, q0
1409 ; CHECK-NEXT: bl __fixunshfdi
1410 ; CHECK-NEXT: mov r4, r0
1411 ; CHECK-NEXT: vmov.u16 r0, q4[0]
1412 ; CHECK-NEXT: bl __fixunshfdi
1413 ; CHECK-NEXT: mov r5, r0
1414 ; CHECK-NEXT: vmov.u16 r0, q4[2]
1415 ; CHECK-NEXT: bl __fixunshfdi
1416 ; CHECK-NEXT: vmov q5[2], q5[0], r5, r0
1417 ; CHECK-NEXT: vmov.u16 r0, q4[1]
1418 ; CHECK-NEXT: bl __fixunshfdi
1419 ; CHECK-NEXT: vmov q5[3], q5[1], r0, r4
1420 ; CHECK-NEXT: vmov q0, q5
1421 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
1422 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1424 %conv = fptoui <4 x half> %x to <4 x i64>
1425 %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
1426 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
1427 ret <4 x i32> %conv6
1430 define arm_aapcs_vfpcc <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
1431 ; CHECK-LABEL: ustest_f16i32_mm:
1432 ; CHECK: @ %bb.0: @ %entry
1433 ; CHECK-NEXT: .save {r4, r5, r6, lr}
1434 ; CHECK-NEXT: push {r4, r5, r6, lr}
1435 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
1436 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
1437 ; CHECK-NEXT: vmov.u16 r0, q0[3]
1438 ; CHECK-NEXT: vmov q4, q0
1439 ; CHECK-NEXT: bl __fixhfdi
1440 ; CHECK-NEXT: mov r4, r0
1441 ; CHECK-NEXT: vmov.u16 r0, q4[2]
1442 ; CHECK-NEXT: mov r5, r1
1443 ; CHECK-NEXT: bl __fixhfdi
1444 ; CHECK-NEXT: rsbs r2, r0, #0
1445 ; CHECK-NEXT: mov.w r6, #0
1446 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
1447 ; CHECK-NEXT: sbcs.w r0, r6, r1
1448 ; CHECK-NEXT: csetm r0, lt
1449 ; CHECK-NEXT: movs r1, #0
1450 ; CHECK-NEXT: bfi r1, r0, #0, #8
1451 ; CHECK-NEXT: rsbs r0, r4, #0
1452 ; CHECK-NEXT: sbcs.w r0, r6, r5
1453 ; CHECK-NEXT: vmov.i32 q5, #0x0
1454 ; CHECK-NEXT: csetm r0, lt
1455 ; CHECK-NEXT: bfi r1, r0, #8, #8
1456 ; CHECK-NEXT: vmov.u16 r0, q4[1]
1457 ; CHECK-NEXT: vmsr p0, r1
1458 ; CHECK-NEXT: vpsel q6, q0, q5
1459 ; CHECK-NEXT: bl __fixhfdi
1460 ; CHECK-NEXT: mov r4, r0
1461 ; CHECK-NEXT: vmov.u16 r0, q4[0]
1462 ; CHECK-NEXT: mov r5, r1
1463 ; CHECK-NEXT: bl __fixhfdi
1464 ; CHECK-NEXT: rsbs r2, r0, #0
1465 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
1466 ; CHECK-NEXT: sbcs.w r0, r6, r1
1467 ; CHECK-NEXT: csetm r0, lt
1468 ; CHECK-NEXT: rsbs r1, r4, #0
1469 ; CHECK-NEXT: sbcs.w r1, r6, r5
1470 ; CHECK-NEXT: bfi r6, r0, #0, #8
1471 ; CHECK-NEXT: csetm r0, lt
1472 ; CHECK-NEXT: bfi r6, r0, #8, #8
1473 ; CHECK-NEXT: vmsr p0, r6
1474 ; CHECK-NEXT: vpsel q0, q0, q5
1475 ; CHECK-NEXT: vmov.f32 s1, s2
1476 ; CHECK-NEXT: vmov.f32 s2, s24
1477 ; CHECK-NEXT: vmov.f32 s3, s26
1478 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
1479 ; CHECK-NEXT: pop {r4, r5, r6, pc}
1481 %conv = fptosi <4 x half> %x to <4 x i64>
1482 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
1483 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)
1484 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
1485 ret <4 x i32> %conv6
1490 define arm_aapcs_vfpcc <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
1491 ; CHECK-LABEL: stest_f64i16_mm:
1492 ; CHECK: @ %bb.0: @ %entry
1493 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1494 ; CHECK-NEXT: push {r4, r5, r7, lr}
1495 ; CHECK-NEXT: .vsave {d8, d9}
1496 ; CHECK-NEXT: vpush {d8, d9}
1497 ; CHECK-NEXT: vmov q4, q0
1498 ; CHECK-NEXT: vmov r0, r1, d9
1499 ; CHECK-NEXT: bl __aeabi_d2lz
1500 ; CHECK-NEXT: mov r4, r0
1501 ; CHECK-NEXT: mov r5, r1
1502 ; CHECK-NEXT: vmov r0, r1, d8
1503 ; CHECK-NEXT: bl __aeabi_d2lz
1504 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
1505 ; CHECK-NEXT: movw r4, #32767
1506 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
1507 ; CHECK-NEXT: adr.w r12, .LCPI36_0
1508 ; CHECK-NEXT: vmov r1, r2, d0
1509 ; CHECK-NEXT: vldrw.u32 q1, [r12]
1510 ; CHECK-NEXT: vmov r3, r5, d1
1511 ; CHECK-NEXT: movw lr, #32768
1512 ; CHECK-NEXT: movt lr, #65535
1513 ; CHECK-NEXT: mov.w r12, #-1
1514 ; CHECK-NEXT: movs r0, #0
1515 ; CHECK-NEXT: subs r1, r1, r4
1516 ; CHECK-NEXT: sbcs r1, r2, #0
1517 ; CHECK-NEXT: mov.w r2, #0
1518 ; CHECK-NEXT: csetm r1, lt
1519 ; CHECK-NEXT: bfi r2, r1, #0, #8
1520 ; CHECK-NEXT: subs r1, r3, r4
1521 ; CHECK-NEXT: sbcs r1, r5, #0
1522 ; CHECK-NEXT: adr r4, .LCPI36_1
1523 ; CHECK-NEXT: csetm r1, lt
1524 ; CHECK-NEXT: bfi r2, r1, #8, #8
1525 ; CHECK-NEXT: vmsr p0, r2
1526 ; CHECK-NEXT: vpsel q0, q0, q1
1527 ; CHECK-NEXT: vldrw.u32 q1, [r4]
1528 ; CHECK-NEXT: vmov r1, r2, d0
1529 ; CHECK-NEXT: vmov r3, r5, d1
1530 ; CHECK-NEXT: subs.w r1, lr, r1
1531 ; CHECK-NEXT: sbcs.w r1, r12, r2
1532 ; CHECK-NEXT: csetm r1, lt
1533 ; CHECK-NEXT: bfi r0, r1, #0, #8
1534 ; CHECK-NEXT: subs.w r1, lr, r3
1535 ; CHECK-NEXT: sbcs.w r1, r12, r5
1536 ; CHECK-NEXT: csetm r1, lt
1537 ; CHECK-NEXT: bfi r0, r1, #8, #8
1538 ; CHECK-NEXT: vmsr p0, r0
1539 ; CHECK-NEXT: vpsel q0, q0, q1
1540 ; CHECK-NEXT: vpop {d8, d9}
1541 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1542 ; CHECK-NEXT: .p2align 4
1543 ; CHECK-NEXT: @ %bb.1:
1544 ; CHECK-NEXT: .LCPI36_0:
1545 ; CHECK-NEXT: .long 32767 @ 0x7fff
1546 ; CHECK-NEXT: .long 0 @ 0x0
1547 ; CHECK-NEXT: .long 32767 @ 0x7fff
1548 ; CHECK-NEXT: .long 0 @ 0x0
1549 ; CHECK-NEXT: .LCPI36_1:
1550 ; CHECK-NEXT: .long 4294934528 @ 0xffff8000
1551 ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
1552 ; CHECK-NEXT: .long 4294934528 @ 0xffff8000
1553 ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
1555 %conv = fptosi <2 x double> %x to <2 x i32>
1556 %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>)
1557 %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>)
1558 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
1559 ret <2 x i16> %conv6
1562 define arm_aapcs_vfpcc <2 x i16> @utest_f64i16_mm(<2 x double> %x) {
1563 ; CHECK-LABEL: utest_f64i16_mm:
1564 ; CHECK: @ %bb.0: @ %entry
1565 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1566 ; CHECK-NEXT: push {r4, r5, r7, lr}
1567 ; CHECK-NEXT: .vsave {d8, d9}
1568 ; CHECK-NEXT: vpush {d8, d9}
1569 ; CHECK-NEXT: vmov q4, q0
1570 ; CHECK-NEXT: vmov r0, r1, d9
1571 ; CHECK-NEXT: bl __aeabi_d2ulz
1572 ; CHECK-NEXT: mov r4, r0
1573 ; CHECK-NEXT: mov r5, r1
1574 ; CHECK-NEXT: vmov r0, r1, d8
1575 ; CHECK-NEXT: bl __aeabi_d2ulz
1576 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
1577 ; CHECK-NEXT: movw r4, #65535
1578 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
1579 ; CHECK-NEXT: movs r5, #0
1580 ; CHECK-NEXT: vmov r0, r1, d0
1581 ; CHECK-NEXT: vmov.i64 q1, #0xffff
1582 ; CHECK-NEXT: vmov r2, r3, d1
1583 ; CHECK-NEXT: subs r0, r0, r4
1584 ; CHECK-NEXT: sbcs r0, r1, #0
1585 ; CHECK-NEXT: csetm r0, lo
1586 ; CHECK-NEXT: bfi r5, r0, #0, #8
1587 ; CHECK-NEXT: subs r0, r2, r4
1588 ; CHECK-NEXT: sbcs r0, r3, #0
1589 ; CHECK-NEXT: csetm r0, lo
1590 ; CHECK-NEXT: bfi r5, r0, #8, #8
1591 ; CHECK-NEXT: vmsr p0, r5
1592 ; CHECK-NEXT: vpsel q0, q0, q1
1593 ; CHECK-NEXT: vpop {d8, d9}
1594 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1596 %conv = fptoui <2 x double> %x to <2 x i32>
1597 %spec.store.select = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)
1598 %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>
1599 ret <2 x i16> %conv6
1602 define arm_aapcs_vfpcc <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
1603 ; CHECK-LABEL: ustest_f64i16_mm:
1604 ; CHECK: @ %bb.0: @ %entry
1605 ; CHECK-NEXT: .save {r4, r5, r7, lr}
1606 ; CHECK-NEXT: push {r4, r5, r7, lr}
1607 ; CHECK-NEXT: .vsave {d8, d9}
1608 ; CHECK-NEXT: vpush {d8, d9}
1609 ; CHECK-NEXT: vmov q4, q0
1610 ; CHECK-NEXT: vmov r0, r1, d9
1611 ; CHECK-NEXT: bl __aeabi_d2lz
1612 ; CHECK-NEXT: mov r4, r0
1613 ; CHECK-NEXT: mov r5, r1
1614 ; CHECK-NEXT: vmov r0, r1, d8
1615 ; CHECK-NEXT: bl __aeabi_d2lz
1616 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
1617 ; CHECK-NEXT: movw r4, #65535
1618 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
1619 ; CHECK-NEXT: vmov.i64 q1, #0xffff
1620 ; CHECK-NEXT: vmov r1, r2, d0
1621 ; CHECK-NEXT: movs r0, #0
1622 ; CHECK-NEXT: vmov r3, r5, d1
1623 ; CHECK-NEXT: subs r1, r1, r4
1624 ; CHECK-NEXT: sbcs r1, r2, #0
1625 ; CHECK-NEXT: mov.w r2, #0
1626 ; CHECK-NEXT: csetm r1, lt
1627 ; CHECK-NEXT: bfi r2, r1, #0, #8
1628 ; CHECK-NEXT: subs r1, r3, r4
1629 ; CHECK-NEXT: sbcs r1, r5, #0
1630 ; CHECK-NEXT: csetm r1, lt
1631 ; CHECK-NEXT: bfi r2, r1, #8, #8
1632 ; CHECK-NEXT: vmsr p0, r2
1633 ; CHECK-NEXT: vpsel q0, q0, q1
1634 ; CHECK-NEXT: vmov.i32 q1, #0x0
1635 ; CHECK-NEXT: vmov r1, r2, d0
1636 ; CHECK-NEXT: vmov r3, r5, d1
1637 ; CHECK-NEXT: rsbs r1, r1, #0
1638 ; CHECK-NEXT: sbcs.w r1, r0, r2
1639 ; CHECK-NEXT: csetm r1, lt
1640 ; CHECK-NEXT: rsbs r2, r3, #0
1641 ; CHECK-NEXT: sbcs.w r2, r0, r5
1642 ; CHECK-NEXT: bfi r0, r1, #0, #8
1643 ; CHECK-NEXT: csetm r1, lt
1644 ; CHECK-NEXT: bfi r0, r1, #8, #8
1645 ; CHECK-NEXT: vmsr p0, r0
1646 ; CHECK-NEXT: vpsel q0, q0, q1
1647 ; CHECK-NEXT: vpop {d8, d9}
1648 ; CHECK-NEXT: pop {r4, r5, r7, pc}
1650 %conv = fptosi <2 x double> %x to <2 x i32>
1651 %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)
1652 %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer)
1653 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
1654 ret <2 x i16> %conv6
1657 define arm_aapcs_vfpcc <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
1658 ; CHECK-LABEL: stest_f32i16_mm:
1659 ; CHECK: @ %bb.0: @ %entry
1660 ; CHECK-NEXT: vcvt.s32.f32 q0, q0
1661 ; CHECK-NEXT: vqmovnb.s32 q0, q0
1662 ; CHECK-NEXT: vmovlb.s16 q0, q0
1665 %conv = fptosi <4 x float> %x to <4 x i32>
1666 %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
1667 %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
1668 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
1669 ret <4 x i16> %conv6
1672 define arm_aapcs_vfpcc <4 x i16> @utest_f32i16_mm(<4 x float> %x) {
1673 ; CHECK-LABEL: utest_f32i16_mm:
1674 ; CHECK: @ %bb.0: @ %entry
1675 ; CHECK-NEXT: vcvt.u32.f32 q0, q0
1676 ; CHECK-NEXT: vqmovnb.u32 q0, q0
1677 ; CHECK-NEXT: vmovlb.u16 q0, q0
1680 %conv = fptoui <4 x float> %x to <4 x i32>
1681 %spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
1682 %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
1683 ret <4 x i16> %conv6
1686 define arm_aapcs_vfpcc <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
1687 ; CHECK-LABEL: ustest_f32i16_mm:
1688 ; CHECK: @ %bb.0: @ %entry
1689 ; CHECK-NEXT: vmov.i32 q1, #0xffff
1690 ; CHECK-NEXT: vcvt.s32.f32 q0, q0
1691 ; CHECK-NEXT: vmov.i32 q2, #0x0
1692 ; CHECK-NEXT: vmin.s32 q0, q0, q1
1693 ; CHECK-NEXT: vmax.s32 q0, q0, q2
1696 %conv = fptosi <4 x float> %x to <4 x i32>
1697 %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
1698 %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
1699 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
1700 ret <4 x i16> %conv6
1703 define arm_aapcs_vfpcc <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
1704 ; CHECK-LABEL: stest_f16i16_mm:
1705 ; CHECK: @ %bb.0: @ %entry
1706 ; CHECK-NEXT: vcvt.s16.f16 q0, q0
1709 %conv = fptosi <8 x half> %x to <8 x i32>
1710 %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
1711 %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
1712 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
1713 ret <8 x i16> %conv6
1716 define arm_aapcs_vfpcc <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
1717 ; CHECK-LABEL: utesth_f16i16_mm:
1718 ; CHECK: @ %bb.0: @ %entry
1719 ; CHECK-NEXT: vmovx.f16 s6, s2
1720 ; CHECK-NEXT: vcvt.u32.f16 s12, s2
1721 ; CHECK-NEXT: vmovx.f16 s2, s0
1722 ; CHECK-NEXT: vcvt.u32.f16 s0, s0
1723 ; CHECK-NEXT: vcvt.u32.f16 s14, s2
1724 ; CHECK-NEXT: vmov r0, s0
1725 ; CHECK-NEXT: vmovx.f16 s4, s3
1726 ; CHECK-NEXT: vmovx.f16 s10, s1
1727 ; CHECK-NEXT: vcvt.u32.f16 s8, s3
1728 ; CHECK-NEXT: vcvt.u32.f16 s5, s1
1729 ; CHECK-NEXT: vmov.16 q0[0], r0
1730 ; CHECK-NEXT: vmov r0, s14
1731 ; CHECK-NEXT: vmov.16 q0[1], r0
1732 ; CHECK-NEXT: vmov r0, s5
1733 ; CHECK-NEXT: vcvt.u32.f16 s10, s10
1734 ; CHECK-NEXT: vmov.16 q0[2], r0
1735 ; CHECK-NEXT: vmov r0, s10
1736 ; CHECK-NEXT: vcvt.u32.f16 s6, s6
1737 ; CHECK-NEXT: vmov.16 q0[3], r0
1738 ; CHECK-NEXT: vmov r0, s12
1739 ; CHECK-NEXT: vmov.16 q0[4], r0
1740 ; CHECK-NEXT: vmov r0, s6
1741 ; CHECK-NEXT: vmov.16 q0[5], r0
1742 ; CHECK-NEXT: vmov r0, s8
1743 ; CHECK-NEXT: vcvt.u32.f16 s4, s4
1744 ; CHECK-NEXT: vmov.16 q0[6], r0
1745 ; CHECK-NEXT: vmov r0, s4
1746 ; CHECK-NEXT: vmov.16 q0[7], r0
1749 %conv = fptoui <8 x half> %x to <8 x i32>
1750 %spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
1751 %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
1752 ret <8 x i16> %conv6
1755 define arm_aapcs_vfpcc <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
1756 ; CHECK-LABEL: ustest_f16i16_mm:
1757 ; CHECK: @ %bb.0: @ %entry
1758 ; CHECK-NEXT: .vsave {d8, d9}
1759 ; CHECK-NEXT: vpush {d8, d9}
1760 ; CHECK-NEXT: .pad #16
1761 ; CHECK-NEXT: sub sp, #16
1762 ; CHECK-NEXT: vmovx.f16 s6, s0
1763 ; CHECK-NEXT: vcvt.s32.f16 s10, s0
1764 ; CHECK-NEXT: vmovx.f16 s0, s3
1765 ; CHECK-NEXT: vcvt.s32.f16 s5, s3
1766 ; CHECK-NEXT: vcvt.s32.f16 s12, s0
1767 ; CHECK-NEXT: vmovx.f16 s0, s2
1768 ; CHECK-NEXT: vcvt.s32.f16 s7, s2
1769 ; CHECK-NEXT: vcvt.s32.f16 s14, s0
1770 ; CHECK-NEXT: vmov r1, s5
1771 ; CHECK-NEXT: vmovx.f16 s4, s1
1772 ; CHECK-NEXT: vmov r2, s7
1773 ; CHECK-NEXT: vcvt.s32.f16 s8, s1
1774 ; CHECK-NEXT: vmov q4[2], q4[0], r2, r1
1775 ; CHECK-NEXT: vmov r1, s12
1776 ; CHECK-NEXT: vmov r2, s14
1777 ; CHECK-NEXT: vcvt.s32.f16 s4, s4
1778 ; CHECK-NEXT: vmov q4[3], q4[1], r2, r1
1779 ; CHECK-NEXT: vcvt.s32.f16 s6, s6
1780 ; CHECK-NEXT: vmov r1, s8
1781 ; CHECK-NEXT: vmov.i32 q0, #0x0
1782 ; CHECK-NEXT: vmov r2, s10
1783 ; CHECK-NEXT: mov r0, sp
1784 ; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
1785 ; CHECK-NEXT: vmov r1, s4
1786 ; CHECK-NEXT: vmov r2, s6
1787 ; CHECK-NEXT: vmax.s32 q3, q4, q0
1788 ; CHECK-NEXT: vmov q2[3], q2[1], r2, r1
1789 ; CHECK-NEXT: vstrh.32 q3, [r0, #8]
1790 ; CHECK-NEXT: vmax.s32 q0, q2, q0
1791 ; CHECK-NEXT: vstrh.32 q0, [r0]
1792 ; CHECK-NEXT: vldrw.u32 q0, [r0]
1793 ; CHECK-NEXT: add sp, #16
1794 ; CHECK-NEXT: vpop {d8, d9}
1797 %conv = fptosi <8 x half> %x to <8 x i32>
1798 %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
1799 %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer)
1800 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
1801 ret <8 x i16> %conv6
1806 define arm_aapcs_vfpcc <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
1807 ; CHECK-LABEL: stest_f64i64_mm:
1808 ; CHECK: @ %bb.0: @ %entry
1809 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
1810 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
1811 ; CHECK-NEXT: .vsave {d8, d9}
1812 ; CHECK-NEXT: vpush {d8, d9}
1813 ; CHECK-NEXT: vmov q4, q0
1814 ; CHECK-NEXT: vmov r0, r1, d9
1815 ; CHECK-NEXT: bl __fixdfti
1816 ; CHECK-NEXT: vmov r12, lr, d8
1817 ; CHECK-NEXT: subs.w r4, r0, #-1
1818 ; CHECK-NEXT: mvn r9, #-2147483648
1819 ; CHECK-NEXT: sbcs.w r4, r1, r9
1820 ; CHECK-NEXT: sbcs r4, r2, #0
1821 ; CHECK-NEXT: mov.w r7, #-1
1822 ; CHECK-NEXT: sbcs r4, r3, #0
1823 ; CHECK-NEXT: mov.w r10, #-2147483648
1824 ; CHECK-NEXT: cset r4, lt
1825 ; CHECK-NEXT: cmp r4, #0
1826 ; CHECK-NEXT: csel r3, r3, r4, ne
1827 ; CHECK-NEXT: csel r2, r2, r4, ne
1828 ; CHECK-NEXT: csel r4, r0, r7, ne
1829 ; CHECK-NEXT: csel r1, r1, r9, ne
1830 ; CHECK-NEXT: rsbs r0, r4, #0
1831 ; CHECK-NEXT: sbcs.w r0, r10, r1
1832 ; CHECK-NEXT: sbcs.w r0, r7, r2
1833 ; CHECK-NEXT: sbcs.w r0, r7, r3
1834 ; CHECK-NEXT: cset r5, lt
1835 ; CHECK-NEXT: cmp r5, #0
1836 ; CHECK-NEXT: csel r8, r1, r10, ne
1837 ; CHECK-NEXT: mov r0, r12
1838 ; CHECK-NEXT: mov r1, lr
1839 ; CHECK-NEXT: bl __fixdfti
1840 ; CHECK-NEXT: subs.w r6, r0, #-1
1841 ; CHECK-NEXT: sbcs.w r6, r1, r9
1842 ; CHECK-NEXT: sbcs r6, r2, #0
1843 ; CHECK-NEXT: sbcs r6, r3, #0
1844 ; CHECK-NEXT: cset r6, lt
1845 ; CHECK-NEXT: cmp r6, #0
1846 ; CHECK-NEXT: csel r0, r0, r7, ne
1847 ; CHECK-NEXT: csel r1, r1, r9, ne
1848 ; CHECK-NEXT: csel r3, r3, r6, ne
1849 ; CHECK-NEXT: csel r2, r2, r6, ne
1850 ; CHECK-NEXT: rsbs r6, r0, #0
1851 ; CHECK-NEXT: sbcs.w r6, r10, r1
1852 ; CHECK-NEXT: sbcs.w r2, r7, r2
1853 ; CHECK-NEXT: sbcs.w r2, r7, r3
1854 ; CHECK-NEXT: cset r2, lt
1855 ; CHECK-NEXT: cmp r2, #0
1856 ; CHECK-NEXT: csel r1, r1, r10, ne
1857 ; CHECK-NEXT: cmp r5, #0
1858 ; CHECK-NEXT: csel r3, r4, r5, ne
1859 ; CHECK-NEXT: cmp r2, #0
1860 ; CHECK-NEXT: csel r0, r0, r2, ne
1861 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
1862 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
1863 ; CHECK-NEXT: vpop {d8, d9}
1864 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
1866 %conv = fptosi <2 x double> %x to <2 x i128>
1867 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
1868 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
1869 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
1870 ret <2 x i64> %conv6
1873 define arm_aapcs_vfpcc <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
1874 ; CHECK-LABEL: utest_f64i64_mm:
1875 ; CHECK: @ %bb.0: @ %entry
1876 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
1877 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
1878 ; CHECK-NEXT: .pad #4
1879 ; CHECK-NEXT: sub sp, #4
1880 ; CHECK-NEXT: .vsave {d8, d9}
1881 ; CHECK-NEXT: vpush {d8, d9}
1882 ; CHECK-NEXT: vmov q4, q0
1883 ; CHECK-NEXT: vmov r0, r1, d9
1884 ; CHECK-NEXT: bl __fixunsdfti
1885 ; CHECK-NEXT: mov r5, r1
1886 ; CHECK-NEXT: vmov r4, r1, d8
1887 ; CHECK-NEXT: subs r2, #1
1888 ; CHECK-NEXT: sbcs r2, r3, #0
1889 ; CHECK-NEXT: cset r6, lo
1890 ; CHECK-NEXT: cmp r6, #0
1891 ; CHECK-NEXT: csel r7, r0, r6, ne
1892 ; CHECK-NEXT: mov r0, r4
1893 ; CHECK-NEXT: bl __fixunsdfti
1894 ; CHECK-NEXT: subs r2, #1
1895 ; CHECK-NEXT: sbcs r2, r3, #0
1896 ; CHECK-NEXT: cset r2, lo
1897 ; CHECK-NEXT: cmp r2, #0
1898 ; CHECK-NEXT: csel r0, r0, r2, ne
1899 ; CHECK-NEXT: cmp r6, #0
1900 ; CHECK-NEXT: csel r3, r5, r6, ne
1901 ; CHECK-NEXT: cmp r2, #0
1902 ; CHECK-NEXT: csel r1, r1, r2, ne
1903 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
1904 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
1905 ; CHECK-NEXT: vpop {d8, d9}
1906 ; CHECK-NEXT: add sp, #4
1907 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
1909 %conv = fptoui <2 x double> %x to <2 x i128>
1910 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
1911 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
1912 ret <2 x i64> %conv6
1915 define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
1916 ; CHECK-LABEL: ustest_f64i64_mm:
1917 ; CHECK: @ %bb.0: @ %entry
1918 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
1919 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
1920 ; CHECK-NEXT: .vsave {d8, d9}
1921 ; CHECK-NEXT: vpush {d8, d9}
1922 ; CHECK-NEXT: vmov q4, q0
1923 ; CHECK-NEXT: vmov r0, r1, d9
1924 ; CHECK-NEXT: bl __fixdfti
1925 ; CHECK-NEXT: mov r8, r1
1926 ; CHECK-NEXT: vmov r4, r1, d8
1927 ; CHECK-NEXT: subs r2, #1
1928 ; CHECK-NEXT: sbcs r2, r3, #0
1929 ; CHECK-NEXT: cset r7, lt
1930 ; CHECK-NEXT: cmp r7, #0
1931 ; CHECK-NEXT: csel r6, r0, r7, ne
1932 ; CHECK-NEXT: csel r5, r3, r7, ne
1933 ; CHECK-NEXT: cmp r5, #0
1935 ; CHECK-NEXT: movmi r6, #0
1936 ; CHECK-NEXT: mov r0, r4
1937 ; CHECK-NEXT: bl __fixdfti
1938 ; CHECK-NEXT: subs r2, #1
1939 ; CHECK-NEXT: sbcs r2, r3, #0
1940 ; CHECK-NEXT: cset r2, lt
1941 ; CHECK-NEXT: cmp r2, #0
1942 ; CHECK-NEXT: csel r3, r3, r2, ne
1943 ; CHECK-NEXT: csel r0, r0, r2, ne
1944 ; CHECK-NEXT: cmp r3, #0
1946 ; CHECK-NEXT: movmi r0, #0
1947 ; CHECK-NEXT: cmp r7, #0
1948 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r6
1949 ; CHECK-NEXT: csel r7, r8, r7, ne
1950 ; CHECK-NEXT: cmp r5, #0
1952 ; CHECK-NEXT: movmi r7, #0
1953 ; CHECK-NEXT: cmp r2, #0
1954 ; CHECK-NEXT: csel r1, r1, r2, ne
1955 ; CHECK-NEXT: cmp r3, #0
1957 ; CHECK-NEXT: movmi r1, #0
1958 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r7
1959 ; CHECK-NEXT: vpop {d8, d9}
1960 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
1962 %conv = fptosi <2 x double> %x to <2 x i128>
1963 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
1964 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
1965 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
1966 ret <2 x i64> %conv6
1969 define arm_aapcs_vfpcc <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
1970 ; CHECK-LABEL: stest_f32i64_mm:
1971 ; CHECK: @ %bb.0: @ %entry
1972 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
1973 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
1974 ; CHECK-NEXT: .pad #4
1975 ; CHECK-NEXT: sub sp, #4
1976 ; CHECK-NEXT: vmov r9, r0, d0
1977 ; CHECK-NEXT: bl __fixsfti
1978 ; CHECK-NEXT: subs.w r7, r0, #-1
1979 ; CHECK-NEXT: mvn r10, #-2147483648
1980 ; CHECK-NEXT: sbcs.w r7, r1, r10
1981 ; CHECK-NEXT: mov.w r4, #-1
1982 ; CHECK-NEXT: sbcs r7, r2, #0
1983 ; CHECK-NEXT: mov.w r11, #-2147483648
1984 ; CHECK-NEXT: sbcs r7, r3, #0
1985 ; CHECK-NEXT: cset r7, lt
1986 ; CHECK-NEXT: cmp r7, #0
1987 ; CHECK-NEXT: csel r5, r0, r4, ne
1988 ; CHECK-NEXT: csel r3, r3, r7, ne
1989 ; CHECK-NEXT: csel r2, r2, r7, ne
1990 ; CHECK-NEXT: csel r1, r1, r10, ne
1991 ; CHECK-NEXT: rsbs r0, r5, #0
1992 ; CHECK-NEXT: sbcs.w r0, r11, r1
1993 ; CHECK-NEXT: sbcs.w r0, r4, r2
1994 ; CHECK-NEXT: sbcs.w r0, r4, r3
1995 ; CHECK-NEXT: cset r6, lt
1996 ; CHECK-NEXT: mov r0, r9
1997 ; CHECK-NEXT: cmp r6, #0
1998 ; CHECK-NEXT: csel r8, r1, r11, ne
1999 ; CHECK-NEXT: bl __fixsfti
2000 ; CHECK-NEXT: subs.w r7, r0, #-1
2001 ; CHECK-NEXT: sbcs.w r7, r1, r10
2002 ; CHECK-NEXT: sbcs r7, r2, #0
2003 ; CHECK-NEXT: sbcs r7, r3, #0
2004 ; CHECK-NEXT: cset r7, lt
2005 ; CHECK-NEXT: cmp r7, #0
2006 ; CHECK-NEXT: csel r0, r0, r4, ne
2007 ; CHECK-NEXT: csel r1, r1, r10, ne
2008 ; CHECK-NEXT: csel r3, r3, r7, ne
2009 ; CHECK-NEXT: csel r2, r2, r7, ne
2010 ; CHECK-NEXT: rsbs r7, r0, #0
2011 ; CHECK-NEXT: sbcs.w r7, r11, r1
2012 ; CHECK-NEXT: sbcs.w r2, r4, r2
2013 ; CHECK-NEXT: sbcs.w r2, r4, r3
2014 ; CHECK-NEXT: cset r2, lt
2015 ; CHECK-NEXT: cmp r2, #0
2016 ; CHECK-NEXT: csel r1, r1, r11, ne
2017 ; CHECK-NEXT: cmp r6, #0
2018 ; CHECK-NEXT: csel r3, r5, r6, ne
2019 ; CHECK-NEXT: cmp r2, #0
2020 ; CHECK-NEXT: csel r0, r0, r2, ne
2021 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
2022 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
2023 ; CHECK-NEXT: add sp, #4
2024 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
2026 %conv = fptosi <2 x float> %x to <2 x i128>
2027 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
2028 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
2029 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
2030 ret <2 x i64> %conv6
2033 define arm_aapcs_vfpcc <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
2034 ; CHECK-LABEL: utest_f32i64_mm:
2035 ; CHECK: @ %bb.0: @ %entry
2036 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
2037 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
2038 ; CHECK-NEXT: .pad #4
2039 ; CHECK-NEXT: sub sp, #4
2040 ; CHECK-NEXT: vmov r4, r0, d0
2041 ; CHECK-NEXT: bl __fixunssfti
2042 ; CHECK-NEXT: mov r5, r1
2043 ; CHECK-NEXT: subs r1, r2, #1
2044 ; CHECK-NEXT: sbcs r1, r3, #0
2045 ; CHECK-NEXT: cset r6, lo
2046 ; CHECK-NEXT: cmp r6, #0
2047 ; CHECK-NEXT: csel r7, r0, r6, ne
2048 ; CHECK-NEXT: mov r0, r4
2049 ; CHECK-NEXT: bl __fixunssfti
2050 ; CHECK-NEXT: subs r2, #1
2051 ; CHECK-NEXT: sbcs r2, r3, #0
2052 ; CHECK-NEXT: cset r2, lo
2053 ; CHECK-NEXT: cmp r2, #0
2054 ; CHECK-NEXT: csel r0, r0, r2, ne
2055 ; CHECK-NEXT: cmp r6, #0
2056 ; CHECK-NEXT: csel r3, r5, r6, ne
2057 ; CHECK-NEXT: cmp r2, #0
2058 ; CHECK-NEXT: csel r1, r1, r2, ne
2059 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
2060 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
2061 ; CHECK-NEXT: add sp, #4
2062 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
2064 %conv = fptoui <2 x float> %x to <2 x i128>
2065 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
2066 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
2067 ret <2 x i64> %conv6
2070 define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
2071 ; CHECK-LABEL: ustest_f32i64_mm:
2072 ; CHECK: @ %bb.0: @ %entry
2073 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
2074 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
2075 ; CHECK-NEXT: vmov r5, r0, d0
2076 ; CHECK-NEXT: bl __fixsfti
2077 ; CHECK-NEXT: mov r8, r1
2078 ; CHECK-NEXT: subs r1, r2, #1
2079 ; CHECK-NEXT: sbcs r1, r3, #0
2080 ; CHECK-NEXT: cset r7, lt
2081 ; CHECK-NEXT: cmp r7, #0
2082 ; CHECK-NEXT: csel r6, r0, r7, ne
2083 ; CHECK-NEXT: csel r4, r3, r7, ne
2084 ; CHECK-NEXT: mov r0, r5
2085 ; CHECK-NEXT: cmp r4, #0
2087 ; CHECK-NEXT: movmi r6, #0
2088 ; CHECK-NEXT: bl __fixsfti
2089 ; CHECK-NEXT: subs r2, #1
2090 ; CHECK-NEXT: sbcs r2, r3, #0
2091 ; CHECK-NEXT: cset r2, lt
2092 ; CHECK-NEXT: cmp r2, #0
2093 ; CHECK-NEXT: csel r3, r3, r2, ne
2094 ; CHECK-NEXT: csel r0, r0, r2, ne
2095 ; CHECK-NEXT: cmp r3, #0
2097 ; CHECK-NEXT: movmi r0, #0
2098 ; CHECK-NEXT: cmp r7, #0
2099 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r6
2100 ; CHECK-NEXT: csel r7, r8, r7, ne
2101 ; CHECK-NEXT: cmp r4, #0
2103 ; CHECK-NEXT: movmi r7, #0
2104 ; CHECK-NEXT: cmp r2, #0
2105 ; CHECK-NEXT: csel r1, r1, r2, ne
2106 ; CHECK-NEXT: cmp r3, #0
2108 ; CHECK-NEXT: movmi r1, #0
2109 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r7
2110 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
2112 %conv = fptosi <2 x float> %x to <2 x i128>
2113 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
2114 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
2115 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
2116 ret <2 x i64> %conv6
2119 define arm_aapcs_vfpcc <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
2120 ; CHECK-LABEL: stest_f16i64_mm:
2121 ; CHECK: @ %bb.0: @ %entry
2122 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
2123 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
2124 ; CHECK-NEXT: .vsave {d8, d9}
2125 ; CHECK-NEXT: vpush {d8, d9}
2126 ; CHECK-NEXT: vmov.u16 r0, q0[1]
2127 ; CHECK-NEXT: vmov q4, q0
2128 ; CHECK-NEXT: bl __fixhfti
2129 ; CHECK-NEXT: subs.w r7, r0, #-1
2130 ; CHECK-NEXT: mvn r9, #-2147483648
2131 ; CHECK-NEXT: sbcs.w r7, r1, r9
2132 ; CHECK-NEXT: mov.w r10, #-2147483648
2133 ; CHECK-NEXT: sbcs r7, r2, #0
2134 ; CHECK-NEXT: sbcs r7, r3, #0
2135 ; CHECK-NEXT: cset r7, lt
2136 ; CHECK-NEXT: cmp r7, #0
2137 ; CHECK-NEXT: csel r3, r3, r7, ne
2138 ; CHECK-NEXT: csel r2, r2, r7, ne
2139 ; CHECK-NEXT: mov.w r7, #-1
2140 ; CHECK-NEXT: csel r1, r1, r9, ne
2141 ; CHECK-NEXT: csel r4, r0, r7, ne
2142 ; CHECK-NEXT: rsbs r0, r4, #0
2143 ; CHECK-NEXT: sbcs.w r0, r10, r1
2144 ; CHECK-NEXT: sbcs.w r0, r7, r2
2145 ; CHECK-NEXT: sbcs.w r0, r7, r3
2146 ; CHECK-NEXT: cset r5, lt
2147 ; CHECK-NEXT: vmov.u16 r0, q4[0]
2148 ; CHECK-NEXT: cmp r5, #0
2149 ; CHECK-NEXT: csel r8, r1, r10, ne
2150 ; CHECK-NEXT: bl __fixhfti
2151 ; CHECK-NEXT: subs.w r6, r0, #-1
2152 ; CHECK-NEXT: sbcs.w r6, r1, r9
2153 ; CHECK-NEXT: sbcs r6, r2, #0
2154 ; CHECK-NEXT: sbcs r6, r3, #0
2155 ; CHECK-NEXT: cset r6, lt
2156 ; CHECK-NEXT: cmp r6, #0
2157 ; CHECK-NEXT: csel r0, r0, r7, ne
2158 ; CHECK-NEXT: csel r1, r1, r9, ne
2159 ; CHECK-NEXT: csel r3, r3, r6, ne
2160 ; CHECK-NEXT: csel r2, r2, r6, ne
2161 ; CHECK-NEXT: rsbs r6, r0, #0
2162 ; CHECK-NEXT: sbcs.w r6, r10, r1
2163 ; CHECK-NEXT: sbcs.w r2, r7, r2
2164 ; CHECK-NEXT: sbcs.w r2, r7, r3
2165 ; CHECK-NEXT: cset r2, lt
2166 ; CHECK-NEXT: cmp r2, #0
2167 ; CHECK-NEXT: csel r1, r1, r10, ne
2168 ; CHECK-NEXT: cmp r5, #0
2169 ; CHECK-NEXT: csel r3, r4, r5, ne
2170 ; CHECK-NEXT: cmp r2, #0
2171 ; CHECK-NEXT: csel r0, r0, r2, ne
2172 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
2173 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
2174 ; CHECK-NEXT: vpop {d8, d9}
2175 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
2177 %conv = fptosi <2 x half> %x to <2 x i128>
2178 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
2179 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
2180 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
2181 ret <2 x i64> %conv6
2184 define arm_aapcs_vfpcc <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
2185 ; CHECK-LABEL: utesth_f16i64_mm:
2186 ; CHECK: @ %bb.0: @ %entry
2187 ; CHECK-NEXT: .save {r4, r5, r7, lr}
2188 ; CHECK-NEXT: push {r4, r5, r7, lr}
2189 ; CHECK-NEXT: .vsave {d8, d9}
2190 ; CHECK-NEXT: vpush {d8, d9}
2191 ; CHECK-NEXT: vmov.u16 r0, q0[1]
2192 ; CHECK-NEXT: vmov q4, q0
2193 ; CHECK-NEXT: bl __fixunshfti
2194 ; CHECK-NEXT: mov r4, r0
2195 ; CHECK-NEXT: vmov.u16 r0, q4[0]
2196 ; CHECK-NEXT: mov r5, r1
2197 ; CHECK-NEXT: bl __fixunshfti
2198 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
2199 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
2200 ; CHECK-NEXT: vpop {d8, d9}
2201 ; CHECK-NEXT: pop {r4, r5, r7, pc}
2203 %conv = fptoui <2 x half> %x to <2 x i128>
2204 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
2205 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
2206 ret <2 x i64> %conv6
2209 define arm_aapcs_vfpcc <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
2210 ; CHECK-LABEL: ustest_f16i64_mm:
2211 ; CHECK: @ %bb.0: @ %entry
2212 ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
2213 ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
2214 ; CHECK-NEXT: .pad #4
2215 ; CHECK-NEXT: sub sp, #4
2216 ; CHECK-NEXT: .vsave {d8, d9}
2217 ; CHECK-NEXT: vpush {d8, d9}
2218 ; CHECK-NEXT: vmov.u16 r0, q0[1]
2219 ; CHECK-NEXT: vmov q4, q0
2220 ; CHECK-NEXT: bl __fixhfti
2221 ; CHECK-NEXT: mov r4, r1
2222 ; CHECK-NEXT: subs r1, r2, #1
2223 ; CHECK-NEXT: sbcs r1, r3, #0
2224 ; CHECK-NEXT: cset r6, lt
2225 ; CHECK-NEXT: cmp r6, #0
2226 ; CHECK-NEXT: csel r5, r0, r6, ne
2227 ; CHECK-NEXT: csel r7, r3, r6, ne
2228 ; CHECK-NEXT: vmov.u16 r0, q4[0]
2229 ; CHECK-NEXT: cmp r7, #0
2231 ; CHECK-NEXT: movmi r5, #0
2232 ; CHECK-NEXT: bl __fixhfti
2233 ; CHECK-NEXT: subs r2, #1
2234 ; CHECK-NEXT: sbcs r2, r3, #0
2235 ; CHECK-NEXT: cset r2, lt
2236 ; CHECK-NEXT: cmp r2, #0
2237 ; CHECK-NEXT: csel r3, r3, r2, ne
2238 ; CHECK-NEXT: csel r0, r0, r2, ne
2239 ; CHECK-NEXT: cmp r3, #0
2241 ; CHECK-NEXT: movmi r0, #0
2242 ; CHECK-NEXT: cmp r6, #0
2243 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
2244 ; CHECK-NEXT: csel r6, r4, r6, ne
2245 ; CHECK-NEXT: cmp r7, #0
2247 ; CHECK-NEXT: movmi r6, #0
2248 ; CHECK-NEXT: cmp r2, #0
2249 ; CHECK-NEXT: csel r1, r1, r2, ne
2250 ; CHECK-NEXT: cmp r3, #0
2252 ; CHECK-NEXT: movmi r1, #0
2253 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r6
2254 ; CHECK-NEXT: vpop {d8, d9}
2255 ; CHECK-NEXT: add sp, #4
2256 ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
2258 %conv = fptosi <2 x half> %x to <2 x i128>
2259 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
2260 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
2261 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
2262 ret <2 x i64> %conv6
2265 declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)
2266 declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)
2267 declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
2268 declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
2269 declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
2270 declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
2271 declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)
2272 declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)
2273 declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
2274 declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>)
2275 declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>)
2276 declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
2277 declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)
2278 declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)
2279 declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
2280 declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>)
2281 declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>)
2282 declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>)