| blob | 6392452e06cddde259b3ae9d1a75f96a9fff9fc9 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
4 ; This loop has a vpt block that should not block tailpredication
5 define void @convert_vptblock(ptr %pchTarget, i16 signext %iTargetStride, ptr %pwLineMask, ptr %ptCopySize, i8 zeroext %chColour, i8 zeroext %chOpacity) {
6 ; CHECK-LABEL: convert_vptblock:
7 ; CHECK: @ %bb.0: @ %entry
8 ; CHECK-NEXT: ldrsh.w r12, [r3, #2]
9 ; CHECK-NEXT: cmp.w r12, #1
10 ; CHECK-NEXT: it lt
11 ; CHECK-NEXT: bxlt lr
12 ; CHECK-NEXT: .LBB0_1: @ %for.body.lr.ph
13 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
14 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
15 ; CHECK-NEXT: .pad #4
16 ; CHECK-NEXT: sub sp, #4
17 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
18 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
19 ; CHECK-NEXT: ldrsh.w r10, [r3]
20 ; CHECK-NEXT: mov.w r8, #0
21 ; CHECK-NEXT: ldrd r4, r5, [sp, #88]
22 ; CHECK-NEXT: mov r7, r0
23 ; CHECK-NEXT: mov.w r11, #0
24 ; CHECK-NEXT: vidup.u16 q0, r8, #4
25 ; CHECK-NEXT: vmov.i32 q1, #0x0
26 ; CHECK-NEXT: vmov.i16 q2, #0x100
27 ; CHECK-NEXT: vmov.i16 q3, #0xff
28 ; CHECK-NEXT: .LBB0_2: @ %for.body
29 ; CHECK-NEXT: @ =>This Loop Header: Depth=1
30 ; CHECK-NEXT: @ Child Loop BB0_3 Depth 2
31 ; CHECK-NEXT: vmov q4, q0
32 ; CHECK-NEXT: mov r6, r8
33 ; CHECK-NEXT: mov r0, r7
34 ; CHECK-NEXT: dlstp.16 lr, r10
35 ; CHECK-NEXT: .LBB0_3: @ %do.body
36 ; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1
37 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
38 ; CHECK-NEXT: vldrb.u16 q5, [r2, q4]
39 ; CHECK-NEXT: vmul.i16 q4, q5, r5
40 ; CHECK-NEXT: vshr.u16 q4, q4, #8
41 ; CHECK-NEXT: vsub.i16 q5, q2, q4
42 ; CHECK-NEXT: vpt.i16 eq, q4, q3
43 ; CHECK-NEXT: vmovt q5, q1
44 ; CHECK-NEXT: vldrb.u16 q6, [r0]
45 ; CHECK-NEXT: vsub.i16 q4, q2, q5
46 ; CHECK-NEXT: vmul.i16 q5, q5, q6
47 ; CHECK-NEXT: vmla.i16 q5, q4, r4
48 ; CHECK-NEXT: vshr.u16 q4, q5, #8
49 ; CHECK-NEXT: vstrb.16 q4, [r0], #8
50 ; CHECK-NEXT: vidup.u16 q4, r6, #4
51 ; CHECK-NEXT: letp lr, .LBB0_3
52 ; CHECK-NEXT: @ %bb.4: @ %do.end
53 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
54 ; CHECK-NEXT: add.w r0, r11, #1
55 ; CHECK-NEXT: add r7, r1
56 ; CHECK-NEXT: sxth.w r11, r0
57 ; CHECK-NEXT: cmp r11, r12
58 ; CHECK-NEXT: blt .LBB0_2
59 ; CHECK-NEXT: @ %bb.5:
60 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
61 ; CHECK-NEXT: add sp, #4
62 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
63 ; CHECK-NEXT: bx lr
64 entry:
65 %iHeight1 = getelementptr inbounds i8, ptr %ptCopySize, i32 2
66 %0 = load i16, ptr %iHeight1, align 2
67 %cmp28 = icmp sgt i16 %0, 0
68 br i1 %cmp28, label %for.body.lr.ph, label %for.cond.cleanup
70 for.body.lr.ph: ; preds = %entry
71 %1 = load i16, ptr %ptCopySize, align 2
72 %conv5 = sext i16 %1 to i32
73 %2 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 0, i32 4)
74 %conv6 = zext i8 %chOpacity to i16
75 %.splatinsert = insertelement <8 x i16> poison, i16 %conv6, i64 0
76 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
77 %conv7 = zext i8 %chColour to i16
78 %.splatinsert.i = insertelement <8 x i16> poison, i16 %conv7, i64 0
79 %.splat.i = shufflevector <8 x i16> %.splatinsert.i, <8 x i16> poison, <8 x i32> zeroinitializer
80 %conv11 = sext i16 %iTargetStride to i32
81 br label %for.body
83 for.cond.cleanup: ; preds = %do.end, %entry
84 ret void
86 for.body: ; preds = %for.body.lr.ph, %do.end
87 %pchTarget.addr.030 = phi ptr [ %pchTarget, %for.body.lr.ph ], [ %add.ptr12, %do.end ]
88 %y.029 = phi i16 [ 0, %for.body.lr.ph ], [ %inc, %do.end ]
89 br label %do.body
91 do.body: ; preds = %do.body, %for.body
92 %blkCnt.0 = phi i32 [ %conv5, %for.body ], [ %sub8, %do.body ]
93 %.pn = phi { <8 x i16>, i32 } [ %2, %for.body ], [ %13, %do.body ]
94 %pchTargetLine.0 = phi ptr [ %pchTarget.addr.030, %for.body ], [ %add.ptr, %do.body ]
95 %vStride4Offs.0 = extractvalue { <8 x i16>, i32 } %.pn, 0
96 %incr.0 = extractvalue { <8 x i16>, i32 } %.pn, 1
97 %3 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %blkCnt.0)
98 %4 = tail call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %pwLineMask, <8 x i16> %vStride4Offs.0, i32 8, i32 0, i32 1, <8 x i1> %3)
99 %5 = mul <8 x i16> %4, %.splat
100 %shr = lshr <8 x i16> %5, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
101 %6 = icmp eq <8 x i16> %shr, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
102 %7 = sub nuw nsw <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>, %shr
103 %sub = select <8 x i1> %6, <8 x i16> zeroinitializer, <8 x i16> %7
104 %8 = tail call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %pchTargetLine.0, i32 1, <8 x i1> %3, <8 x i8> zeroinitializer)
105 %9 = zext <8 x i8> %8 to <8 x i16>
106 %sub.i = sub nsw <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>, %sub
107 %10 = mul <8 x i16> %sub.i, %.splat.i
108 %11 = mul <8 x i16> %sub, %9
109 %add.i = add <8 x i16> %10, %11
110 %shr.i = lshr <8 x i16> %add.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
111 %12 = trunc nuw <8 x i16> %shr.i to <8 x i8>
112 tail call void @llvm.masked.store.v8i8.p0(<8 x i8> %12, ptr %pchTargetLine.0, i32 1, <8 x i1> %3)
113 %13 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %incr.0, i32 4)
114 %add.ptr = getelementptr inbounds i8, ptr %pchTargetLine.0, i32 8
115 %sub8 = add nsw i32 %blkCnt.0, -8
116 %cmp9 = icmp sgt i32 %blkCnt.0, 8
117 br i1 %cmp9, label %do.body, label %do.end
119 do.end: ; preds = %do.body
120 %add.ptr12 = getelementptr inbounds i8, ptr %pchTarget.addr.030, i32 %conv11
121 %inc = add nuw nsw i16 %y.029, 1
122 %cmp = icmp slt i16 %inc, %0
123 br i1 %cmp, label %for.body, label %for.cond.cleanup
124 }
126 ; This loop has an else predicate on the vqshl, which is not very realistic but
127 ; prevents us from converting to a vptblock without being able to remove it.
128 define i32 @else(ptr %s1, ptr %s2, i32 %x, ptr %d, i32 %n) {
129 ; CHECK-LABEL: else:
130 ; CHECK: @ %bb.0: @ %entry
131 ; CHECK-NEXT: .save {r7, lr}
132 ; CHECK-NEXT: push {r7, lr}
133 ; CHECK-NEXT: ldr r2, [sp, #8]
134 ; CHECK-NEXT: cmp r2, #4
135 ; CHECK-NEXT: mov r3, r2
136 ; CHECK-NEXT: it ge
137 ; CHECK-NEXT: movge r3, #4
138 ; CHECK-NEXT: subs r3, r2, r3
139 ; CHECK-NEXT: add.w r12, r3, #3
140 ; CHECK-NEXT: movs r3, #1
141 ; CHECK-NEXT: add.w r12, r3, r12, lsr #2
142 ; CHECK-NEXT: movs r3, #98
143 ; CHECK-NEXT: dls lr, r12
144 ; CHECK-NEXT: .LBB1_1: @ %do.body
145 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
146 ; CHECK-NEXT: vctp.32 r2
147 ; CHECK-NEXT: subs r2, #4
148 ; CHECK-NEXT: vpstt
149 ; CHECK-NEXT: vldrwt.u32 q1, [r1], #16
150 ; CHECK-NEXT: vldrwt.u32 q0, [r0]
151 ; CHECK-NEXT: vmov q2, q1
152 ; CHECK-NEXT: vpstet
153 ; CHECK-NEXT: vqdmlsdht.s32 q2, q1, q0
154 ; CHECK-NEXT: vqshle.u32 q2, r3
155 ; CHECK-NEXT: vstrwt.32 q2, [r0], #16
156 ; CHECK-NEXT: le lr, .LBB1_1
157 ; CHECK-NEXT: @ %bb.2: @ %do.end
158 ; CHECK-NEXT: movs r0, #0
159 ; CHECK-NEXT: pop {r7, pc}
160 entry:
161 br label %do.body
163 do.body: ; preds = %do.body, %entry
164 %n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]
165 %s2.addr.0 = phi ptr [ %s2, %entry ], [ %add.ptr1, %do.body ]
166 %s1.addr.0 = phi ptr [ %s1, %entry ], [ %add.ptr, %do.body ]
167 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)
168 %1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %s1.addr.0, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)
169 %2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %s2.addr.0, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)
170 %3 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %2, <4 x i32> %2, <4 x i32> %1, i32 0, i32 0, i32 1, <4 x i1> %0)
171 %4 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
172 %5 = tail call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %3, i32 98, i32 1, i32 0, i32 1, <4 x i1> %4)
173 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %5, ptr %s1.addr.0, i32 4, <4 x i1> %0)
174 %add.ptr = getelementptr inbounds i8, ptr %s1.addr.0, i32 16
175 %add.ptr1 = getelementptr inbounds i8, ptr %s2.addr.0, i32 16
176 %sub = add nsw i32 %n.addr.0, -4
177 %cmp = icmp sgt i32 %n.addr.0, 4
178 br i1 %cmp, label %do.body, label %do.end
180 do.end: ; preds = %do.body
181 ret i32 0
182 }