1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6 target triple = "thumbv8.1m.main-none-none-eabi"
8 define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_non_consecutive_ins(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
10 %conv.i = zext i16 %p to i32
11 %0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12 %1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13 %2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
14 %3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
18 declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
20 attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
21 attributes #1 = { nounwind readnone }
22 attributes #2 = { nounwind }
26 name: vpt_2_blocks_non_consecutive_ins
28 exposesReturnsTwice: false
30 regBankSelected: false
33 tracksRegLiveness: true
37 - { reg: '$q0', virtual-reg: '' }
38 - { reg: '$q1', virtual-reg: '' }
39 - { reg: '$q2', virtual-reg: '' }
40 - { reg: '$r0', virtual-reg: '' }
42 isFrameAddressTaken: false
43 isReturnAddressTaken: false
53 cvBytesOfCalleeSavedRegisters: 0
54 hasOpaqueSPAdjustment: false
56 hasMustTailInVarArgFunc: false
65 liveins: $q0, $q1, $q2, $r0
68 ; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins
69 ; CHECK: liveins: $q0, $q1, $q2, $r0
70 ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
71 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
72 ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
73 ; CHECK: MVE_VPST 4, implicit $vpr
74 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
75 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
77 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
78 ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
79 ; CHECK: MVE_VPST 4, implicit $vpr
80 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
81 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
83 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
84 $vpr = VMSR_P0 killed $r0, 14, $noreg
85 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
86 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
87 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
89 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
91 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
92 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
93 tBX_RET 14, $noreg, implicit $q0