1 ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3 ;;; Test vector floating reciprocal intrinsic instructions
6 ;;; We test VRCP*vl, VRCP*vl_v, PVRCP*vl, and PVRCP*vl_v instructions.
8 ; Function Attrs: nounwind readnone
9 define fastcc <256 x double> @vrcpd_vvl(<256 x double> %0) {
10 ; CHECK-LABEL: vrcpd_vvl:
12 ; CHECK-NEXT: lea %s0, 256
14 ; CHECK-NEXT: vrcp.d %v0, %v0
15 ; CHECK-NEXT: b.l.t (, %s10)
16 %2 = tail call fast <256 x double> @llvm.ve.vl.vrcpd.vvl(<256 x double> %0, i32 256)
20 ; Function Attrs: nounwind readnone
21 declare <256 x double> @llvm.ve.vl.vrcpd.vvl(<256 x double>, i32)
23 ; Function Attrs: nounwind readnone
24 define fastcc <256 x double> @vrcpd_vvvl(<256 x double> %0, <256 x double> %1) {
25 ; CHECK-LABEL: vrcpd_vvvl:
27 ; CHECK-NEXT: lea %s0, 128
29 ; CHECK-NEXT: vrcp.d %v1, %v0
30 ; CHECK-NEXT: lea %s16, 256
31 ; CHECK-NEXT: lvl %s16
32 ; CHECK-NEXT: vor %v0, (0)1, %v1
33 ; CHECK-NEXT: b.l.t (, %s10)
34 %3 = tail call fast <256 x double> @llvm.ve.vl.vrcpd.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
38 ; Function Attrs: nounwind readnone
39 declare <256 x double> @llvm.ve.vl.vrcpd.vvvl(<256 x double>, <256 x double>, i32)
41 ; Function Attrs: nounwind readnone
42 define fastcc <256 x double> @vrcps_vvl(<256 x double> %0) {
43 ; CHECK-LABEL: vrcps_vvl:
45 ; CHECK-NEXT: lea %s0, 256
47 ; CHECK-NEXT: vrcp.s %v0, %v0
48 ; CHECK-NEXT: b.l.t (, %s10)
49 %2 = tail call fast <256 x double> @llvm.ve.vl.vrcps.vvl(<256 x double> %0, i32 256)
53 ; Function Attrs: nounwind readnone
54 declare <256 x double> @llvm.ve.vl.vrcps.vvl(<256 x double>, i32)
56 ; Function Attrs: nounwind readnone
57 define fastcc <256 x double> @vrcps_vvvl(<256 x double> %0, <256 x double> %1) {
58 ; CHECK-LABEL: vrcps_vvvl:
60 ; CHECK-NEXT: lea %s0, 128
62 ; CHECK-NEXT: vrcp.s %v1, %v0
63 ; CHECK-NEXT: lea %s16, 256
64 ; CHECK-NEXT: lvl %s16
65 ; CHECK-NEXT: vor %v0, (0)1, %v1
66 ; CHECK-NEXT: b.l.t (, %s10)
67 %3 = tail call fast <256 x double> @llvm.ve.vl.vrcps.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
71 ; Function Attrs: nounwind readnone
72 declare <256 x double> @llvm.ve.vl.vrcps.vvvl(<256 x double>, <256 x double>, i32)
74 ; Function Attrs: nounwind readnone
75 define fastcc <256 x double> @pvrcp_vvl(<256 x double> %0) {
76 ; CHECK-LABEL: pvrcp_vvl:
78 ; CHECK-NEXT: lea %s0, 256
80 ; CHECK-NEXT: pvrcp %v0, %v0
81 ; CHECK-NEXT: b.l.t (, %s10)
82 %2 = tail call fast <256 x double> @llvm.ve.vl.pvrcp.vvl(<256 x double> %0, i32 256)
86 ; Function Attrs: nounwind readnone
87 declare <256 x double> @llvm.ve.vl.pvrcp.vvl(<256 x double>, i32)
89 ; Function Attrs: nounwind readnone
90 define fastcc <256 x double> @pvrcp_vvvl(<256 x double> %0, <256 x double> %1) {
91 ; CHECK-LABEL: pvrcp_vvvl:
93 ; CHECK-NEXT: lea %s0, 128
95 ; CHECK-NEXT: pvrcp %v1, %v0
96 ; CHECK-NEXT: lea %s16, 256
97 ; CHECK-NEXT: lvl %s16
98 ; CHECK-NEXT: vor %v0, (0)1, %v1
99 ; CHECK-NEXT: b.l.t (, %s10)
100 %3 = tail call fast <256 x double> @llvm.ve.vl.pvrcp.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
101 ret <256 x double> %3
104 ; Function Attrs: nounwind readnone
105 declare <256 x double> @llvm.ve.vl.pvrcp.vvvl(<256 x double>, <256 x double>, i32)