| blob | 3e6acda18422df4eaffc1305339d1484cf6faffd |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=O0
3 ; RUN: llc -O1 < %s | FileCheck %s --check-prefixes=OPT
4 ; RUN: llc -O2 < %s | FileCheck %s --check-prefixes=OPT
5 ; RUN: llc -O3 < %s | FileCheck %s --check-prefixes=OPT
7 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
8 target triple = "x86_64-unknown-linux-gnu"
10 @__llvm_gcov_ctr.89 = internal global [2 x i64] zeroinitializer
11 @__llvm_gcov_ctr.109 = internal global [2 x i64] zeroinitializer
12 @__llvm_gcov_ctr.112 = internal global [2 x i64] zeroinitializer
13 @__llvm_gcov_ctr.113 = internal global [2 x i64] zeroinitializer
14 @__llvm_gcov_ctr.154 = internal global [1 x i64] zeroinitializer
15 @__llvm_gcov_ctr.155 = internal global [2 x i64] zeroinitializer
16 @__llvm_gcov_ctr.156 = internal global [2 x i64] zeroinitializer
17 @__llvm_gcov_ctr.157 = internal global [2 x i64] zeroinitializer
18 @__llvm_gcov_ctr.160 = internal global [2 x i64] zeroinitializer
19 @__llvm_gcov_ctr.161 = internal global [2 x i64] zeroinitializer
20 @__llvm_gcov_ctr.189 = internal global [2 x i64] zeroinitializer
21 @__llvm_gcov_ctr.1109 = internal global [2 x i64] zeroinitializer
22 @__llvm_gcov_ctr.1112 = internal global [2 x i64] zeroinitializer
23 @__llvm_gcov_ctr.1113 = internal global [2 x i64] zeroinitializer
24 @__llvm_gcov_ctr.1154 = internal global [1 x i64] zeroinitializer
25 @__llvm_gcov_ctr.1155 = internal global [2 x i64] zeroinitializer
26 @__llvm_gcov_ctr.1156 = internal global [2 x i64] zeroinitializer
27 @__llvm_gcov_ctr.1157 = internal global [2 x i64] zeroinitializer
28 @__llvm_gcov_ctr.1160 = internal global [2 x i64] zeroinitializer
29 @__llvm_gcov_ctr.1161 = internal global [2 x i64] zeroinitializer
31 define dso_local void @independent_load_stores() {
32 ; O0-LABEL: independent_load_stores:
33 ; O0: # %bb.0:
34 ; O0-NEXT: .Lpcsection0:
35 ; O0-NEXT: movq __llvm_gcov_ctr.109, %rax
36 ; O0-NEXT: addq $1, %rax
37 ; O0-NEXT: .Lpcsection1:
38 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.109
39 ; O0-NEXT: .Lpcsection2:
40 ; O0-NEXT: movq __llvm_gcov_ctr.112, %rax
41 ; O0-NEXT: addq $1, %rax
42 ; O0-NEXT: .Lpcsection3:
43 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.112
44 ; O0-NEXT: .Lpcsection4:
45 ; O0-NEXT: movq __llvm_gcov_ctr.113, %rax
46 ; O0-NEXT: addq $1, %rax
47 ; O0-NEXT: .Lpcsection5:
48 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.113
49 ; O0-NEXT: .Lpcsection6:
50 ; O0-NEXT: movq __llvm_gcov_ctr.154, %rax
51 ; O0-NEXT: addq $1, %rax
52 ; O0-NEXT: .Lpcsection7:
53 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.154
54 ; O0-NEXT: .Lpcsection8:
55 ; O0-NEXT: movq __llvm_gcov_ctr.155, %rax
56 ; O0-NEXT: addq $1, %rax
57 ; O0-NEXT: .Lpcsection9:
58 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.155
59 ; O0-NEXT: .Lpcsection10:
60 ; O0-NEXT: movq __llvm_gcov_ctr.89, %rax
61 ; O0-NEXT: addq $1, %rax
62 ; O0-NEXT: .Lpcsection11:
63 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.89
64 ; O0-NEXT: .Lpcsection12:
65 ; O0-NEXT: movq __llvm_gcov_ctr.160, %rax
66 ; O0-NEXT: addq $1, %rax
67 ; O0-NEXT: .Lpcsection13:
68 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.160
69 ; O0-NEXT: .Lpcsection14:
70 ; O0-NEXT: movq __llvm_gcov_ctr.156, %rax
71 ; O0-NEXT: addq $1, %rax
72 ; O0-NEXT: .Lpcsection15:
73 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.156
74 ; O0-NEXT: .Lpcsection16:
75 ; O0-NEXT: movq __llvm_gcov_ctr.157, %rax
76 ; O0-NEXT: addq $1, %rax
77 ; O0-NEXT: .Lpcsection17:
78 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.157
79 ; O0-NEXT: .Lpcsection18:
80 ; O0-NEXT: movq __llvm_gcov_ctr.161, %rax
81 ; O0-NEXT: addq $1, %rax
82 ; O0-NEXT: .Lpcsection19:
83 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.161
84 ; O0-NEXT: .Lpcsection20:
85 ; O0-NEXT: movq __llvm_gcov_ctr.1109, %rax
86 ; O0-NEXT: addq $1, %rax
87 ; O0-NEXT: .Lpcsection21:
88 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1109
89 ; O0-NEXT: .Lpcsection22:
90 ; O0-NEXT: movq __llvm_gcov_ctr.1112, %rax
91 ; O0-NEXT: addq $1, %rax
92 ; O0-NEXT: .Lpcsection23:
93 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1112
94 ; O0-NEXT: .Lpcsection24:
95 ; O0-NEXT: movq __llvm_gcov_ctr.1113, %rax
96 ; O0-NEXT: addq $1, %rax
97 ; O0-NEXT: .Lpcsection25:
98 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1113
99 ; O0-NEXT: .Lpcsection26:
100 ; O0-NEXT: movq __llvm_gcov_ctr.1154, %rax
101 ; O0-NEXT: addq $1, %rax
102 ; O0-NEXT: .Lpcsection27:
103 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1154
104 ; O0-NEXT: .Lpcsection28:
105 ; O0-NEXT: movq __llvm_gcov_ctr.1155, %rax
106 ; O0-NEXT: addq $1, %rax
107 ; O0-NEXT: .Lpcsection29:
108 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1155
109 ; O0-NEXT: .Lpcsection30:
110 ; O0-NEXT: movq __llvm_gcov_ctr.189, %rax
111 ; O0-NEXT: addq $1, %rax
112 ; O0-NEXT: .Lpcsection31:
113 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.189
114 ; O0-NEXT: .Lpcsection32:
115 ; O0-NEXT: movq __llvm_gcov_ctr.1160, %rax
116 ; O0-NEXT: addq $1, %rax
117 ; O0-NEXT: .Lpcsection33:
118 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1160
119 ; O0-NEXT: .Lpcsection34:
120 ; O0-NEXT: movq __llvm_gcov_ctr.1156, %rax
121 ; O0-NEXT: addq $1, %rax
122 ; O0-NEXT: .Lpcsection35:
123 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1156
124 ; O0-NEXT: .Lpcsection36:
125 ; O0-NEXT: movq __llvm_gcov_ctr.1157, %rax
126 ; O0-NEXT: addq $1, %rax
127 ; O0-NEXT: .Lpcsection37:
128 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1157
129 ; O0-NEXT: .Lpcsection38:
130 ; O0-NEXT: movq __llvm_gcov_ctr.1161, %rax
131 ; O0-NEXT: addq $1, %rax
132 ; O0-NEXT: .Lpcsection39:
133 ; O0-NEXT: movq %rax, __llvm_gcov_ctr.1161
134 ; O0-NEXT: retq
135 ;
136 ; OPT-LABEL: independent_load_stores:
137 ; OPT: # %bb.0:
138 ; OPT-NEXT: .Lpcsection0:
139 ; OPT-NEXT: incq __llvm_gcov_ctr.109(%rip)
140 ; OPT-NEXT: .Lpcsection1:
141 ; OPT-NEXT: incq __llvm_gcov_ctr.112(%rip)
142 ; OPT-NEXT: .Lpcsection2:
143 ; OPT-NEXT: incq __llvm_gcov_ctr.113(%rip)
144 ; OPT-NEXT: .Lpcsection3:
145 ; OPT-NEXT: incq __llvm_gcov_ctr.154(%rip)
146 ; OPT-NEXT: .Lpcsection4:
147 ; OPT-NEXT: incq __llvm_gcov_ctr.155(%rip)
148 ; OPT-NEXT: .Lpcsection5:
149 ; OPT-NEXT: incq __llvm_gcov_ctr.89(%rip)
150 ; OPT-NEXT: .Lpcsection6:
151 ; OPT-NEXT: incq __llvm_gcov_ctr.160(%rip)
152 ; OPT-NEXT: .Lpcsection7:
153 ; OPT-NEXT: incq __llvm_gcov_ctr.156(%rip)
154 ; OPT-NEXT: .Lpcsection8:
155 ; OPT-NEXT: incq __llvm_gcov_ctr.157(%rip)
156 ; OPT-NEXT: .Lpcsection9:
157 ; OPT-NEXT: incq __llvm_gcov_ctr.161(%rip)
158 ; OPT-NEXT: .Lpcsection10:
159 ; OPT-NEXT: incq __llvm_gcov_ctr.1109(%rip)
160 ; OPT-NEXT: .Lpcsection11:
161 ; OPT-NEXT: incq __llvm_gcov_ctr.1112(%rip)
162 ; OPT-NEXT: .Lpcsection12:
163 ; OPT-NEXT: incq __llvm_gcov_ctr.1113(%rip)
164 ; OPT-NEXT: .Lpcsection13:
165 ; OPT-NEXT: incq __llvm_gcov_ctr.1154(%rip)
166 ; OPT-NEXT: .Lpcsection14:
167 ; OPT-NEXT: incq __llvm_gcov_ctr.1155(%rip)
168 ; OPT-NEXT: .Lpcsection15:
169 ; OPT-NEXT: incq __llvm_gcov_ctr.189(%rip)
170 ; OPT-NEXT: .Lpcsection16:
171 ; OPT-NEXT: incq __llvm_gcov_ctr.1160(%rip)
172 ; OPT-NEXT: .Lpcsection17:
173 ; OPT-NEXT: incq __llvm_gcov_ctr.1156(%rip)
174 ; OPT-NEXT: .Lpcsection18:
175 ; OPT-NEXT: incq __llvm_gcov_ctr.1157(%rip)
176 ; OPT-NEXT: .Lpcsection19:
177 ; OPT-NEXT: incq __llvm_gcov_ctr.1161(%rip)
178 ; OPT-NEXT: retq
179 %1 = load i64, ptr @__llvm_gcov_ctr.109, align 8, !pcsections !0
180 %2 = add i64 %1, 1
181 store i64 %2, ptr @__llvm_gcov_ctr.109, align 8, !pcsections !0
182 %3 = load i64, ptr @__llvm_gcov_ctr.112, align 8, !pcsections !0
183 %4 = add i64 %3, 1
184 store i64 %4, ptr @__llvm_gcov_ctr.112, align 8, !pcsections !0
185 %5 = load i64, ptr @__llvm_gcov_ctr.113, align 8, !pcsections !0
186 %6 = add i64 %5, 1
187 store i64 %6, ptr @__llvm_gcov_ctr.113, align 8, !pcsections !0
188 %7 = load i64, ptr @__llvm_gcov_ctr.154, align 8, !pcsections !0
189 %8 = add i64 %7, 1
190 store i64 %8, ptr @__llvm_gcov_ctr.154, align 8, !pcsections !0
191 %9 = load i64, ptr @__llvm_gcov_ctr.155, align 8, !pcsections !0
192 %10 = add i64 %9, 1
193 store i64 %10, ptr @__llvm_gcov_ctr.155, align 8, !pcsections !0
194 %11 = load i64, ptr @__llvm_gcov_ctr.89, align 8, !pcsections !0
195 %12 = add i64 %11, 1
196 store i64 %12, ptr @__llvm_gcov_ctr.89, align 8, !pcsections !0
197 %13 = load i64, ptr @__llvm_gcov_ctr.160, align 8, !pcsections !0
198 %14 = add i64 %13, 1
199 store i64 %14, ptr @__llvm_gcov_ctr.160, align 8, !pcsections !0
200 %15 = load i64, ptr @__llvm_gcov_ctr.156, align 8, !pcsections !0
201 %16 = add i64 %15, 1
202 store i64 %16, ptr @__llvm_gcov_ctr.156, align 8, !pcsections !0
203 %17 = load i64, ptr @__llvm_gcov_ctr.157, align 8, !pcsections !0
204 %18 = add i64 %17, 1
205 store i64 %18, ptr @__llvm_gcov_ctr.157, align 8, !pcsections !0
206 %19 = load i64, ptr @__llvm_gcov_ctr.161, align 8, !pcsections !0
207 %20 = add i64 %19, 1
208 store i64 %20, ptr @__llvm_gcov_ctr.161, align 8, !pcsections !0
210 %21 = load i64, ptr @__llvm_gcov_ctr.1109, align 8, !pcsections !0
211 %22 = add i64 %21, 1
212 store i64 %22, ptr @__llvm_gcov_ctr.1109, align 8, !pcsections !0
213 %23 = load i64, ptr @__llvm_gcov_ctr.1112, align 8, !pcsections !0
214 %24 = add i64 %23, 1
215 store i64 %24, ptr @__llvm_gcov_ctr.1112, align 8, !pcsections !0
216 %25 = load i64, ptr @__llvm_gcov_ctr.1113, align 8, !pcsections !0
217 %26 = add i64 %25, 1
218 store i64 %26, ptr @__llvm_gcov_ctr.1113, align 8, !pcsections !0
219 %27 = load i64, ptr @__llvm_gcov_ctr.1154, align 8, !pcsections !0
220 %28 = add i64 %27, 1
221 store i64 %28, ptr @__llvm_gcov_ctr.1154, align 8, !pcsections !0
222 %29 = load i64, ptr @__llvm_gcov_ctr.1155, align 8, !pcsections !0
223 %30 = add i64 %29, 1
224 store i64 %30, ptr @__llvm_gcov_ctr.1155, align 8, !pcsections !0
225 %31 = load i64, ptr @__llvm_gcov_ctr.189, align 8, !pcsections !0
226 %32 = add i64 %31, 1
227 store i64 %32, ptr @__llvm_gcov_ctr.189, align 8, !pcsections !0
228 %33 = load i64, ptr @__llvm_gcov_ctr.1160, align 8, !pcsections !0
229 %34 = add i64 %33, 1
230 store i64 %34, ptr @__llvm_gcov_ctr.1160, align 8, !pcsections !0
231 %35 = load i64, ptr @__llvm_gcov_ctr.1156, align 8, !pcsections !0
232 %36 = add i64 %35, 1
233 store i64 %36, ptr @__llvm_gcov_ctr.1156, align 8, !pcsections !0
234 %37 = load i64, ptr @__llvm_gcov_ctr.1157, align 8, !pcsections !0
235 %38 = add i64 %37, 1
236 store i64 %38, ptr @__llvm_gcov_ctr.1157, align 8, !pcsections !0
237 %39 = load i64, ptr @__llvm_gcov_ctr.1161, align 8, !pcsections !0
238 %40 = add i64 %39, 1
239 store i64 %40, ptr @__llvm_gcov_ctr.1161, align 8, !pcsections !0
241 ret void
242 }
244 !0 = !{!"foo"}