| blob | 6360c68e62cc9457a9f339ede032055a26226a7c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE,SSE2
3 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefixes=SSE,SSE3
4 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
5 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
6 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
7 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2OR512VL,AVX2,AVX2-SLOW
8 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2OR512VL,AVX2,AVX2-FAST
9 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2OR512VL,AVX2,AVX2-FAST
10 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2OR512VL,AVX512VL
11 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2OR512VL,AVX512VL
13 define <4 x i32> @shuffle_v4i32_0001(<4 x i32> %a, <4 x i32> %b) {
14 ; SSE-LABEL: shuffle_v4i32_0001:
15 ; SSE: # %bb.0:
16 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,1]
17 ; SSE-NEXT: retq
18 ;
19 ; AVX-LABEL: shuffle_v4i32_0001:
20 ; AVX: # %bb.0:
21 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
22 ; AVX-NEXT: retq
23 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
24 ret <4 x i32> %shuffle
25 }
26 define <4 x i32> @shuffle_v4i32_0020(<4 x i32> %a, <4 x i32> %b) {
27 ; SSE-LABEL: shuffle_v4i32_0020:
28 ; SSE: # %bb.0:
29 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,0]
30 ; SSE-NEXT: retq
31 ;
32 ; AVX-LABEL: shuffle_v4i32_0020:
33 ; AVX: # %bb.0:
34 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
35 ; AVX-NEXT: retq
36 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
37 ret <4 x i32> %shuffle
38 }
39 define <4 x i32> @shuffle_v4i32_0112(<4 x i32> %a, <4 x i32> %b) {
40 ; SSE-LABEL: shuffle_v4i32_0112:
41 ; SSE: # %bb.0:
42 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
43 ; SSE-NEXT: retq
44 ;
45 ; AVX-LABEL: shuffle_v4i32_0112:
46 ; AVX: # %bb.0:
47 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,1,2]
48 ; AVX-NEXT: retq
49 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 1, i32 2>
50 ret <4 x i32> %shuffle
51 }
52 define <4 x i32> @shuffle_v4i32_0300(<4 x i32> %a, <4 x i32> %b) {
53 ; SSE-LABEL: shuffle_v4i32_0300:
54 ; SSE: # %bb.0:
55 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,0,0]
56 ; SSE-NEXT: retq
57 ;
58 ; AVX-LABEL: shuffle_v4i32_0300:
59 ; AVX: # %bb.0:
60 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
61 ; AVX-NEXT: retq
62 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
63 ret <4 x i32> %shuffle
64 }
65 define <4 x i32> @shuffle_v4i32_1000(<4 x i32> %a, <4 x i32> %b) {
66 ; SSE-LABEL: shuffle_v4i32_1000:
67 ; SSE: # %bb.0:
68 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
69 ; SSE-NEXT: retq
70 ;
71 ; AVX-LABEL: shuffle_v4i32_1000:
72 ; AVX: # %bb.0:
73 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
74 ; AVX-NEXT: retq
75 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
76 ret <4 x i32> %shuffle
77 }
78 define <4 x i32> @shuffle_v4i32_2200(<4 x i32> %a, <4 x i32> %b) {
79 ; SSE-LABEL: shuffle_v4i32_2200:
80 ; SSE: # %bb.0:
81 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,0,0]
82 ; SSE-NEXT: retq
83 ;
84 ; AVX-LABEL: shuffle_v4i32_2200:
85 ; AVX: # %bb.0:
86 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
87 ; AVX-NEXT: retq
88 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
89 ret <4 x i32> %shuffle
90 }
91 define <4 x i32> @shuffle_v4i32_3330(<4 x i32> %a, <4 x i32> %b) {
92 ; SSE-LABEL: shuffle_v4i32_3330:
93 ; SSE: # %bb.0:
94 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,0]
95 ; SSE-NEXT: retq
96 ;
97 ; AVX-LABEL: shuffle_v4i32_3330:
98 ; AVX: # %bb.0:
99 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,0]
100 ; AVX-NEXT: retq
101 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
102 ret <4 x i32> %shuffle
103 }
104 define <4 x i32> @shuffle_v4i32_3210(<4 x i32> %a, <4 x i32> %b) {
105 ; SSE-LABEL: shuffle_v4i32_3210:
106 ; SSE: # %bb.0:
107 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
108 ; SSE-NEXT: retq
109 ;
110 ; AVX-LABEL: shuffle_v4i32_3210:
111 ; AVX: # %bb.0:
112 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
113 ; AVX-NEXT: retq
114 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
115 ret <4 x i32> %shuffle
116 }
118 define <4 x i32> @shuffle_v4i32_2121(<4 x i32> %a, <4 x i32> %b) {
119 ; SSE-LABEL: shuffle_v4i32_2121:
120 ; SSE: # %bb.0:
121 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,2,1]
122 ; SSE-NEXT: retq
123 ;
124 ; AVX-LABEL: shuffle_v4i32_2121:
125 ; AVX: # %bb.0:
126 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,1,2,1]
127 ; AVX-NEXT: retq
128 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 1, i32 2, i32 1>
129 ret <4 x i32> %shuffle
130 }
132 define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
133 ; SSE-LABEL: shuffle_v4f32_0001:
134 ; SSE: # %bb.0:
135 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
136 ; SSE-NEXT: retq
137 ;
138 ; AVX-LABEL: shuffle_v4f32_0001:
139 ; AVX: # %bb.0:
140 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
141 ; AVX-NEXT: retq
142 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
143 ret <4 x float> %shuffle
144 }
145 define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
146 ; SSE-LABEL: shuffle_v4f32_0020:
147 ; SSE: # %bb.0:
148 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
149 ; SSE-NEXT: retq
150 ;
151 ; AVX-LABEL: shuffle_v4f32_0020:
152 ; AVX: # %bb.0:
153 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
154 ; AVX-NEXT: retq
155 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
156 ret <4 x float> %shuffle
157 }
158 define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
159 ; SSE-LABEL: shuffle_v4f32_0300:
160 ; SSE: # %bb.0:
161 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
162 ; SSE-NEXT: retq
163 ;
164 ; AVX-LABEL: shuffle_v4f32_0300:
165 ; AVX: # %bb.0:
166 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
167 ; AVX-NEXT: retq
168 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
169 ret <4 x float> %shuffle
170 }
171 define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
172 ; SSE-LABEL: shuffle_v4f32_1000:
173 ; SSE: # %bb.0:
174 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
175 ; SSE-NEXT: retq
176 ;
177 ; AVX-LABEL: shuffle_v4f32_1000:
178 ; AVX: # %bb.0:
179 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
180 ; AVX-NEXT: retq
181 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
182 ret <4 x float> %shuffle
183 }
184 define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
185 ; SSE-LABEL: shuffle_v4f32_2200:
186 ; SSE: # %bb.0:
187 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
188 ; SSE-NEXT: retq
189 ;
190 ; AVX-LABEL: shuffle_v4f32_2200:
191 ; AVX: # %bb.0:
192 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
193 ; AVX-NEXT: retq
194 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
195 ret <4 x float> %shuffle
196 }
197 define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
198 ; SSE-LABEL: shuffle_v4f32_3330:
199 ; SSE: # %bb.0:
200 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,0]
201 ; SSE-NEXT: retq
202 ;
203 ; AVX-LABEL: shuffle_v4f32_3330:
204 ; AVX: # %bb.0:
205 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,0]
206 ; AVX-NEXT: retq
207 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
208 ret <4 x float> %shuffle
209 }
210 define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
211 ; SSE-LABEL: shuffle_v4f32_3210:
212 ; SSE: # %bb.0:
213 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
214 ; SSE-NEXT: retq
215 ;
216 ; AVX-LABEL: shuffle_v4f32_3210:
217 ; AVX: # %bb.0:
218 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
219 ; AVX-NEXT: retq
220 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
221 ret <4 x float> %shuffle
222 }
223 define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) {
224 ; SSE-LABEL: shuffle_v4f32_0011:
225 ; SSE: # %bb.0:
226 ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1]
227 ; SSE-NEXT: retq
228 ;
229 ; AVX-LABEL: shuffle_v4f32_0011:
230 ; AVX: # %bb.0:
231 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,1,1]
232 ; AVX-NEXT: retq
233 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
234 ret <4 x float> %shuffle
235 }
236 define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) {
237 ; SSE-LABEL: shuffle_v4f32_2233:
238 ; SSE: # %bb.0:
239 ; SSE-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3]
240 ; SSE-NEXT: retq
241 ;
242 ; AVX-LABEL: shuffle_v4f32_2233:
243 ; AVX: # %bb.0:
244 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]
245 ; AVX-NEXT: retq
246 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
247 ret <4 x float> %shuffle
248 }
249 define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) {
250 ; SSE2-LABEL: shuffle_v4f32_0022:
251 ; SSE2: # %bb.0:
252 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,2]
253 ; SSE2-NEXT: retq
254 ;
255 ; SSE3-LABEL: shuffle_v4f32_0022:
256 ; SSE3: # %bb.0:
257 ; SSE3-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
258 ; SSE3-NEXT: retq
259 ;
260 ; SSSE3-LABEL: shuffle_v4f32_0022:
261 ; SSSE3: # %bb.0:
262 ; SSSE3-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
263 ; SSSE3-NEXT: retq
264 ;
265 ; SSE41-LABEL: shuffle_v4f32_0022:
266 ; SSE41: # %bb.0:
267 ; SSE41-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
268 ; SSE41-NEXT: retq
269 ;
270 ; AVX-LABEL: shuffle_v4f32_0022:
271 ; AVX: # %bb.0:
272 ; AVX-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
273 ; AVX-NEXT: retq
274 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
275 ret <4 x float> %shuffle
276 }
277 define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
278 ; SSE2-LABEL: shuffle_v4f32_1133:
279 ; SSE2: # %bb.0:
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3]
281 ; SSE2-NEXT: retq
282 ;
283 ; SSE3-LABEL: shuffle_v4f32_1133:
284 ; SSE3: # %bb.0:
285 ; SSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
286 ; SSE3-NEXT: retq
287 ;
288 ; SSSE3-LABEL: shuffle_v4f32_1133:
289 ; SSSE3: # %bb.0:
290 ; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
291 ; SSSE3-NEXT: retq
292 ;
293 ; SSE41-LABEL: shuffle_v4f32_1133:
294 ; SSE41: # %bb.0:
295 ; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
296 ; SSE41-NEXT: retq
297 ;
298 ; AVX-LABEL: shuffle_v4f32_1133:
299 ; AVX: # %bb.0:
300 ; AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
301 ; AVX-NEXT: retq
302 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
303 ret <4 x float> %shuffle
304 }
306 define <4 x float> @shuffle_v4f32_0145(<4 x float> %a, <4 x float> %b) {
307 ; SSE-LABEL: shuffle_v4f32_0145:
308 ; SSE: # %bb.0:
309 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
310 ; SSE-NEXT: retq
311 ;
312 ; AVX-LABEL: shuffle_v4f32_0145:
313 ; AVX: # %bb.0:
314 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
315 ; AVX-NEXT: retq
316 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
317 ret <4 x float> %shuffle
318 }
320 define <4 x float> @shuffle_v4f32_6723(<4 x float> %a, <4 x float> %b) {
321 ; SSE-LABEL: shuffle_v4f32_6723:
322 ; SSE: # %bb.0:
323 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
324 ; SSE-NEXT: retq
325 ;
326 ; AVX-LABEL: shuffle_v4f32_6723:
327 ; AVX: # %bb.0:
328 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
329 ; AVX-NEXT: retq
330 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
331 ret <4 x float> %shuffle
332 }
334 define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) {
335 ; SSE2-LABEL: shuffle_v4i32_0124:
336 ; SSE2: # %bb.0:
337 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
338 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
339 ; SSE2-NEXT: retq
340 ;
341 ; SSE3-LABEL: shuffle_v4i32_0124:
342 ; SSE3: # %bb.0:
343 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
344 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
345 ; SSE3-NEXT: retq
346 ;
347 ; SSSE3-LABEL: shuffle_v4i32_0124:
348 ; SSSE3: # %bb.0:
349 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
350 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
351 ; SSSE3-NEXT: retq
352 ;
353 ; SSE41-LABEL: shuffle_v4i32_0124:
354 ; SSE41: # %bb.0:
355 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
356 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
357 ; SSE41-NEXT: retq
358 ;
359 ; AVX1-LABEL: shuffle_v4i32_0124:
360 ; AVX1: # %bb.0:
361 ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
362 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
363 ; AVX1-NEXT: retq
364 ;
365 ; AVX2-LABEL: shuffle_v4i32_0124:
366 ; AVX2: # %bb.0:
367 ; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
368 ; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
369 ; AVX2-NEXT: retq
370 ;
371 ; AVX512VL-LABEL: shuffle_v4i32_0124:
372 ; AVX512VL: # %bb.0:
373 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,1,2,4]
374 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
375 ; AVX512VL-NEXT: retq
376 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
377 ret <4 x i32> %shuffle
378 }
379 define <4 x i32> @shuffle_v4i32_0142(<4 x i32> %a, <4 x i32> %b) {
380 ; SSE2-LABEL: shuffle_v4i32_0142:
381 ; SSE2: # %bb.0:
382 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
383 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
384 ; SSE2-NEXT: retq
385 ;
386 ; SSE3-LABEL: shuffle_v4i32_0142:
387 ; SSE3: # %bb.0:
388 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
389 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
390 ; SSE3-NEXT: retq
391 ;
392 ; SSSE3-LABEL: shuffle_v4i32_0142:
393 ; SSSE3: # %bb.0:
394 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
395 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
396 ; SSSE3-NEXT: retq
397 ;
398 ; SSE41-LABEL: shuffle_v4i32_0142:
399 ; SSE41: # %bb.0:
400 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
401 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
402 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
403 ; SSE41-NEXT: retq
404 ;
405 ; AVX1-LABEL: shuffle_v4i32_0142:
406 ; AVX1: # %bb.0:
407 ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,1,0,1]
408 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,2,2]
409 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
410 ; AVX1-NEXT: retq
411 ;
412 ; AVX2-LABEL: shuffle_v4i32_0142:
413 ; AVX2: # %bb.0:
414 ; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
415 ; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,2,2]
416 ; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
417 ; AVX2-NEXT: retq
418 ;
419 ; AVX512VL-LABEL: shuffle_v4i32_0142:
420 ; AVX512VL: # %bb.0:
421 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,1,4,2]
422 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
423 ; AVX512VL-NEXT: retq
424 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
425 ret <4 x i32> %shuffle
426 }
427 define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) {
428 ; SSE2-LABEL: shuffle_v4i32_0412:
429 ; SSE2: # %bb.0:
430 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
431 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
432 ; SSE2-NEXT: movaps %xmm1, %xmm0
433 ; SSE2-NEXT: retq
434 ;
435 ; SSE3-LABEL: shuffle_v4i32_0412:
436 ; SSE3: # %bb.0:
437 ; SSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
438 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
439 ; SSE3-NEXT: movaps %xmm1, %xmm0
440 ; SSE3-NEXT: retq
441 ;
442 ; SSSE3-LABEL: shuffle_v4i32_0412:
443 ; SSSE3: # %bb.0:
444 ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
445 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
446 ; SSSE3-NEXT: movaps %xmm1, %xmm0
447 ; SSSE3-NEXT: retq
448 ;
449 ; SSE41-LABEL: shuffle_v4i32_0412:
450 ; SSE41: # %bb.0:
451 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
452 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
453 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
454 ; SSE41-NEXT: retq
455 ;
456 ; AVX1-LABEL: shuffle_v4i32_0412:
457 ; AVX1: # %bb.0:
458 ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0,1,1]
459 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,1,2]
460 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
461 ; AVX1-NEXT: retq
462 ;
463 ; AVX2-LABEL: shuffle_v4i32_0412:
464 ; AVX2: # %bb.0:
465 ; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
466 ; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,1,2]
467 ; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
468 ; AVX2-NEXT: retq
469 ;
470 ; AVX512VL-LABEL: shuffle_v4i32_0412:
471 ; AVX512VL: # %bb.0:
472 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,4,1,2]
473 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
474 ; AVX512VL-NEXT: retq
475 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
476 ret <4 x i32> %shuffle
477 }
478 define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) {
479 ; SSE2-LABEL: shuffle_v4i32_4012:
480 ; SSE2: # %bb.0:
481 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
482 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
483 ; SSE2-NEXT: movaps %xmm1, %xmm0
484 ; SSE2-NEXT: retq
485 ;
486 ; SSE3-LABEL: shuffle_v4i32_4012:
487 ; SSE3: # %bb.0:
488 ; SSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
489 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
490 ; SSE3-NEXT: movaps %xmm1, %xmm0
491 ; SSE3-NEXT: retq
492 ;
493 ; SSSE3-LABEL: shuffle_v4i32_4012:
494 ; SSSE3: # %bb.0:
495 ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
496 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
497 ; SSSE3-NEXT: movaps %xmm1, %xmm0
498 ; SSSE3-NEXT: retq
499 ;
500 ; SSE41-LABEL: shuffle_v4i32_4012:
501 ; SSE41: # %bb.0:
502 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
503 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
504 ; SSE41-NEXT: retq
505 ;
506 ; AVX1OR2-LABEL: shuffle_v4i32_4012:
507 ; AVX1OR2: # %bb.0:
508 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,1,2]
509 ; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
510 ; AVX1OR2-NEXT: retq
511 ;
512 ; AVX512VL-LABEL: shuffle_v4i32_4012:
513 ; AVX512VL: # %bb.0:
514 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,0,1,2]
515 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
516 ; AVX512VL-NEXT: retq
517 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
518 ret <4 x i32> %shuffle
519 }
520 define <4 x i32> @shuffle_v4i32_0145(<4 x i32> %a, <4 x i32> %b) {
521 ; SSE-LABEL: shuffle_v4i32_0145:
522 ; SSE: # %bb.0:
523 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
524 ; SSE-NEXT: retq
525 ;
526 ; AVX-LABEL: shuffle_v4i32_0145:
527 ; AVX: # %bb.0:
528 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
529 ; AVX-NEXT: retq
530 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
531 ret <4 x i32> %shuffle
532 }
533 define <4 x i32> @shuffle_v4i32_0451(<4 x i32> %a, <4 x i32> %b) {
534 ; SSE-LABEL: shuffle_v4i32_0451:
535 ; SSE: # %bb.0:
536 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
537 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
538 ; SSE-NEXT: retq
539 ;
540 ; AVX1OR2-LABEL: shuffle_v4i32_0451:
541 ; AVX1OR2: # %bb.0:
542 ; AVX1OR2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
543 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,3,2]
544 ; AVX1OR2-NEXT: retq
545 ;
546 ; AVX512VL-LABEL: shuffle_v4i32_0451:
547 ; AVX512VL: # %bb.0:
548 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,4,5,1]
549 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
550 ; AVX512VL-NEXT: retq
551 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1>
552 ret <4 x i32> %shuffle
553 }
554 define <4 x i32> @shuffle_v4i32_4501(<4 x i32> %a, <4 x i32> %b) {
555 ; SSE-LABEL: shuffle_v4i32_4501:
556 ; SSE: # %bb.0:
557 ; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
558 ; SSE-NEXT: movaps %xmm1, %xmm0
559 ; SSE-NEXT: retq
560 ;
561 ; AVX-LABEL: shuffle_v4i32_4501:
562 ; AVX: # %bb.0:
563 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
564 ; AVX-NEXT: retq
565 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
566 ret <4 x i32> %shuffle
567 }
568 define <4 x i32> @shuffle_v4i32_4015(<4 x i32> %a, <4 x i32> %b) {
569 ; SSE-LABEL: shuffle_v4i32_4015:
570 ; SSE: # %bb.0:
571 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
572 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3]
573 ; SSE-NEXT: retq
574 ;
575 ; AVX1OR2-LABEL: shuffle_v4i32_4015:
576 ; AVX1OR2: # %bb.0:
577 ; AVX1OR2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
578 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,2,3]
579 ; AVX1OR2-NEXT: retq
580 ;
581 ; AVX512VL-LABEL: shuffle_v4i32_4015:
582 ; AVX512VL: # %bb.0:
583 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,0,1,5]
584 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
585 ; AVX512VL-NEXT: retq
586 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5>
587 ret <4 x i32> %shuffle
588 }
590 define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
591 ; SSE2-LABEL: shuffle_v4f32_4zzz:
592 ; SSE2: # %bb.0:
593 ; SSE2-NEXT: xorps %xmm1, %xmm1
594 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
595 ; SSE2-NEXT: movaps %xmm1, %xmm0
596 ; SSE2-NEXT: retq
597 ;
598 ; SSE3-LABEL: shuffle_v4f32_4zzz:
599 ; SSE3: # %bb.0:
600 ; SSE3-NEXT: xorps %xmm1, %xmm1
601 ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
602 ; SSE3-NEXT: movaps %xmm1, %xmm0
603 ; SSE3-NEXT: retq
604 ;
605 ; SSSE3-LABEL: shuffle_v4f32_4zzz:
606 ; SSSE3: # %bb.0:
607 ; SSSE3-NEXT: xorps %xmm1, %xmm1
608 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
609 ; SSSE3-NEXT: movaps %xmm1, %xmm0
610 ; SSSE3-NEXT: retq
611 ;
612 ; SSE41-LABEL: shuffle_v4f32_4zzz:
613 ; SSE41: # %bb.0:
614 ; SSE41-NEXT: xorps %xmm1, %xmm1
615 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
616 ; SSE41-NEXT: retq
617 ;
618 ; AVX-LABEL: shuffle_v4f32_4zzz:
619 ; AVX: # %bb.0:
620 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
621 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
622 ; AVX-NEXT: retq
623 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
624 ret <4 x float> %shuffle
625 }
627 define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
628 ; SSE2-LABEL: shuffle_v4f32_z4zz:
629 ; SSE2: # %bb.0:
630 ; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
631 ; SSE2-NEXT: xorps %xmm1, %xmm1
632 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
633 ; SSE2-NEXT: retq
634 ;
635 ; SSE3-LABEL: shuffle_v4f32_z4zz:
636 ; SSE3: # %bb.0:
637 ; SSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
638 ; SSE3-NEXT: xorps %xmm1, %xmm1
639 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
640 ; SSE3-NEXT: retq
641 ;
642 ; SSSE3-LABEL: shuffle_v4f32_z4zz:
643 ; SSSE3: # %bb.0:
644 ; SSSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
645 ; SSSE3-NEXT: xorps %xmm1, %xmm1
646 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
647 ; SSSE3-NEXT: retq
648 ;
649 ; SSE41-LABEL: shuffle_v4f32_z4zz:
650 ; SSE41: # %bb.0:
651 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
652 ; SSE41-NEXT: retq
653 ;
654 ; AVX-LABEL: shuffle_v4f32_z4zz:
655 ; AVX: # %bb.0:
656 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
657 ; AVX-NEXT: retq
658 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
659 ret <4 x float> %shuffle
660 }
662 define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
663 ; SSE2-LABEL: shuffle_v4f32_zz4z:
664 ; SSE2: # %bb.0:
665 ; SSE2-NEXT: movq {{.*#+}} xmm1 = xmm0[0],zero
666 ; SSE2-NEXT: pxor %xmm0, %xmm0
667 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
668 ; SSE2-NEXT: retq
669 ;
670 ; SSE3-LABEL: shuffle_v4f32_zz4z:
671 ; SSE3: # %bb.0:
672 ; SSE3-NEXT: movq {{.*#+}} xmm1 = xmm0[0],zero
673 ; SSE3-NEXT: pxor %xmm0, %xmm0
674 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
675 ; SSE3-NEXT: retq
676 ;
677 ; SSSE3-LABEL: shuffle_v4f32_zz4z:
678 ; SSSE3: # %bb.0:
679 ; SSSE3-NEXT: movq {{.*#+}} xmm1 = xmm0[0],zero
680 ; SSSE3-NEXT: pxor %xmm0, %xmm0
681 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
682 ; SSSE3-NEXT: retq
683 ;
684 ; SSE41-LABEL: shuffle_v4f32_zz4z:
685 ; SSE41: # %bb.0:
686 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,xmm0[0],zero
687 ; SSE41-NEXT: retq
688 ;
689 ; AVX-LABEL: shuffle_v4f32_zz4z:
690 ; AVX: # %bb.0:
691 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,xmm0[0],zero
692 ; AVX-NEXT: retq
693 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
694 ret <4 x float> %shuffle
695 }
697 define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) {
698 ; SSE2-LABEL: shuffle_v4f32_zuu4:
699 ; SSE2: # %bb.0:
700 ; SSE2-NEXT: xorps %xmm1, %xmm1
701 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
702 ; SSE2-NEXT: movaps %xmm1, %xmm0
703 ; SSE2-NEXT: retq
704 ;
705 ; SSE3-LABEL: shuffle_v4f32_zuu4:
706 ; SSE3: # %bb.0:
707 ; SSE3-NEXT: xorps %xmm1, %xmm1
708 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
709 ; SSE3-NEXT: movaps %xmm1, %xmm0
710 ; SSE3-NEXT: retq
711 ;
712 ; SSSE3-LABEL: shuffle_v4f32_zuu4:
713 ; SSSE3: # %bb.0:
714 ; SSSE3-NEXT: xorps %xmm1, %xmm1
715 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
716 ; SSSE3-NEXT: movaps %xmm1, %xmm0
717 ; SSSE3-NEXT: retq
718 ;
719 ; SSE41-LABEL: shuffle_v4f32_zuu4:
720 ; SSE41: # %bb.0:
721 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[0]
722 ; SSE41-NEXT: retq
723 ;
724 ; AVX-LABEL: shuffle_v4f32_zuu4:
725 ; AVX: # %bb.0:
726 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[0]
727 ; AVX-NEXT: retq
728 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
729 ret <4 x float> %shuffle
730 }
732 define <4 x float> @shuffle_v4f32_zzz7(<4 x float> %a) {
733 ; SSE2-LABEL: shuffle_v4f32_zzz7:
734 ; SSE2: # %bb.0:
735 ; SSE2-NEXT: xorps %xmm1, %xmm1
736 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
737 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
738 ; SSE2-NEXT: movaps %xmm1, %xmm0
739 ; SSE2-NEXT: retq
740 ;
741 ; SSE3-LABEL: shuffle_v4f32_zzz7:
742 ; SSE3: # %bb.0:
743 ; SSE3-NEXT: xorps %xmm1, %xmm1
744 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
745 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
746 ; SSE3-NEXT: movaps %xmm1, %xmm0
747 ; SSE3-NEXT: retq
748 ;
749 ; SSSE3-LABEL: shuffle_v4f32_zzz7:
750 ; SSSE3: # %bb.0:
751 ; SSSE3-NEXT: xorps %xmm1, %xmm1
752 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
753 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
754 ; SSSE3-NEXT: movaps %xmm1, %xmm0
755 ; SSSE3-NEXT: retq
756 ;
757 ; SSE41-LABEL: shuffle_v4f32_zzz7:
758 ; SSE41: # %bb.0:
759 ; SSE41-NEXT: xorps %xmm1, %xmm1
760 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
761 ; SSE41-NEXT: retq
762 ;
763 ; AVX-LABEL: shuffle_v4f32_zzz7:
764 ; AVX: # %bb.0:
765 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
766 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
767 ; AVX-NEXT: retq
768 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
769 ret <4 x float> %shuffle
770 }
772 define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
773 ; SSE2-LABEL: shuffle_v4f32_z6zz:
774 ; SSE2: # %bb.0:
775 ; SSE2-NEXT: xorps %xmm1, %xmm1
776 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
777 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
778 ; SSE2-NEXT: retq
779 ;
780 ; SSE3-LABEL: shuffle_v4f32_z6zz:
781 ; SSE3: # %bb.0:
782 ; SSE3-NEXT: xorps %xmm1, %xmm1
783 ; SSE3-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
784 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
785 ; SSE3-NEXT: retq
786 ;
787 ; SSSE3-LABEL: shuffle_v4f32_z6zz:
788 ; SSSE3: # %bb.0:
789 ; SSSE3-NEXT: xorps %xmm1, %xmm1
790 ; SSSE3-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
791 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
792 ; SSSE3-NEXT: retq
793 ;
794 ; SSE41-LABEL: shuffle_v4f32_z6zz:
795 ; SSE41: # %bb.0:
796 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero
797 ; SSE41-NEXT: retq
798 ;
799 ; AVX-LABEL: shuffle_v4f32_z6zz:
800 ; AVX: # %bb.0:
801 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero
802 ; AVX-NEXT: retq
803 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
804 ret <4 x float> %shuffle
805 }
807 define <4 x float> @shuffle_v4f32_0z23(<4 x float> %a) {
808 ; SSE2-LABEL: shuffle_v4f32_0z23:
809 ; SSE2: # %bb.0:
810 ; SSE2-NEXT: xorps %xmm1, %xmm1
811 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
812 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
813 ; SSE2-NEXT: movaps %xmm1, %xmm0
814 ; SSE2-NEXT: retq
815 ;
816 ; SSE3-LABEL: shuffle_v4f32_0z23:
817 ; SSE3: # %bb.0:
818 ; SSE3-NEXT: xorps %xmm1, %xmm1
819 ; SSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
820 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
821 ; SSE3-NEXT: movaps %xmm1, %xmm0
822 ; SSE3-NEXT: retq
823 ;
824 ; SSSE3-LABEL: shuffle_v4f32_0z23:
825 ; SSSE3: # %bb.0:
826 ; SSSE3-NEXT: xorps %xmm1, %xmm1
827 ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
828 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
829 ; SSSE3-NEXT: movaps %xmm1, %xmm0
830 ; SSSE3-NEXT: retq
831 ;
832 ; SSE41-LABEL: shuffle_v4f32_0z23:
833 ; SSE41: # %bb.0:
834 ; SSE41-NEXT: xorps %xmm1, %xmm1
835 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
836 ; SSE41-NEXT: retq
837 ;
838 ; AVX-LABEL: shuffle_v4f32_0z23:
839 ; AVX: # %bb.0:
840 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
841 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
842 ; AVX-NEXT: retq
843 %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
844 ret <4 x float> %shuffle
845 }
847 define <4 x float> @shuffle_v4f32_01z3(<4 x float> %a) {
848 ; SSE2-LABEL: shuffle_v4f32_01z3:
849 ; SSE2: # %bb.0:
850 ; SSE2-NEXT: xorps %xmm1, %xmm1
851 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
852 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
853 ; SSE2-NEXT: retq
854 ;
855 ; SSE3-LABEL: shuffle_v4f32_01z3:
856 ; SSE3: # %bb.0:
857 ; SSE3-NEXT: xorps %xmm1, %xmm1
858 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
859 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
860 ; SSE3-NEXT: retq
861 ;
862 ; SSSE3-LABEL: shuffle_v4f32_01z3:
863 ; SSSE3: # %bb.0:
864 ; SSSE3-NEXT: xorps %xmm1, %xmm1
865 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
866 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
867 ; SSSE3-NEXT: retq
868 ;
869 ; SSE41-LABEL: shuffle_v4f32_01z3:
870 ; SSE41: # %bb.0:
871 ; SSE41-NEXT: xorps %xmm1, %xmm1
872 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
873 ; SSE41-NEXT: retq
874 ;
875 ; AVX-LABEL: shuffle_v4f32_01z3:
876 ; AVX: # %bb.0:
877 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
878 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
879 ; AVX-NEXT: retq
880 %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
881 ret <4 x float> %shuffle
882 }
884 define <4 x float> @shuffle_v4f32_012z(<4 x float> %a) {
885 ; SSE2-LABEL: shuffle_v4f32_012z:
886 ; SSE2: # %bb.0:
887 ; SSE2-NEXT: xorps %xmm1, %xmm1
888 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
889 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
890 ; SSE2-NEXT: retq
891 ;
892 ; SSE3-LABEL: shuffle_v4f32_012z:
893 ; SSE3: # %bb.0:
894 ; SSE3-NEXT: xorps %xmm1, %xmm1
895 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
896 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
897 ; SSE3-NEXT: retq
898 ;
899 ; SSSE3-LABEL: shuffle_v4f32_012z:
900 ; SSSE3: # %bb.0:
901 ; SSSE3-NEXT: xorps %xmm1, %xmm1
902 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
903 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
904 ; SSSE3-NEXT: retq
905 ;
906 ; SSE41-LABEL: shuffle_v4f32_012z:
907 ; SSE41: # %bb.0:
908 ; SSE41-NEXT: xorps %xmm1, %xmm1
909 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
910 ; SSE41-NEXT: retq
911 ;
912 ; AVX-LABEL: shuffle_v4f32_012z:
913 ; AVX: # %bb.0:
914 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
915 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
916 ; AVX-NEXT: retq
917 %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
918 ret <4 x float> %shuffle
919 }
921 define <4 x float> @shuffle_v4f32_0zz3(<4 x float> %a) {
922 ; SSE2-LABEL: shuffle_v4f32_0zz3:
923 ; SSE2: # %bb.0:
924 ; SSE2-NEXT: xorps %xmm1, %xmm1
925 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[1,2]
926 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
927 ; SSE2-NEXT: retq
928 ;
929 ; SSE3-LABEL: shuffle_v4f32_0zz3:
930 ; SSE3: # %bb.0:
931 ; SSE3-NEXT: xorps %xmm1, %xmm1
932 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[1,2]
933 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
934 ; SSE3-NEXT: retq
935 ;
936 ; SSSE3-LABEL: shuffle_v4f32_0zz3:
937 ; SSSE3: # %bb.0:
938 ; SSSE3-NEXT: xorps %xmm1, %xmm1
939 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[1,2]
940 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
941 ; SSSE3-NEXT: retq
942 ;
943 ; SSE41-LABEL: shuffle_v4f32_0zz3:
944 ; SSE41: # %bb.0:
945 ; SSE41-NEXT: xorps %xmm1, %xmm1
946 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
947 ; SSE41-NEXT: retq
948 ;
949 ; AVX-LABEL: shuffle_v4f32_0zz3:
950 ; AVX: # %bb.0:
951 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
952 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
953 ; AVX-NEXT: retq
954 %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
955 ret <4 x float> %shuffle
956 }
958 define <4 x float> @shuffle_v4f32_0z2z(<4 x float> %v) {
959 ; SSE2-LABEL: shuffle_v4f32_0z2z:
960 ; SSE2: # %bb.0:
961 ; SSE2-NEXT: xorps %xmm1, %xmm1
962 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
963 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
964 ; SSE2-NEXT: retq
965 ;
966 ; SSE3-LABEL: shuffle_v4f32_0z2z:
967 ; SSE3: # %bb.0:
968 ; SSE3-NEXT: xorps %xmm1, %xmm1
969 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
970 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
971 ; SSE3-NEXT: retq
972 ;
973 ; SSSE3-LABEL: shuffle_v4f32_0z2z:
974 ; SSSE3: # %bb.0:
975 ; SSSE3-NEXT: xorps %xmm1, %xmm1
976 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
977 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
978 ; SSSE3-NEXT: retq
979 ;
980 ; SSE41-LABEL: shuffle_v4f32_0z2z:
981 ; SSE41: # %bb.0:
982 ; SSE41-NEXT: xorps %xmm1, %xmm1
983 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
984 ; SSE41-NEXT: retq
985 ;
986 ; AVX-LABEL: shuffle_v4f32_0z2z:
987 ; AVX: # %bb.0:
988 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
989 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
990 ; AVX-NEXT: retq
991 %shuffle = shufflevector <4 x float> %v, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 2, i32 4>
992 ret <4 x float> %shuffle
993 }
995 define <4 x float> @shuffle_v4f32_u051(<4 x float> %a, <4 x float> %b) {
996 ; SSE-LABEL: shuffle_v4f32_u051:
997 ; SSE: # %bb.0:
998 ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
999 ; SSE-NEXT: movaps %xmm1, %xmm0
1000 ; SSE-NEXT: retq
1001 ;
1002 ; AVX-LABEL: shuffle_v4f32_u051:
1003 ; AVX: # %bb.0:
1004 ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1005 ; AVX-NEXT: retq
1006 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 undef, i32 0, i32 5, i32 1>
1007 ret <4 x float> %shuffle
1008 }
1010 define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %a, <4 x float> %b) {
1011 ; SSE2-LABEL: shuffle_v4f32_0zz4:
1012 ; SSE2: # %bb.0:
1013 ; SSE2-NEXT: movq {{.*#+}} xmm2 = xmm1[0],zero
1014 ; SSE2-NEXT: pxor %xmm1, %xmm1
1015 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
1016 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1017 ; SSE2-NEXT: movaps %xmm1, %xmm0
1018 ; SSE2-NEXT: retq
1019 ;
1020 ; SSE3-LABEL: shuffle_v4f32_0zz4:
1021 ; SSE3: # %bb.0:
1022 ; SSE3-NEXT: movq {{.*#+}} xmm2 = xmm1[0],zero
1023 ; SSE3-NEXT: pxor %xmm1, %xmm1
1024 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
1025 ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1026 ; SSE3-NEXT: movaps %xmm1, %xmm0
1027 ; SSE3-NEXT: retq
1028 ;
1029 ; SSSE3-LABEL: shuffle_v4f32_0zz4:
1030 ; SSSE3: # %bb.0:
1031 ; SSSE3-NEXT: movq {{.*#+}} xmm2 = xmm1[0],zero
1032 ; SSSE3-NEXT: pxor %xmm1, %xmm1
1033 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
1034 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1035 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1036 ; SSSE3-NEXT: retq
1037 ;
1038 ; SSE41-LABEL: shuffle_v4f32_0zz4:
1039 ; SSE41: # %bb.0:
1040 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
1041 ; SSE41-NEXT: retq
1042 ;
1043 ; AVX-LABEL: shuffle_v4f32_0zz4:
1044 ; AVX: # %bb.0:
1045 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
1046 ; AVX-NEXT: retq
1047 %shuffle = shufflevector <4 x float> %b, <4 x float> zeroinitializer, <4 x i32> <i32 undef, i32 5, i32 6, i32 0>
1048 %shuffle1 = shufflevector <4 x float> %a, <4 x float> %shuffle, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1049 ret <4 x float> %shuffle1
1050 }
1052 define <4 x float> @shuffle_v4f32_0zz6(<4 x float> %a, <4 x float> %b) {
1053 ; SSE2-LABEL: shuffle_v4f32_0zz6:
1054 ; SSE2: # %bb.0:
1055 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,2]
1056 ; SSE2-NEXT: xorps %xmm1, %xmm1
1057 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,2],xmm0[0,3]
1058 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0,1,3]
1059 ; SSE2-NEXT: movaps %xmm1, %xmm0
1060 ; SSE2-NEXT: retq
1061 ;
1062 ; SSE3-LABEL: shuffle_v4f32_0zz6:
1063 ; SSE3: # %bb.0:
1064 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,2]
1065 ; SSE3-NEXT: xorps %xmm1, %xmm1
1066 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,2],xmm0[0,3]
1067 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0,1,3]
1068 ; SSE3-NEXT: movaps %xmm1, %xmm0
1069 ; SSE3-NEXT: retq
1070 ;
1071 ; SSSE3-LABEL: shuffle_v4f32_0zz6:
1072 ; SSSE3: # %bb.0:
1073 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,2]
1074 ; SSSE3-NEXT: xorps %xmm1, %xmm1
1075 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,2],xmm0[0,3]
1076 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0,1,3]
1077 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1078 ; SSSE3-NEXT: retq
1079 ;
1080 ; SSE41-LABEL: shuffle_v4f32_0zz6:
1081 ; SSE41: # %bb.0:
1082 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[2]
1083 ; SSE41-NEXT: retq
1084 ;
1085 ; AVX-LABEL: shuffle_v4f32_0zz6:
1086 ; AVX: # %bb.0:
1087 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[2]
1088 ; AVX-NEXT: retq
1089 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 undef, i32 undef, i32 6>
1090 %shuffle1 = shufflevector <4 x float> zeroinitializer, <4 x float> %shuffle, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
1091 ret <4 x float> %shuffle1
1092 }
1094 define <4 x float> @shuffle_v4f32_0z24(<4 x float> %a, <4 x float> %b) {
1095 ; SSE2-LABEL: shuffle_v4f32_0z24:
1096 ; SSE2: # %bb.0:
1097 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
1098 ; SSE2-NEXT: xorps %xmm2, %xmm2
1099 ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
1100 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
1101 ; SSE2-NEXT: movaps %xmm2, %xmm0
1102 ; SSE2-NEXT: retq
1103 ;
1104 ; SSE3-LABEL: shuffle_v4f32_0z24:
1105 ; SSE3: # %bb.0:
1106 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
1107 ; SSE3-NEXT: xorps %xmm2, %xmm2
1108 ; SSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
1109 ; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
1110 ; SSE3-NEXT: movaps %xmm2, %xmm0
1111 ; SSE3-NEXT: retq
1112 ;
1113 ; SSSE3-LABEL: shuffle_v4f32_0z24:
1114 ; SSSE3: # %bb.0:
1115 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
1116 ; SSSE3-NEXT: xorps %xmm2, %xmm2
1117 ; SSSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
1118 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
1119 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1120 ; SSSE3-NEXT: retq
1121 ;
1122 ; SSE41-LABEL: shuffle_v4f32_0z24:
1123 ; SSE41: # %bb.0:
1124 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
1125 ; SSE41-NEXT: retq
1126 ;
1127 ; AVX-LABEL: shuffle_v4f32_0z24:
1128 ; AVX: # %bb.0:
1129 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
1130 ; AVX-NEXT: retq
1131 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 undef, i32 2, i32 4>
1132 %shuffle1 = shufflevector <4 x float> zeroinitializer, <4 x float> %shuffle, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1133 ret <4 x float> %shuffle1
1134 }
1136 define <4 x i32> @shuffle_v4i32_4zzz(<4 x i32> %a) {
1137 ; SSE2-LABEL: shuffle_v4i32_4zzz:
1138 ; SSE2: # %bb.0:
1139 ; SSE2-NEXT: xorps %xmm1, %xmm1
1140 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1141 ; SSE2-NEXT: movaps %xmm1, %xmm0
1142 ; SSE2-NEXT: retq
1143 ;
1144 ; SSE3-LABEL: shuffle_v4i32_4zzz:
1145 ; SSE3: # %bb.0:
1146 ; SSE3-NEXT: xorps %xmm1, %xmm1
1147 ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1148 ; SSE3-NEXT: movaps %xmm1, %xmm0
1149 ; SSE3-NEXT: retq
1150 ;
1151 ; SSSE3-LABEL: shuffle_v4i32_4zzz:
1152 ; SSSE3: # %bb.0:
1153 ; SSSE3-NEXT: xorps %xmm1, %xmm1
1154 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1155 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1156 ; SSSE3-NEXT: retq
1157 ;
1158 ; SSE41-LABEL: shuffle_v4i32_4zzz:
1159 ; SSE41: # %bb.0:
1160 ; SSE41-NEXT: xorps %xmm1, %xmm1
1161 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1162 ; SSE41-NEXT: retq
1163 ;
1164 ; AVX-LABEL: shuffle_v4i32_4zzz:
1165 ; AVX: # %bb.0:
1166 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
1167 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1168 ; AVX-NEXT: retq
1169 %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1170 ret <4 x i32> %shuffle
1171 }
1173 define <4 x i32> @shuffle_v4i32_z4zz(<4 x i32> %a) {
1174 ; SSE2-LABEL: shuffle_v4i32_z4zz:
1175 ; SSE2: # %bb.0:
1176 ; SSE2-NEXT: xorps %xmm1, %xmm1
1177 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1178 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
1179 ; SSE2-NEXT: retq
1180 ;
1181 ; SSE3-LABEL: shuffle_v4i32_z4zz:
1182 ; SSE3: # %bb.0:
1183 ; SSE3-NEXT: xorps %xmm1, %xmm1
1184 ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1185 ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
1186 ; SSE3-NEXT: retq
1187 ;
1188 ; SSSE3-LABEL: shuffle_v4i32_z4zz:
1189 ; SSSE3: # %bb.0:
1190 ; SSSE3-NEXT: xorps %xmm1, %xmm1
1191 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1192 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
1193 ; SSSE3-NEXT: retq
1194 ;
1195 ; SSE41-LABEL: shuffle_v4i32_z4zz:
1196 ; SSE41: # %bb.0:
1197 ; SSE41-NEXT: pxor %xmm1, %xmm1
1198 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1199 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
1200 ; SSE41-NEXT: retq
1201 ;
1202 ; AVX1-LABEL: shuffle_v4i32_z4zz:
1203 ; AVX1: # %bb.0:
1204 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
1205 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1206 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,1,1]
1207 ; AVX1-NEXT: retq
1208 ;
1209 ; AVX2-SLOW-LABEL: shuffle_v4i32_z4zz:
1210 ; AVX2-SLOW: # %bb.0:
1211 ; AVX2-SLOW-NEXT: vxorps %xmm1, %xmm1, %xmm1
1212 ; AVX2-SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1213 ; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,1,1]
1214 ; AVX2-SLOW-NEXT: retq
1215 ;
1216 ; AVX2-FAST-LABEL: shuffle_v4i32_z4zz:
1217 ; AVX2-FAST: # %bb.0:
1218 ; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero
1219 ; AVX2-FAST-NEXT: retq
1220 ;
1221 ; AVX512VL-LABEL: shuffle_v4i32_z4zz:
1222 ; AVX512VL: # %bb.0:
1223 ; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero
1224 ; AVX512VL-NEXT: retq
1225 %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
1226 ret <4 x i32> %shuffle
1227 }
1229 define <4 x i32> @shuffle_v4i32_zz4z(<4 x i32> %a) {
1230 ; SSE2-LABEL: shuffle_v4i32_zz4z:
1231 ; SSE2: # %bb.0:
1232 ; SSE2-NEXT: xorps %xmm1, %xmm1
1233 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1234 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
1235 ; SSE2-NEXT: retq
1236 ;
1237 ; SSE3-LABEL: shuffle_v4i32_zz4z:
1238 ; SSE3: # %bb.0:
1239 ; SSE3-NEXT: xorps %xmm1, %xmm1
1240 ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1241 ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
1242 ; SSE3-NEXT: retq
1243 ;
1244 ; SSSE3-LABEL: shuffle_v4i32_zz4z:
1245 ; SSSE3: # %bb.0:
1246 ; SSSE3-NEXT: xorps %xmm1, %xmm1
1247 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1248 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
1249 ; SSSE3-NEXT: retq
1250 ;
1251 ; SSE41-LABEL: shuffle_v4i32_zz4z:
1252 ; SSE41: # %bb.0:
1253 ; SSE41-NEXT: pxor %xmm1, %xmm1
1254 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1255 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
1256 ; SSE41-NEXT: retq
1257 ;
1258 ; AVX1-LABEL: shuffle_v4i32_zz4z:
1259 ; AVX1: # %bb.0:
1260 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
1261 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1262 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
1263 ; AVX1-NEXT: retq
1264 ;
1265 ; AVX2-SLOW-LABEL: shuffle_v4i32_zz4z:
1266 ; AVX2-SLOW: # %bb.0:
1267 ; AVX2-SLOW-NEXT: vxorps %xmm1, %xmm1, %xmm1
1268 ; AVX2-SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1269 ; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
1270 ; AVX2-SLOW-NEXT: retq
1271 ;
1272 ; AVX2-FAST-LABEL: shuffle_v4i32_zz4z:
1273 ; AVX2-FAST: # %bb.0:
1274 ; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3],zero,zero,zero,zero
1275 ; AVX2-FAST-NEXT: retq
1276 ;
1277 ; AVX512VL-LABEL: shuffle_v4i32_zz4z:
1278 ; AVX512VL: # %bb.0:
1279 ; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3],zero,zero,zero,zero
1280 ; AVX512VL-NEXT: retq
1281 %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
1282 ret <4 x i32> %shuffle
1283 }
1285 define <4 x i32> @shuffle_v4i32_zuu4(<4 x i32> %a) {
1286 ; SSE-LABEL: shuffle_v4i32_zuu4:
1287 ; SSE: # %bb.0:
1288 ; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
1289 ; SSE-NEXT: retq
1290 ;
1291 ; AVX-LABEL: shuffle_v4i32_zuu4:
1292 ; AVX: # %bb.0:
1293 ; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
1294 ; AVX-NEXT: retq
1295 %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
1296 ret <4 x i32> %shuffle
1297 }
1299 define <4 x i32> @shuffle_v4i32_z6zz(<4 x i32> %a) {
1300 ; SSE2-LABEL: shuffle_v4i32_z6zz:
1301 ; SSE2: # %bb.0:
1302 ; SSE2-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
1303 ; SSE2-NEXT: xorps %xmm1, %xmm1
1304 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1305 ; SSE2-NEXT: retq
1306 ;
1307 ; SSE3-LABEL: shuffle_v4i32_z6zz:
1308 ; SSE3: # %bb.0:
1309 ; SSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
1310 ; SSE3-NEXT: xorps %xmm1, %xmm1
1311 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1312 ; SSE3-NEXT: retq
1313 ;
1314 ; SSSE3-LABEL: shuffle_v4i32_z6zz:
1315 ; SSSE3: # %bb.0:
1316 ; SSSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
1317 ; SSSE3-NEXT: xorps %xmm1, %xmm1
1318 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1319 ; SSSE3-NEXT: retq
1320 ;
1321 ; SSE41-LABEL: shuffle_v4i32_z6zz:
1322 ; SSE41: # %bb.0:
1323 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
1324 ; SSE41-NEXT: pxor %xmm0, %xmm0
1325 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1326 ; SSE41-NEXT: retq
1327 ;
1328 ; AVX1-LABEL: shuffle_v4i32_z6zz:
1329 ; AVX1: # %bb.0:
1330 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]
1331 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
1332 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1333 ; AVX1-NEXT: retq
1334 ;
1335 ; AVX2-SLOW-LABEL: shuffle_v4i32_z6zz:
1336 ; AVX2-SLOW: # %bb.0:
1337 ; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]
1338 ; AVX2-SLOW-NEXT: vxorps %xmm1, %xmm1, %xmm1
1339 ; AVX2-SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1340 ; AVX2-SLOW-NEXT: retq
1341 ;
1342 ; AVX2-FAST-LABEL: shuffle_v4i32_z6zz:
1343 ; AVX2-FAST: # %bb.0:
1344 ; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[8,9,10,11],zero,zero,zero,zero,zero,zero,zero,zero
1345 ; AVX2-FAST-NEXT: retq
1346 ;
1347 ; AVX512VL-LABEL: shuffle_v4i32_z6zz:
1348 ; AVX512VL: # %bb.0:
1349 ; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[8,9,10,11],zero,zero,zero,zero,zero,zero,zero,zero
1350 ; AVX512VL-NEXT: retq
1351 %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
1352 ret <4 x i32> %shuffle
1353 }
1355 define <4 x i32> @shuffle_v4i32_7012(<4 x i32> %a, <4 x i32> %b) {
1356 ; SSE2-LABEL: shuffle_v4i32_7012:
1357 ; SSE2: # %bb.0:
1358 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[0,0]
1359 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
1360 ; SSE2-NEXT: movaps %xmm1, %xmm0
1361 ; SSE2-NEXT: retq
1362 ;
1363 ; SSE3-LABEL: shuffle_v4i32_7012:
1364 ; SSE3: # %bb.0:
1365 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[0,0]
1366 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
1367 ; SSE3-NEXT: movaps %xmm1, %xmm0
1368 ; SSE3-NEXT: retq
1369 ;
1370 ; SSSE3-LABEL: shuffle_v4i32_7012:
1371 ; SSSE3: # %bb.0:
1372 ; SSSE3-NEXT: palignr {{.*#+}} xmm0 = xmm1[12,13,14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
1373 ; SSSE3-NEXT: retq
1374 ;
1375 ; SSE41-LABEL: shuffle_v4i32_7012:
1376 ; SSE41: # %bb.0:
1377 ; SSE41-NEXT: palignr {{.*#+}} xmm0 = xmm1[12,13,14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
1378 ; SSE41-NEXT: retq
1379 ;
1380 ; AVX-LABEL: shuffle_v4i32_7012:
1381 ; AVX: # %bb.0:
1382 ; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[12,13,14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
1383 ; AVX-NEXT: retq
1384 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
1385 ret <4 x i32> %shuffle
1386 }
1388 define <4 x i32> @shuffle_v4i32_6701(<4 x i32> %a, <4 x i32> %b) {
1389 ; SSE2-LABEL: shuffle_v4i32_6701:
1390 ; SSE2: # %bb.0:
1391 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
1392 ; SSE2-NEXT: movaps %xmm1, %xmm0
1393 ; SSE2-NEXT: retq
1394 ;
1395 ; SSE3-LABEL: shuffle_v4i32_6701:
1396 ; SSE3: # %bb.0:
1397 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
1398 ; SSE3-NEXT: movaps %xmm1, %xmm0
1399 ; SSE3-NEXT: retq
1400 ;
1401 ; SSSE3-LABEL: shuffle_v4i32_6701:
1402 ; SSSE3: # %bb.0:
1403 ; SSSE3-NEXT: palignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
1404 ; SSSE3-NEXT: retq
1405 ;
1406 ; SSE41-LABEL: shuffle_v4i32_6701:
1407 ; SSE41: # %bb.0:
1408 ; SSE41-NEXT: palignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
1409 ; SSE41-NEXT: retq
1410 ;
1411 ; AVX-LABEL: shuffle_v4i32_6701:
1412 ; AVX: # %bb.0:
1413 ; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
1414 ; AVX-NEXT: retq
1415 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1416 ret <4 x i32> %shuffle
1417 }
1419 define <4 x i32> @shuffle_v4i32_5670(<4 x i32> %a, <4 x i32> %b) {
1420 ; SSE2-LABEL: shuffle_v4i32_5670:
1421 ; SSE2: # %bb.0:
1422 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1423 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,2],xmm0[2,0]
1424 ; SSE2-NEXT: movaps %xmm1, %xmm0
1425 ; SSE2-NEXT: retq
1426 ;
1427 ; SSE3-LABEL: shuffle_v4i32_5670:
1428 ; SSE3: # %bb.0:
1429 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1430 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,2],xmm0[2,0]
1431 ; SSE3-NEXT: movaps %xmm1, %xmm0
1432 ; SSE3-NEXT: retq
1433 ;
1434 ; SSSE3-LABEL: shuffle_v4i32_5670:
1435 ; SSSE3: # %bb.0:
1436 ; SSSE3-NEXT: palignr {{.*#+}} xmm0 = xmm1[4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3]
1437 ; SSSE3-NEXT: retq
1438 ;
1439 ; SSE41-LABEL: shuffle_v4i32_5670:
1440 ; SSE41: # %bb.0:
1441 ; SSE41-NEXT: palignr {{.*#+}} xmm0 = xmm1[4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3]
1442 ; SSE41-NEXT: retq
1443 ;
1444 ; AVX-LABEL: shuffle_v4i32_5670:
1445 ; AVX: # %bb.0:
1446 ; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3]
1447 ; AVX-NEXT: retq
1448 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
1449 ret <4 x i32> %shuffle
1450 }
1452 define <4 x i32> @shuffle_v4i32_1234(<4 x i32> %a, <4 x i32> %b) {
1453 ; SSE2-LABEL: shuffle_v4i32_1234:
1454 ; SSE2: # %bb.0:
1455 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
1456 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,2],xmm1[2,0]
1457 ; SSE2-NEXT: retq
1458 ;
1459 ; SSE3-LABEL: shuffle_v4i32_1234:
1460 ; SSE3: # %bb.0:
1461 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
1462 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,2],xmm1[2,0]
1463 ; SSE3-NEXT: retq
1464 ;
1465 ; SSSE3-LABEL: shuffle_v4i32_1234:
1466 ; SSSE3: # %bb.0:
1467 ; SSSE3-NEXT: palignr {{.*#+}} xmm1 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3]
1468 ; SSSE3-NEXT: movdqa %xmm1, %xmm0
1469 ; SSSE3-NEXT: retq
1470 ;
1471 ; SSE41-LABEL: shuffle_v4i32_1234:
1472 ; SSE41: # %bb.0:
1473 ; SSE41-NEXT: palignr {{.*#+}} xmm1 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3]
1474 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1475 ; SSE41-NEXT: retq
1476 ;
1477 ; AVX-LABEL: shuffle_v4i32_1234:
1478 ; AVX: # %bb.0:
1479 ; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3]
1480 ; AVX-NEXT: retq
1481 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
1482 ret <4 x i32> %shuffle
1483 }
1485 define <4 x i32> @shuffle_v4i32_2345(<4 x i32> %a, <4 x i32> %b) {
1486 ; SSE2-LABEL: shuffle_v4i32_2345:
1487 ; SSE2: # %bb.0:
1488 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,1]
1489 ; SSE2-NEXT: retq
1490 ;
1491 ; SSE3-LABEL: shuffle_v4i32_2345:
1492 ; SSE3: # %bb.0:
1493 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,1]
1494 ; SSE3-NEXT: retq
1495 ;
1496 ; SSSE3-LABEL: shuffle_v4i32_2345:
1497 ; SSSE3: # %bb.0:
1498 ; SSSE3-NEXT: palignr {{.*#+}} xmm1 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
1499 ; SSSE3-NEXT: movdqa %xmm1, %xmm0
1500 ; SSSE3-NEXT: retq
1501 ;
1502 ; SSE41-LABEL: shuffle_v4i32_2345:
1503 ; SSE41: # %bb.0:
1504 ; SSE41-NEXT: palignr {{.*#+}} xmm1 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
1505 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1506 ; SSE41-NEXT: retq
1507 ;
1508 ; AVX-LABEL: shuffle_v4i32_2345:
1509 ; AVX: # %bb.0:
1510 ; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
1511 ; AVX-NEXT: retq
1512 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
1513 ret <4 x i32> %shuffle
1514 }
1516 ; PR22391
1517 define <4 x i32> @shuffle_v4i32_2456(<4 x i32> %a, <4 x i32> %b) {
1518 ; SSE2-LABEL: shuffle_v4i32_2456:
1519 ; SSE2: # %bb.0:
1520 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,1]
1521 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
1522 ; SSE2-NEXT: retq
1523 ;
1524 ; SSE3-LABEL: shuffle_v4i32_2456:
1525 ; SSE3: # %bb.0:
1526 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,1]
1527 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
1528 ; SSE3-NEXT: retq
1529 ;
1530 ; SSSE3-LABEL: shuffle_v4i32_2456:
1531 ; SSSE3: # %bb.0:
1532 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
1533 ; SSSE3-NEXT: palignr {{.*#+}} xmm1 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
1534 ; SSSE3-NEXT: movdqa %xmm1, %xmm0
1535 ; SSSE3-NEXT: retq
1536 ;
1537 ; SSE41-LABEL: shuffle_v4i32_2456:
1538 ; SSE41: # %bb.0:
1539 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
1540 ; SSE41-NEXT: palignr {{.*#+}} xmm1 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
1541 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1542 ; SSE41-NEXT: retq
1543 ;
1544 ; AVX1OR2-LABEL: shuffle_v4i32_2456:
1545 ; AVX1OR2: # %bb.0:
1546 ; AVX1OR2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
1547 ; AVX1OR2-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
1548 ; AVX1OR2-NEXT: retq
1549 ;
1550 ; AVX512VL-LABEL: shuffle_v4i32_2456:
1551 ; AVX512VL: # %bb.0:
1552 ; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [6,0,1,2]
1553 ; AVX512VL-NEXT: vpermi2d %xmm0, %xmm1, %xmm2
1554 ; AVX512VL-NEXT: vmovdqa %xmm2, %xmm0
1555 ; AVX512VL-NEXT: retq
1556 %s1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
1557 %s2 = shufflevector <4 x i32> %s1, <4 x i32> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
1558 ret <4 x i32> %s2
1559 }
1561 define <4 x i32> @shuffle_v4i32_40u1(<4 x i32> %a, <4 x i32> %b) {
1562 ; SSE-LABEL: shuffle_v4i32_40u1:
1563 ; SSE: # %bb.0:
1564 ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1565 ; SSE-NEXT: movaps %xmm1, %xmm0
1566 ; SSE-NEXT: retq
1567 ;
1568 ; AVX-LABEL: shuffle_v4i32_40u1:
1569 ; AVX: # %bb.0:
1570 ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1571 ; AVX-NEXT: retq
1572 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 undef, i32 1>
1573 ret <4 x i32> %shuffle
1574 }
1576 define <4 x i32> @shuffle_v4i32_3456(<4 x i32> %a, <4 x i32> %b) {
1577 ; SSE2-LABEL: shuffle_v4i32_3456:
1578 ; SSE2: # %bb.0:
1579 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[0,0]
1580 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
1581 ; SSE2-NEXT: retq
1582 ;
1583 ; SSE3-LABEL: shuffle_v4i32_3456:
1584 ; SSE3: # %bb.0:
1585 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[0,0]
1586 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
1587 ; SSE3-NEXT: retq
1588 ;
1589 ; SSSE3-LABEL: shuffle_v4i32_3456:
1590 ; SSSE3: # %bb.0:
1591 ; SSSE3-NEXT: palignr {{.*#+}} xmm1 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
1592 ; SSSE3-NEXT: movdqa %xmm1, %xmm0
1593 ; SSSE3-NEXT: retq
1594 ;
1595 ; SSE41-LABEL: shuffle_v4i32_3456:
1596 ; SSE41: # %bb.0:
1597 ; SSE41-NEXT: palignr {{.*#+}} xmm1 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
1598 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1599 ; SSE41-NEXT: retq
1600 ;
1601 ; AVX-LABEL: shuffle_v4i32_3456:
1602 ; AVX: # %bb.0:
1603 ; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
1604 ; AVX-NEXT: retq
1605 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
1606 ret <4 x i32> %shuffle
1607 }
1609 define <4 x i32> @shuffle_v4i32_0u1u(<4 x i32> %a, <4 x i32> %b) {
1610 ; SSE2-LABEL: shuffle_v4i32_0u1u:
1611 ; SSE2: # %bb.0:
1612 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
1613 ; SSE2-NEXT: retq
1614 ;
1615 ; SSE3-LABEL: shuffle_v4i32_0u1u:
1616 ; SSE3: # %bb.0:
1617 ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
1618 ; SSE3-NEXT: retq
1619 ;
1620 ; SSSE3-LABEL: shuffle_v4i32_0u1u:
1621 ; SSSE3: # %bb.0:
1622 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
1623 ; SSSE3-NEXT: retq
1624 ;
1625 ; SSE41-LABEL: shuffle_v4i32_0u1u:
1626 ; SSE41: # %bb.0:
1627 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
1628 ; SSE41-NEXT: retq
1629 ;
1630 ; AVX-LABEL: shuffle_v4i32_0u1u:
1631 ; AVX: # %bb.0:
1632 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
1633 ; AVX-NEXT: retq
1634 %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
1635 ret <4 x i32> %shuffle
1636 }
1638 define <4 x i32> @shuffle_v4i32_0z1z(<4 x i32> %a) {
1639 ; SSE2-LABEL: shuffle_v4i32_0z1z:
1640 ; SSE2: # %bb.0:
1641 ; SSE2-NEXT: xorps %xmm1, %xmm1
1642 ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1643 ; SSE2-NEXT: retq
1644 ;
1645 ; SSE3-LABEL: shuffle_v4i32_0z1z:
1646 ; SSE3: # %bb.0:
1647 ; SSE3-NEXT: xorps %xmm1, %xmm1
1648 ; SSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1649 ; SSE3-NEXT: retq
1650 ;
1651 ; SSSE3-LABEL: shuffle_v4i32_0z1z:
1652 ; SSSE3: # %bb.0:
1653 ; SSSE3-NEXT: xorps %xmm1, %xmm1
1654 ; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1655 ; SSSE3-NEXT: retq
1656 ;
1657 ; SSE41-LABEL: shuffle_v4i32_0z1z:
1658 ; SSE41: # %bb.0:
1659 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
1660 ; SSE41-NEXT: retq
1661 ;
1662 ; AVX-LABEL: shuffle_v4i32_0z1z:
1663 ; AVX: # %bb.0:
1664 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
1665 ; AVX-NEXT: retq
1666 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1667 ret <4 x i32> %shuffle
1668 }
1670 define <4 x i32> @shuffle_v4i32_01zu(<4 x i32> %a) {
1671 ; SSE-LABEL: shuffle_v4i32_01zu:
1672 ; SSE: # %bb.0:
1673 ; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
1674 ; SSE-NEXT: retq
1675 ;
1676 ; AVX-LABEL: shuffle_v4i32_01zu:
1677 ; AVX: # %bb.0:
1678 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
1679 ; AVX-NEXT: retq
1680 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 7, i32 undef>
1681 ret <4 x i32> %shuffle
1682 }
1684 define <4 x i32> @shuffle_v4i32_0z23(<4 x i32> %a) {
1685 ; SSE2-LABEL: shuffle_v4i32_0z23:
1686 ; SSE2: # %bb.0:
1687 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1688 ; SSE2-NEXT: retq
1689 ;
1690 ; SSE3-LABEL: shuffle_v4i32_0z23:
1691 ; SSE3: # %bb.0:
1692 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1693 ; SSE3-NEXT: retq
1694 ;
1695 ; SSSE3-LABEL: shuffle_v4i32_0z23:
1696 ; SSSE3: # %bb.0:
1697 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1698 ; SSSE3-NEXT: retq
1699 ;
1700 ; SSE41-LABEL: shuffle_v4i32_0z23:
1701 ; SSE41: # %bb.0:
1702 ; SSE41-NEXT: xorps %xmm1, %xmm1
1703 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1704 ; SSE41-NEXT: retq
1705 ;
1706 ; AVX-LABEL: shuffle_v4i32_0z23:
1707 ; AVX: # %bb.0:
1708 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
1709 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1710 ; AVX-NEXT: retq
1711 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
1712 ret <4 x i32> %shuffle
1713 }
1715 define <4 x i32> @shuffle_v4i32_01z3(<4 x i32> %a) {
1716 ; SSE2-LABEL: shuffle_v4i32_01z3:
1717 ; SSE2: # %bb.0:
1718 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1719 ; SSE2-NEXT: retq
1720 ;
1721 ; SSE3-LABEL: shuffle_v4i32_01z3:
1722 ; SSE3: # %bb.0:
1723 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1724 ; SSE3-NEXT: retq
1725 ;
1726 ; SSSE3-LABEL: shuffle_v4i32_01z3:
1727 ; SSSE3: # %bb.0:
1728 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1729 ; SSSE3-NEXT: retq
1730 ;
1731 ; SSE41-LABEL: shuffle_v4i32_01z3:
1732 ; SSE41: # %bb.0:
1733 ; SSE41-NEXT: xorps %xmm1, %xmm1
1734 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
1735 ; SSE41-NEXT: retq
1736 ;
1737 ; AVX-LABEL: shuffle_v4i32_01z3:
1738 ; AVX: # %bb.0:
1739 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
1740 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
1741 ; AVX-NEXT: retq
1742 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
1743 ret <4 x i32> %shuffle
1744 }
1746 define <4 x i32> @shuffle_v4i32_012z(<4 x i32> %a) {
1747 ; SSE2-LABEL: shuffle_v4i32_012z:
1748 ; SSE2: # %bb.0:
1749 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1750 ; SSE2-NEXT: retq
1751 ;
1752 ; SSE3-LABEL: shuffle_v4i32_012z:
1753 ; SSE3: # %bb.0:
1754 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1755 ; SSE3-NEXT: retq
1756 ;
1757 ; SSSE3-LABEL: shuffle_v4i32_012z:
1758 ; SSSE3: # %bb.0:
1759 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1760 ; SSSE3-NEXT: retq
1761 ;
1762 ; SSE41-LABEL: shuffle_v4i32_012z:
1763 ; SSE41: # %bb.0:
1764 ; SSE41-NEXT: xorps %xmm1, %xmm1
1765 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
1766 ; SSE41-NEXT: retq
1767 ;
1768 ; AVX-LABEL: shuffle_v4i32_012z:
1769 ; AVX: # %bb.0:
1770 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
1771 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
1772 ; AVX-NEXT: retq
1773 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1774 ret <4 x i32> %shuffle
1775 }
1777 define <4 x i32> @shuffle_v4i32_0zz3(<4 x i32> %a) {
1778 ; SSE2-LABEL: shuffle_v4i32_0zz3:
1779 ; SSE2: # %bb.0:
1780 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1781 ; SSE2-NEXT: retq
1782 ;
1783 ; SSE3-LABEL: shuffle_v4i32_0zz3:
1784 ; SSE3: # %bb.0:
1785 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1786 ; SSE3-NEXT: retq
1787 ;
1788 ; SSSE3-LABEL: shuffle_v4i32_0zz3:
1789 ; SSSE3: # %bb.0:
1790 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1791 ; SSSE3-NEXT: retq
1792 ;
1793 ; SSE41-LABEL: shuffle_v4i32_0zz3:
1794 ; SSE41: # %bb.0:
1795 ; SSE41-NEXT: xorps %xmm1, %xmm1
1796 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
1797 ; SSE41-NEXT: retq
1798 ;
1799 ; AVX-LABEL: shuffle_v4i32_0zz3:
1800 ; AVX: # %bb.0:
1801 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
1802 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
1803 ; AVX-NEXT: retq
1804 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
1805 ret <4 x i32> %shuffle
1806 }
1808 define <4 x i32> @shuffle_v4i32_bitcast_0415(<4 x i32> %a, <4 x i32> %b) {
1809 ; SSE-LABEL: shuffle_v4i32_bitcast_0415:
1810 ; SSE: # %bb.0:
1811 ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1812 ; SSE-NEXT: retq
1813 ;
1814 ; AVX-LABEL: shuffle_v4i32_bitcast_0415:
1815 ; AVX: # %bb.0:
1816 ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1817 ; AVX-NEXT: retq
1818 %shuffle32 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 0, i32 4>
1819 %bitcast64 = bitcast <4 x i32> %shuffle32 to <2 x double>
1820 %shuffle64 = shufflevector <2 x double> %bitcast64, <2 x double> undef, <2 x i32> <i32 1, i32 0>
1821 %bitcast32 = bitcast <2 x double> %shuffle64 to <4 x i32>
1822 ret <4 x i32> %bitcast32
1823 }
1825 define <4 x float> @shuffle_v4f32_bitcast_4401(<4 x float> %a, <4 x i32> %b) {
1826 ; SSE-LABEL: shuffle_v4f32_bitcast_4401:
1827 ; SSE: # %bb.0:
1828 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,1]
1829 ; SSE-NEXT: movaps %xmm1, %xmm0
1830 ; SSE-NEXT: retq
1831 ;
1832 ; AVX-LABEL: shuffle_v4f32_bitcast_4401:
1833 ; AVX: # %bb.0:
1834 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[0,1]
1835 ; AVX-NEXT: retq
1836 %1 = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
1837 %2 = bitcast <4 x i32> %1 to <2 x double>
1838 %3 = bitcast <4 x float> %a to <2 x double>
1839 %4 = shufflevector <2 x double> %2, <2 x double> %3, <2 x i32> <i32 0, i32 2>
1840 %5 = bitcast <2 x double> %4 to <4 x float>
1841 ret <4 x float> %5
1842 }
1844 define <4 x float> @shuffle_v4f32_bitcast_0045(<4 x float> %a, <4 x i32> %b) {
1845 ; SSE-LABEL: shuffle_v4f32_bitcast_0045:
1846 ; SSE: # %bb.0:
1847 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,1]
1848 ; SSE-NEXT: retq
1849 ;
1850 ; AVX-LABEL: shuffle_v4f32_bitcast_0045:
1851 ; AVX: # %bb.0:
1852 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,1]
1853 ; AVX-NEXT: retq
1854 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
1855 %2 = bitcast <4 x i32> %b to <4 x float>
1856 %3 = shufflevector <4 x float> %1, <4 x float> %2, <4 x i32> <i32 1, i32 0, i32 4, i32 5>
1857 ret <4 x float> %3
1858 }
1860 define <4 x float> @mask_v4f32_4127(<4 x float> %a, <4 x float> %b) {
1861 ; SSE2-LABEL: mask_v4f32_4127:
1862 ; SSE2: # %bb.0:
1863 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,2]
1864 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1865 ; SSE2-NEXT: movaps %xmm1, %xmm0
1866 ; SSE2-NEXT: retq
1867 ;
1868 ; SSE3-LABEL: mask_v4f32_4127:
1869 ; SSE3: # %bb.0:
1870 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,2]
1871 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1872 ; SSE3-NEXT: movaps %xmm1, %xmm0
1873 ; SSE3-NEXT: retq
1874 ;
1875 ; SSSE3-LABEL: mask_v4f32_4127:
1876 ; SSSE3: # %bb.0:
1877 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,2]
1878 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1879 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1880 ; SSSE3-NEXT: retq
1881 ;
1882 ; SSE41-LABEL: mask_v4f32_4127:
1883 ; SSE41: # %bb.0:
1884 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
1885 ; SSE41-NEXT: retq
1886 ;
1887 ; AVX-LABEL: mask_v4f32_4127:
1888 ; AVX: # %bb.0:
1889 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
1890 ; AVX-NEXT: retq
1891 %1 = bitcast <4 x float> %a to <4 x i32>
1892 %2 = bitcast <4 x float> %b to <4 x i32>
1893 %3 = and <4 x i32> %1, <i32 0, i32 -1, i32 -1, i32 0>
1894 %4 = and <4 x i32> %2, <i32 -1, i32 0, i32 0, i32 -1>
1895 %5 = or <4 x i32> %4, %3
1896 %6 = bitcast <4 x i32> %5 to <4 x float>
1897 ret <4 x float> %6
1898 }
1900 define <4 x float> @mask_v4f32_0127(<4 x float> %a, <4 x float> %b) {
1901 ; SSE2-LABEL: mask_v4f32_0127:
1902 ; SSE2: # %bb.0:
1903 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
1904 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
1905 ; SSE2-NEXT: movaps %xmm1, %xmm0
1906 ; SSE2-NEXT: retq
1907 ;
1908 ; SSE3-LABEL: mask_v4f32_0127:
1909 ; SSE3: # %bb.0:
1910 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
1911 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
1912 ; SSE3-NEXT: movaps %xmm1, %xmm0
1913 ; SSE3-NEXT: retq
1914 ;
1915 ; SSSE3-LABEL: mask_v4f32_0127:
1916 ; SSSE3: # %bb.0:
1917 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
1918 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
1919 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1920 ; SSSE3-NEXT: retq
1921 ;
1922 ; SSE41-LABEL: mask_v4f32_0127:
1923 ; SSE41: # %bb.0:
1924 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
1925 ; SSE41-NEXT: retq
1926 ;
1927 ; AVX-LABEL: mask_v4f32_0127:
1928 ; AVX: # %bb.0:
1929 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
1930 ; AVX-NEXT: retq
1931 %1 = bitcast <4 x float> %a to <2 x i64>
1932 %2 = bitcast <4 x float> %b to <2 x i64>
1933 %3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
1934 %4 = and <2 x i64> %2, <i64 -1, i64 4294967295>
1935 %5 = or <2 x i64> %4, %3
1936 %6 = bitcast <2 x i64> %5 to <4 x float>
1937 ret <4 x float> %6
1938 }
1940 define <4 x i32> @mask_v4i32_0127(<4 x i32> %a, <4 x i32> %b) {
1941 ; SSE2-LABEL: mask_v4i32_0127:
1942 ; SSE2: # %bb.0:
1943 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
1944 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
1945 ; SSE2-NEXT: movaps %xmm1, %xmm0
1946 ; SSE2-NEXT: retq
1947 ;
1948 ; SSE3-LABEL: mask_v4i32_0127:
1949 ; SSE3: # %bb.0:
1950 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
1951 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
1952 ; SSE3-NEXT: movaps %xmm1, %xmm0
1953 ; SSE3-NEXT: retq
1954 ;
1955 ; SSSE3-LABEL: mask_v4i32_0127:
1956 ; SSSE3: # %bb.0:
1957 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
1958 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
1959 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1960 ; SSSE3-NEXT: retq
1961 ;
1962 ; SSE41-LABEL: mask_v4i32_0127:
1963 ; SSE41: # %bb.0:
1964 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
1965 ; SSE41-NEXT: retq
1966 ;
1967 ; AVX-LABEL: mask_v4i32_0127:
1968 ; AVX: # %bb.0:
1969 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
1970 ; AVX-NEXT: retq
1971 %1 = bitcast <4 x i32> %a to <2 x i64>
1972 %2 = bitcast <4 x i32> %b to <2 x i64>
1973 %3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
1974 %4 = and <2 x i64> %2, <i64 -1, i64 4294967295>
1975 %5 = or <2 x i64> %4, %3
1976 %6 = bitcast <2 x i64> %5 to <4 x i32>
1977 ret <4 x i32> %6
1978 }
1980 define <4 x float> @broadcast_v4f32_0101_from_v2f32(ptr %x) {
1981 ; SSE2-LABEL: broadcast_v4f32_0101_from_v2f32:
1982 ; SSE2: # %bb.0:
1983 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
1984 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
1985 ; SSE2-NEXT: retq
1986 ;
1987 ; SSE3-LABEL: broadcast_v4f32_0101_from_v2f32:
1988 ; SSE3: # %bb.0:
1989 ; SSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
1990 ; SSE3-NEXT: retq
1991 ;
1992 ; SSSE3-LABEL: broadcast_v4f32_0101_from_v2f32:
1993 ; SSSE3: # %bb.0:
1994 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
1995 ; SSSE3-NEXT: retq
1996 ;
1997 ; SSE41-LABEL: broadcast_v4f32_0101_from_v2f32:
1998 ; SSE41: # %bb.0:
1999 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
2000 ; SSE41-NEXT: retq
2001 ;
2002 ; AVX-LABEL: broadcast_v4f32_0101_from_v2f32:
2003 ; AVX: # %bb.0:
2004 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
2005 ; AVX-NEXT: retq
2006 %1 = load <2 x float>, ptr %x, align 1
2007 %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
2008 ret <4 x float> %2
2009 }
2011 define <4 x i32> @extract3_insert0_v4i32_7123(<4 x i32> %a0, <4 x i32> %a1) {
2012 ; SSE2-LABEL: extract3_insert0_v4i32_7123:
2013 ; SSE2: # %bb.0:
2014 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
2015 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
2016 ; SSE2-NEXT: retq
2017 ;
2018 ; SSE3-LABEL: extract3_insert0_v4i32_7123:
2019 ; SSE3: # %bb.0:
2020 ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
2021 ; SSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
2022 ; SSE3-NEXT: retq
2023 ;
2024 ; SSSE3-LABEL: extract3_insert0_v4i32_7123:
2025 ; SSSE3: # %bb.0:
2026 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
2027 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
2028 ; SSSE3-NEXT: retq
2029 ;
2030 ; SSE41-LABEL: extract3_insert0_v4i32_7123:
2031 ; SSE41: # %bb.0:
2032 ; SSE41-NEXT: extractps $3, %xmm1, %eax
2033 ; SSE41-NEXT: pinsrd $0, %eax, %xmm0
2034 ; SSE41-NEXT: retq
2035 ;
2036 ; AVX-LABEL: extract3_insert0_v4i32_7123:
2037 ; AVX: # %bb.0:
2038 ; AVX-NEXT: vextractps $3, %xmm1, %eax
2039 ; AVX-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0
2040 ; AVX-NEXT: retq
2041 %1 = extractelement <4 x i32> %a1, i32 3
2042 %2 = insertelement <4 x i32> %a0, i32 %1, i32 0
2043 ret <4 x i32> %2
2044 }
2046 define <4 x i32> @extract3_insert3_v4i32_0127(<4 x i32> %a0, <4 x i32> %a1) {
2047 ; SSE2-LABEL: extract3_insert3_v4i32_0127:
2048 ; SSE2: # %bb.0:
2049 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]
2050 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2051 ; SSE2-NEXT: retq
2052 ;
2053 ; SSE3-LABEL: extract3_insert3_v4i32_0127:
2054 ; SSE3: # %bb.0:
2055 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]
2056 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2057 ; SSE3-NEXT: retq
2058 ;
2059 ; SSSE3-LABEL: extract3_insert3_v4i32_0127:
2060 ; SSSE3: # %bb.0:
2061 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]
2062 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2063 ; SSSE3-NEXT: retq
2064 ;
2065 ; SSE41-LABEL: extract3_insert3_v4i32_0127:
2066 ; SSE41: # %bb.0:
2067 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
2068 ; SSE41-NEXT: retq
2069 ;
2070 ; AVX-LABEL: extract3_insert3_v4i32_0127:
2071 ; AVX: # %bb.0:
2072 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
2073 ; AVX-NEXT: retq
2074 %1 = extractelement <4 x i32> %a1, i32 3
2075 %2 = insertelement <4 x i32> %a0, i32 %1, i32 3
2076 ret <4 x i32> %2
2077 }
2079 define <4 x i32> @insert_reg_and_zero_v4i32(i32 %a) {
2080 ; SSE-LABEL: insert_reg_and_zero_v4i32:
2081 ; SSE: # %bb.0:
2082 ; SSE-NEXT: movd %edi, %xmm0
2083 ; SSE-NEXT: retq
2084 ;
2085 ; AVX-LABEL: insert_reg_and_zero_v4i32:
2086 ; AVX: # %bb.0:
2087 ; AVX-NEXT: vmovd %edi, %xmm0
2088 ; AVX-NEXT: retq
2089 %v = insertelement <4 x i32> undef, i32 %a, i32 0
2090 %shuffle = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
2091 ret <4 x i32> %shuffle
2092 }
2094 define <4 x i32> @insert_mem_and_zero_v4i32(ptr %ptr) {
2095 ; SSE-LABEL: insert_mem_and_zero_v4i32:
2096 ; SSE: # %bb.0:
2097 ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
2098 ; SSE-NEXT: retq
2099 ;
2100 ; AVX-LABEL: insert_mem_and_zero_v4i32:
2101 ; AVX: # %bb.0:
2102 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
2103 ; AVX-NEXT: retq
2104 %a = load i32, ptr %ptr
2105 %v = insertelement <4 x i32> undef, i32 %a, i32 0
2106 %shuffle = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
2107 ret <4 x i32> %shuffle
2108 }
2110 define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
2111 ; SSE2-LABEL: insert_reg_and_zero_v4f32:
2112 ; SSE2: # %bb.0:
2113 ; SSE2-NEXT: xorps %xmm1, %xmm1
2114 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2115 ; SSE2-NEXT: movaps %xmm1, %xmm0
2116 ; SSE2-NEXT: retq
2117 ;
2118 ; SSE3-LABEL: insert_reg_and_zero_v4f32:
2119 ; SSE3: # %bb.0:
2120 ; SSE3-NEXT: xorps %xmm1, %xmm1
2121 ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2122 ; SSE3-NEXT: movaps %xmm1, %xmm0
2123 ; SSE3-NEXT: retq
2124 ;
2125 ; SSSE3-LABEL: insert_reg_and_zero_v4f32:
2126 ; SSSE3: # %bb.0:
2127 ; SSSE3-NEXT: xorps %xmm1, %xmm1
2128 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2129 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2130 ; SSSE3-NEXT: retq
2131 ;
2132 ; SSE41-LABEL: insert_reg_and_zero_v4f32:
2133 ; SSE41: # %bb.0:
2134 ; SSE41-NEXT: xorps %xmm1, %xmm1
2135 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2136 ; SSE41-NEXT: retq
2137 ;
2138 ; AVX-LABEL: insert_reg_and_zero_v4f32:
2139 ; AVX: # %bb.0:
2140 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
2141 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2142 ; AVX-NEXT: retq
2143 %v = insertelement <4 x float> undef, float %a, i32 0
2144 %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
2145 ret <4 x float> %shuffle
2146 }
2148 define <4 x float> @insert_mem_and_zero_v4f32(ptr %ptr) {
2149 ; SSE-LABEL: insert_mem_and_zero_v4f32:
2150 ; SSE: # %bb.0:
2151 ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
2152 ; SSE-NEXT: retq
2153 ;
2154 ; AVX-LABEL: insert_mem_and_zero_v4f32:
2155 ; AVX: # %bb.0:
2156 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
2157 ; AVX-NEXT: retq
2158 %a = load float, ptr %ptr
2159 %v = insertelement <4 x float> undef, float %a, i32 0
2160 %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
2161 ret <4 x float> %shuffle
2162 }
2164 define <4 x i32> @insert_reg_lo_v4i32(i64 %a, <4 x i32> %b) {
2165 ; SSE2-LABEL: insert_reg_lo_v4i32:
2166 ; SSE2: # %bb.0:
2167 ; SSE2-NEXT: movq %rdi, %xmm1
2168 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2169 ; SSE2-NEXT: retq
2170 ;
2171 ; SSE3-LABEL: insert_reg_lo_v4i32:
2172 ; SSE3: # %bb.0:
2173 ; SSE3-NEXT: movq %rdi, %xmm1
2174 ; SSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2175 ; SSE3-NEXT: retq
2176 ;
2177 ; SSSE3-LABEL: insert_reg_lo_v4i32:
2178 ; SSSE3: # %bb.0:
2179 ; SSSE3-NEXT: movq %rdi, %xmm1
2180 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2181 ; SSSE3-NEXT: retq
2182 ;
2183 ; SSE41-LABEL: insert_reg_lo_v4i32:
2184 ; SSE41: # %bb.0:
2185 ; SSE41-NEXT: movq %rdi, %xmm1
2186 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
2187 ; SSE41-NEXT: retq
2188 ;
2189 ; AVX1-LABEL: insert_reg_lo_v4i32:
2190 ; AVX1: # %bb.0:
2191 ; AVX1-NEXT: vmovq %rdi, %xmm1
2192 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
2193 ; AVX1-NEXT: retq
2194 ;
2195 ; AVX2OR512VL-LABEL: insert_reg_lo_v4i32:
2196 ; AVX2OR512VL: # %bb.0:
2197 ; AVX2OR512VL-NEXT: vmovq %rdi, %xmm1
2198 ; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
2199 ; AVX2OR512VL-NEXT: retq
2200 %a.cast = bitcast i64 %a to <2 x i32>
2201 %v = shufflevector <2 x i32> %a.cast, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2202 %shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
2203 ret <4 x i32> %shuffle
2204 }
2206 define <4 x i32> @insert_mem_lo_v4i32(ptr %ptr, <4 x i32> %b) {
2207 ; SSE2-LABEL: insert_mem_lo_v4i32:
2208 ; SSE2: # %bb.0:
2209 ; SSE2-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2210 ; SSE2-NEXT: retq
2211 ;
2212 ; SSE3-LABEL: insert_mem_lo_v4i32:
2213 ; SSE3: # %bb.0:
2214 ; SSE3-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2215 ; SSE3-NEXT: retq
2216 ;
2217 ; SSSE3-LABEL: insert_mem_lo_v4i32:
2218 ; SSSE3: # %bb.0:
2219 ; SSSE3-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2220 ; SSSE3-NEXT: retq
2221 ;
2222 ; SSE41-LABEL: insert_mem_lo_v4i32:
2223 ; SSE41: # %bb.0:
2224 ; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
2225 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
2226 ; SSE41-NEXT: retq
2227 ;
2228 ; AVX-LABEL: insert_mem_lo_v4i32:
2229 ; AVX: # %bb.0:
2230 ; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
2231 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
2232 ; AVX-NEXT: retq
2233 %a = load <2 x i32>, ptr %ptr
2234 %v = shufflevector <2 x i32> %a, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2235 %shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
2236 ret <4 x i32> %shuffle
2237 }
2239 define <4 x i32> @insert_reg_hi_v4i32(i64 %a, <4 x i32> %b) {
2240 ; SSE-LABEL: insert_reg_hi_v4i32:
2241 ; SSE: # %bb.0:
2242 ; SSE-NEXT: movq %rdi, %xmm1
2243 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2244 ; SSE-NEXT: retq
2245 ;
2246 ; AVX-LABEL: insert_reg_hi_v4i32:
2247 ; AVX: # %bb.0:
2248 ; AVX-NEXT: vmovq %rdi, %xmm1
2249 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2250 ; AVX-NEXT: retq
2251 %a.cast = bitcast i64 %a to <2 x i32>
2252 %v = shufflevector <2 x i32> %a.cast, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2253 %shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
2254 ret <4 x i32> %shuffle
2255 }
2257 define <4 x i32> @insert_mem_hi_v4i32(ptr %ptr, <4 x i32> %b) {
2258 ; SSE-LABEL: insert_mem_hi_v4i32:
2259 ; SSE: # %bb.0:
2260 ; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
2261 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2262 ; SSE-NEXT: retq
2263 ;
2264 ; AVX-LABEL: insert_mem_hi_v4i32:
2265 ; AVX: # %bb.0:
2266 ; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
2267 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2268 ; AVX-NEXT: retq
2269 %a = load <2 x i32>, ptr %ptr
2270 %v = shufflevector <2 x i32> %a, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2271 %shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
2272 ret <4 x i32> %shuffle
2273 }
2275 define <4 x float> @insert_reg_lo_v4f32(double %a, <4 x float> %b) {
2276 ; SSE2-LABEL: insert_reg_lo_v4f32:
2277 ; SSE2: # %bb.0:
2278 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
2279 ; SSE2-NEXT: retq
2280 ;
2281 ; SSE3-LABEL: insert_reg_lo_v4f32:
2282 ; SSE3: # %bb.0:
2283 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
2284 ; SSE3-NEXT: retq
2285 ;
2286 ; SSSE3-LABEL: insert_reg_lo_v4f32:
2287 ; SSSE3: # %bb.0:
2288 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
2289 ; SSSE3-NEXT: retq
2290 ;
2291 ; SSE41-LABEL: insert_reg_lo_v4f32:
2292 ; SSE41: # %bb.0:
2293 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
2294 ; SSE41-NEXT: retq
2295 ;
2296 ; AVX-LABEL: insert_reg_lo_v4f32:
2297 ; AVX: # %bb.0:
2298 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
2299 ; AVX-NEXT: retq
2300 %a.cast = bitcast double %a to <2 x float>
2301 %v = shufflevector <2 x float> %a.cast, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2302 %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
2303 ret <4 x float> %shuffle
2304 }
2306 define <4 x float> @insert_mem_lo_v4f32(ptr %ptr, <4 x float> %b) {
2307 ; SSE-LABEL: insert_mem_lo_v4f32:
2308 ; SSE: # %bb.0:
2309 ; SSE-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2310 ; SSE-NEXT: retq
2311 ;
2312 ; AVX-LABEL: insert_mem_lo_v4f32:
2313 ; AVX: # %bb.0:
2314 ; AVX-NEXT: vmovlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2315 ; AVX-NEXT: retq
2316 %a = load <2 x float>, ptr %ptr
2317 %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2318 %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
2319 ret <4 x float> %shuffle
2320 }
2322 define <4 x float> @insert_reg_hi_v4f32(double %a, <4 x float> %b) {
2323 ; SSE-LABEL: insert_reg_hi_v4f32:
2324 ; SSE: # %bb.0:
2325 ; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
2326 ; SSE-NEXT: movaps %xmm1, %xmm0
2327 ; SSE-NEXT: retq
2328 ;
2329 ; AVX-LABEL: insert_reg_hi_v4f32:
2330 ; AVX: # %bb.0:
2331 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
2332 ; AVX-NEXT: retq
2333 %a.cast = bitcast double %a to <2 x float>
2334 %v = shufflevector <2 x float> %a.cast, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2335 %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
2336 ret <4 x float> %shuffle
2337 }
2339 define <4 x float> @insert_mem_hi_v4f32(ptr %ptr, <4 x float> %b) {
2340 ; SSE-LABEL: insert_mem_hi_v4f32:
2341 ; SSE: # %bb.0:
2342 ; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
2343 ; SSE-NEXT: retq
2344 ;
2345 ; AVX-LABEL: insert_mem_hi_v4f32:
2346 ; AVX: # %bb.0:
2347 ; AVX-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
2348 ; AVX-NEXT: retq
2349 %a = load <2 x float>, ptr %ptr
2350 %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
2351 %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
2352 ret <4 x float> %shuffle
2353 }
2355 ; PR21137
2356 define <4 x float> @shuffle_mem_v4f32_3210(ptr %ptr) {
2357 ; SSE-LABEL: shuffle_mem_v4f32_3210:
2358 ; SSE: # %bb.0:
2359 ; SSE-NEXT: movaps (%rdi), %xmm0
2360 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2361 ; SSE-NEXT: retq
2362 ;
2363 ; AVX-LABEL: shuffle_mem_v4f32_3210:
2364 ; AVX: # %bb.0:
2365 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = mem[3,2,1,0]
2366 ; AVX-NEXT: retq
2367 %a = load <4 x float>, ptr %ptr
2368 %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
2369 ret <4 x float> %shuffle
2370 }
2372 define <4 x i32> @insert_dup_mem_v4i32(ptr %ptr) {
2373 ; SSE-LABEL: insert_dup_mem_v4i32:
2374 ; SSE: # %bb.0:
2375 ; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2376 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
2377 ; SSE-NEXT: retq
2378 ;
2379 ; AVX-LABEL: insert_dup_mem_v4i32:
2380 ; AVX: # %bb.0:
2381 ; AVX-NEXT: vbroadcastss (%rdi), %xmm0
2382 ; AVX-NEXT: retq
2383 %tmp = load i32, ptr %ptr, align 4
2384 %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
2385 %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
2386 ret <4 x i32> %tmp2
2387 }
2389 ; PR41249
2390 define <4 x float> @shuffle_mem_pmovzx_v4f32(ptr %p0, ptr %p1) {
2391 ; SSE-LABEL: shuffle_mem_pmovzx_v4f32:
2392 ; SSE: # %bb.0:
2393 ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
2394 ; SSE-NEXT: xorps %xmm1, %xmm1
2395 ; SSE-NEXT: movaps %xmm0, %xmm2
2396 ; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
2397 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
2398 ; SSE-NEXT: movaps %xmm2, (%rsi)
2399 ; SSE-NEXT: retq
2400 ;
2401 ; AVX1-LABEL: shuffle_mem_pmovzx_v4f32:
2402 ; AVX1: # %bb.0:
2403 ; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
2404 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
2405 ; AVX1-NEXT: vunpckhps {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
2406 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
2407 ; AVX1-NEXT: vmovaps %xmm1, (%rsi)
2408 ; AVX1-NEXT: retq
2409 ;
2410 ; AVX2OR512VL-LABEL: shuffle_mem_pmovzx_v4f32:
2411 ; AVX2OR512VL: # %bb.0:
2412 ; AVX2OR512VL-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
2413 ; AVX2OR512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
2414 ; AVX2OR512VL-NEXT: vunpckhps {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
2415 ; AVX2OR512VL-NEXT: vbroadcastss %xmm0, %xmm0
2416 ; AVX2OR512VL-NEXT: vmovaps %xmm1, (%rsi)
2417 ; AVX2OR512VL-NEXT: retq
2418 %1 = load <2 x float>, ptr %p0
2419 %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
2420 %3 = shufflevector <4 x float> %2, <4 x float> <float undef, float undef, float 0.000000e+00, float 0.000000e+00>, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
2421 %4 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> zeroinitializer
2422 store <4 x float> %3, ptr %p1
2423 ret <4 x float> %4
2424 }
2426 ;
2427 ; Shuffle to logical bit shifts
2428 ;
2430 define <4 x i32> @shuffle_v4i32_z0zX(<4 x i32> %a) {
2431 ; SSE-LABEL: shuffle_v4i32_z0zX:
2432 ; SSE: # %bb.0:
2433 ; SSE-NEXT: psllq $32, %xmm0
2434 ; SSE-NEXT: retq
2435 ;
2436 ; AVX-LABEL: shuffle_v4i32_z0zX:
2437 ; AVX: # %bb.0:
2438 ; AVX-NEXT: vpsllq $32, %xmm0, %xmm0
2439 ; AVX-NEXT: retq
2440 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 undef>
2441 ret <4 x i32> %shuffle
2442 }
2444 define <4 x i32> @shuffle_v4i32_1z3z(<4 x i32> %a) {
2445 ; SSE-LABEL: shuffle_v4i32_1z3z:
2446 ; SSE: # %bb.0:
2447 ; SSE-NEXT: psrlq $32, %xmm0
2448 ; SSE-NEXT: retq
2449 ;
2450 ; AVX-LABEL: shuffle_v4i32_1z3z:
2451 ; AVX: # %bb.0:
2452 ; AVX-NEXT: vpsrlq $32, %xmm0, %xmm0
2453 ; AVX-NEXT: retq
2454 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
2455 ret <4 x i32> %shuffle
2456 }
2458 define <4 x float> @shuffle_mem_v4f32_0145(<4 x float> %a, ptr %pb) {
2459 ; SSE-LABEL: shuffle_mem_v4f32_0145:
2460 ; SSE: # %bb.0:
2461 ; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
2462 ; SSE-NEXT: retq
2463 ;
2464 ; AVX-LABEL: shuffle_mem_v4f32_0145:
2465 ; AVX: # %bb.0:
2466 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],mem[0]
2467 ; AVX-NEXT: retq
2468 %b = load <4 x float>, ptr %pb, align 1
2469 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
2470 ret <4 x float> %shuffle
2471 }
2473 define <4 x float> @shuffle_mem_v4f32_4523(<4 x float> %a, ptr %pb) {
2474 ; SSE2-LABEL: shuffle_mem_v4f32_4523:
2475 ; SSE2: # %bb.0:
2476 ; SSE2-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2477 ; SSE2-NEXT: retq
2478 ;
2479 ; SSE3-LABEL: shuffle_mem_v4f32_4523:
2480 ; SSE3: # %bb.0:
2481 ; SSE3-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2482 ; SSE3-NEXT: retq
2483 ;
2484 ; SSSE3-LABEL: shuffle_mem_v4f32_4523:
2485 ; SSSE3: # %bb.0:
2486 ; SSSE3-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2487 ; SSSE3-NEXT: retq
2488 ;
2489 ; SSE41-LABEL: shuffle_mem_v4f32_4523:
2490 ; SSE41: # %bb.0:
2491 ; SSE41-NEXT: movups (%rdi), %xmm1
2492 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
2493 ; SSE41-NEXT: retq
2494 ;
2495 ; AVX-LABEL: shuffle_mem_v4f32_4523:
2496 ; AVX: # %bb.0:
2497 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
2498 ; AVX-NEXT: retq
2499 %b = load <4 x float>, ptr %pb, align 1
2500 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
2501 ret <4 x float> %shuffle
2502 }
2504 define <4 x float> @shuffle_mem_v4f32_0624(<4 x float> %a0, ptr %a1) {
2505 ; SSE-LABEL: shuffle_mem_v4f32_0624:
2506 ; SSE: # %bb.0:
2507 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],mem[0,2]
2508 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0,3,1]
2509 ; SSE-NEXT: retq
2510 ;
2511 ; AVX1OR2-LABEL: shuffle_mem_v4f32_0624:
2512 ; AVX1OR2: # %bb.0:
2513 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],mem[0,2]
2514 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0,3,1]
2515 ; AVX1OR2-NEXT: retq
2516 ;
2517 ; AVX512VL-LABEL: shuffle_mem_v4f32_0624:
2518 ; AVX512VL: # %bb.0:
2519 ; AVX512VL-NEXT: vmovaps (%rdi), %xmm2
2520 ; AVX512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,6,2,4]
2521 ; AVX512VL-NEXT: vpermi2ps %xmm0, %xmm2, %xmm1
2522 ; AVX512VL-NEXT: vmovaps %xmm1, %xmm0
2523 ; AVX512VL-NEXT: retq
2524 %1 = load <4 x float>, ptr %a1
2525 %2 = shufflevector <4 x float> %1, <4 x float> %a0, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
2526 ret <4 x float> %2
2527 }
2529 define <4 x float> @shuffle_mem_v4f32_4760(<4 x float> %a0, ptr %a1) {
2530 ; SSE-LABEL: shuffle_mem_v4f32_4760:
2531 ; SSE: # %bb.0:
2532 ; SSE-NEXT: movaps %xmm0, %xmm1
2533 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[0,0]
2534 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,2]
2535 ; SSE-NEXT: retq
2536 ;
2537 ; AVX1OR2-LABEL: shuffle_mem_v4f32_4760:
2538 ; AVX1OR2: # %bb.0:
2539 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,0],mem[0,0]
2540 ; AVX1OR2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,2]
2541 ; AVX1OR2-NEXT: retq
2542 ;
2543 ; AVX512VL-LABEL: shuffle_mem_v4f32_4760:
2544 ; AVX512VL: # %bb.0:
2545 ; AVX512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,3,2,4]
2546 ; AVX512VL-NEXT: vpermt2ps (%rdi), %xmm1, %xmm0
2547 ; AVX512VL-NEXT: retq
2548 %1 = load <4 x float>, ptr %a1
2549 %2 = shufflevector <4 x float> %1, <4 x float> %a0, <4 x i32> <i32 4, i32 7, i32 6, i32 0>
2550 ret <4 x float> %2
2551 }