llvm/test/TableGen/DefaultOpsGlobalISel.td

   1 // RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
   2
   3 include "llvm/Target/Target.td"
   4 include "GlobalISelEmitterCommon.td"
   5
   6
   7 def SelectClamp  : ComplexPattern<untyped, 2, "SelectClamp">;
   8 def SelectOMod  : ComplexPattern<untyped, 2, "SelectOMod">;
   9 def SelectClampOMod  : ComplexPattern<untyped, 3, "SelectClampOMod">;
  10 def SelectSrcMods  : ComplexPattern<untyped, 2, "SelectSrcMods">;
  11
  12 def gi_SelectClamp :
  13     GIComplexOperandMatcher<s32, "selectClamp">,
  14     GIComplexPatternEquiv<SelectClamp>;
  15
  16 def gi_SelectOMod :
  17     GIComplexOperandMatcher<s32, "selectOMod">,
  18     GIComplexPatternEquiv<SelectOMod>;
  19
  20 def gi_SelectClampOMod :
  21     GIComplexOperandMatcher<s32, "selectClampOMod">,
  22     GIComplexPatternEquiv<SelectClampOMod>;
  23
  24 def gi_SelectSrcMods :
  25     GIComplexOperandMatcher<s32, "selectSrcMods">,
  26     GIComplexPatternEquiv<SelectSrcMods>;
  27
  28
  29 def src_mods : Operand <i32>;
  30 def omod : OperandWithDefaultOps <i32, (ops (i32 0))>;
  31 def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
  32
  33
  34 // CHECK:      const uint8_t *MyTargetInstructionSelector::getMatchTable() const {
  35 // CHECK-NEXT:   constexpr static uint8_t MatchTable0[] = {
  36 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(69), // Rule ID 3 //
  37 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
  38 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
  39 // CHECK-NEXT:       // MIs[0] DstI[dst]
  40 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  41 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
  42 // CHECK-NEXT:       // MIs[0] SelectSrcMods:src0:mods0
  43 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  44 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods),
  45 // CHECK-NEXT:       // MIs[0] SelectSrcMods:src1:mods1
  46 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
  47 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_SelectSrcMods),
  48 // CHECK-NEXT:       // (fmaxnum:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods0), (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src1, src_mods:{ *:[i32] }:$mods1))  =>  (FMAX:{ *:[f32] } src_mods:{ *:[i32] }:$mods0, f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods1, f32:{ *:[f32] }:$src1)
  49 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX),
  50 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
  51 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods0
  52 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
  53 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // mods1
  54 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
  55 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
  56 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
  57 // CHECK-NEXT:       // GIR_Coverage, 3,
  58 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
  59 // CHECK-NEXT:     // Label 0: @69
  60 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(120), // Rule ID 2 //
  61 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
  62 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FFLOOR),
  63 // CHECK-NEXT:       // MIs[0] DstI[dst]
  64 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  65 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
  66 // CHECK-NEXT:       // MIs[0] SelectClampOMod:src0:omod:clamp
  67 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  68 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClampOMod),
  69 // CHECK-NEXT:       // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp))  =>  (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod)
  70 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLOMP),
  71 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
  72 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
  73 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
  74 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod
  75 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
  76 // CHECK-NEXT:       // GIR_Coverage, 2,
  77 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
  78 // CHECK-NEXT:     // Label 1: @120
  79 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(179), // Rule ID 8 //
  80 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
  81 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
  82 // CHECK-NEXT:       // MIs[0] DstI[dst]
  83 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  84 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
  85 // CHECK-NEXT:       // MIs[0] SelectSrcMods:src:mods
  86 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  87 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods),
  88 // CHECK-NEXT:       // (fcanonicalize:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$mods))  =>  (FMAX:{ *:[f32] } ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, 0:{ *:[i1] })
  89 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX),
  90 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
  91 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
  92 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
  93 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
  94 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
  95 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
  96 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
  97 // CHECK-NEXT:       // GIR_Coverage, 8,
  98 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
  99 // CHECK-NEXT:     // Label 2: @179
 100 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(228), // Rule ID 5 //
 101 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 102 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCOS),
 103 // CHECK-NEXT:       // MIs[0] DstI[dst]
 104 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
 105 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
 106 // CHECK-NEXT:       // MIs[0] SelectOMod:src0:omod
 107 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
 108 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectOMod),
 109 // CHECK-NEXT:       // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod))  =>  (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod)
 110 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP),
 111 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
 112 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
 113 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod
 114 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
 115 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
 116 // CHECK-NEXT:       // GIR_Coverage, 5,
 117 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
 118 // CHECK-NEXT:     // Label 3: @228
 119 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(299), // Rule ID 7 //
 120 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 121 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FEXP2),
 122 // CHECK-NEXT:       // MIs[0] DstI[dst]
 123 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
 124 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
 125 // CHECK-NEXT:       // MIs[0] SelectClamp:src0:clamp
 126 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
 127 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp),
 128 // CHECK-NEXT:       // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp))  =>  (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp)
 129 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
 130 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::FFOO),
 131 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
 132 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
 133 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
 134 // CHECK-NEXT:       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 135 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FEEPLE),
 136 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
 137 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
 138 // CHECK-NEXT:       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
 139 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
 140 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
 141 // CHECK-NEXT:       // GIR_Coverage, 7,
 142 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
 143 // CHECK-NEXT:     // Label 4: @299
 144 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(345), // Rule ID 0 //
 145 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 146 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSIN),
 147 // CHECK-NEXT:       // MIs[0] DstI[dst]
 148 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
 149 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
 150 // CHECK-NEXT:       // MIs[0] SelectClamp:src0:clamp
 151 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
 152 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp),
 153 // CHECK-NEXT:       // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp))  =>  (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)
 154 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO),
 155 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
 156 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
 157 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
 158 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
 159 // CHECK-NEXT:       // GIR_Coverage, 0,
 160 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
 161 // CHECK-NEXT:     // Label 5: @345
 162 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(394), // Rule ID 6 //
 163 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 164 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSQRT),
 165 // CHECK-NEXT:       // MIs[0] DstI[dst]
 166 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
 167 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
 168 // CHECK-NEXT:       // MIs[0] SelectClamp:src0:clamp
 169 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
 170 // CHECK-NEXT:       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp),
 171 // CHECK-NEXT:       // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp))  =>  (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp)
 172 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP),
 173 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
 174 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
 175 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/0, /*Imm*/93,
 176 // CHECK-NEXT:       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
 177 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
 178 // CHECK-NEXT:       // GIR_Coverage, 6,
 179 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
 180 // CHECK-NEXT:     // Label 6: @394
 181 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(428), // Rule ID 1 //
 182 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 183 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
 184 // CHECK-NEXT:       // MIs[0] DstI[dst]
 185 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
 186 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
 187 // CHECK-NEXT:       // MIs[0] src0
 188 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
 189 // CHECK-NEXT:       // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0)  =>  (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0)
 190 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FBAR),
 191 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
 192 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/1, // src0
 193 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
 194 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
 195 // CHECK-NEXT:       // GIR_Coverage, 1,
 196 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
 197 // CHECK-NEXT:     // Label 7: @428
 198 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(462), // Rule ID 4 //
 199 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 200 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
 201 // CHECK-NEXT:       // MIs[0] DstI[dst]
 202 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
 203 // CHECK-NEXT:       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
 204 // CHECK-NEXT:       // MIs[0] src0
 205 // CHECK-NEXT:       GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
 206 // CHECK-NEXT:       // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0)  =>  (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0)
 207 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO),
 208 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
 209 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/1, // src0
 210 // CHECK-NEXT:       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
 211 // CHECK-NEXT:       GIR_RootConstrainSelectedInstOperands,
 212 // CHECK-NEXT:       // GIR_Coverage, 4,
 213 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
 214 // CHECK-NEXT:     // Label 8: @462
 215 // CHECK-NEXT:     GIM_Reject,
 216 // CHECK-NEXT:     }; // Size: 463 bytes
 217 // CHECK-NEXT:   return MatchTable0;
 218 // CHECK-NEXT: }
 219
 220 // Have default operand with explicit value from complex pattern.
 221 def FFOO : I<(outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp),
 222             [(set FPR32:$dst, (fsin (SelectClamp f32:$src0, i1:$clamp)))]>;
 223
 224
 225 // Have default operand, not explicitly specified in a standalone
 226 // pattern.
 227 def : Pat <
 228   (ftrunc f32:$src0),
 229   (FFOO FPR32:$src0)
 230 >;
 231
 232 // Have default operand, not explicitly specified in an instruction
 233 // definition pattern.
 234 def FBAR : I<(outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp),
 235             [(set FPR32:$dst, (fround f32:$src0))]>;
 236
 237
 238 // // Swapped order in instruction from pattern
 239 def FLOMP : I<
 240   (outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp, omod:$omod),
 241   [(set FPR32:$dst, (ffloor (SelectClampOMod f32:$src0, omod:$omod, i1:$clamp)))]>;
 242
 243 def FLAMP : I<(outs FPR32:$dst), (ins FPR32:$src0, omod:$omod, clamp:$clamp), []>;
 244
 245 // // Have 2 default operands, and the first is specified
 246 def : Pat <
 247   (fcos (SelectOMod f32:$src0, i32:$omod)),
 248   (FLAMP FPR32:$src0, omod:$omod)
 249 >;
 250
 251 // Immediate used for first defaulted operand
 252 def : Pat <
 253   (fsqrt (SelectClamp f32:$src0, i1:$clamp)),
 254   (FLAMP FPR32:$src0, 93, clamp:$clamp)
 255 >;
 256
 257 def FEEPLE : I<(outs FPR32:$dst),
 258                (ins FPR32:$src0, FPR32:$src1, clamp:$clamp), []>;
 259
 260 // Default operand isn't on the root ouput instruction
 261 def : Pat <
 262   (fexp2 (SelectClamp f32:$src0, i1:$clamp)),
 263   (FEEPLE FPR32:$src0, (FFOO FPR32:$src0), clamp:$clamp)
 264 >;
 265
 266 // Same instruction is used in two different pattern contexts, one
 267 // uses the default and one does not.
 268 def FMAX : I<(outs FPR32:$dst),
 269   (ins src_mods:$mods0, FPR32:$src0, src_mods:$mods1, FPR32:$src1, clamp:$clamp),
 270   [(set FPR32:$dst, (f32 (fmaxnum (SelectSrcMods f32:$src0, src_mods:$mods0),
 271                                   (SelectSrcMods f32:$src1, src_mods:$mods1))))]
 272 >;
 273
 274 def : Pat<
 275   (fcanonicalize (f32 (SelectSrcMods f32:$src, i32:$mods))),
 276   (FMAX $mods, $src, $mods, $src, 0)
 277 >;