llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td

   1 // RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
   2 // RUN:     -combiners=MyCombiner %s | FileCheck %s
   3
   4 // Checks that temporary registers defined in apply patterns
   5 // are emitted with RegState::Define.
   6
   7 include "llvm/Target/Target.td"
   8 include "llvm/Target/GlobalISel/Combine.td"
   9
  10 def MyTargetISA : InstrInfo;
  11 def MyTarget : Target { let InstructionSet = MyTargetISA; }
  12
  13 def Test0 : GICombineRule<
  14   (defs root:$dst),
  15   (match (G_ADD $dst, $lhs, $rhs)),
  16   (apply (G_UDIVREM $tmp, $dst, $lhs, $rhs))
  17 >;
  18
  19 def Test1 : GICombineRule<
  20   (defs root:$dst),
  21   (match (G_ADD $dst, $lhs, $rhs)),
  22   (apply (G_UDIVREM $dst, $tmp, $lhs, $rhs))
  23 >;
  24
  25 def Test2 : GICombineRule<
  26   (defs root:$dst),
  27   (match (G_ADD $dst, $lhs, $rhs)),
  28   (apply (G_ADD $tmp, 0, $lhs),
  29          (G_ADD $dst, $tmp, $rhs))
  30 >;
  31
  32 def MyCombiner: GICombiner<"GenMyCombiner", [
  33   Test0,
  34   Test1,
  35   Test2,
  36 ]>;
  37
  38 // CHECK:       // Combiner Rule #0: Test0
  39 // CHECK-NEXT:  GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM),
  40 // CHECK-NEXT:  GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
  41 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/0, // dst
  42 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/1, // lhs
  43 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/2, // rhs
  44
  45 // CHECK:       // Combiner Rule #1: Test1
  46 // CHECK-NEXT:  GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM),
  47 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/0, // dst
  48 // CHECK-NEXT:  GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
  49 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/1, // lhs
  50 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/2, // rhs
  51
  52 // CHECK:       // Combiner Rule #2: Test2
  53 // CHECK-NEXT:  GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
  54 // CHECK-NEXT:  GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
  55 // CHECK-NEXT:  GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
  56 // CHECK-NEXT:  GIR_RootToRootCopy, /*OpIdx*/1, // lhs