llvm/test/TableGen/GlobalISelEmitterVariadic.td

   1 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
   2
   3 include "llvm/Target/Target.td"
   4 include "GlobalISelEmitterCommon.td"
   5
   6 def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
   7
   8 def ONE : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
   9 def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
  10
  11 // G_BUILD_VECTOR is guaranteed to have at least one operand, therefore performing a
  12 // number of operands check is not needed to avoid per-operand checks accessing the
  13 // MI's operand list out of bounds in this particular pattern. However, we still
  14 // must perform the check, as a G_BUILD_VECTOR instance with two source operands
  15 // will pass all checks done by this pattern otherwise, which will lead to a
  16 // mis-match if this pattern tried first (and it will if it has higher complexity).
  17 def : Pat<(build_vector GPR32:$src1),
  18           (ONE GPR32:$src1)> {
  19   let AddedComplexity = 1000;
  20 }
  21
  22 def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
  23           (TWO GPR32:$src1, GPR32:$src2)>;
  24
  25 // CHECK:       GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4([[NEXT_OPCODE_LABEL:[0-9]+]]),
  26 // CHECK-NEXT:    GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
  27 // CHECK-NEXT:    GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 //
  28 // CHECK-NEXT:      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
  29 // CHECK-NEXT:      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  30 // CHECK-NEXT:      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  31 // CHECK-NEXT:      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  32 // CHECK-NEXT:      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  33 // CHECK-NEXT:      // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1)  =>  (ONE:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
  34 // CHECK-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ONE),
  35 // CHECK-NEXT:      GIR_RootConstrainSelectedInstOperands,
  36 // CHECK-NEXT:      // GIR_Coverage, 0,
  37 // CHECK-NEXT:      GIR_Done,
  38 // CHECK-NEXT:    // Label 1: @[[NEXT_NUM_OPERANDS_LABEL_1]]
  39 // CHECK-NEXT:    GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_2:[0-9]+]]), // Rule ID 1 //
  40 // CHECK-NEXT:      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
  41 // CHECK-NEXT:      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  42 // CHECK-NEXT:      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  43 // CHECK-NEXT:      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
  44 // CHECK-NEXT:      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  45 // CHECK-NEXT:      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  46 // CHECK-NEXT:      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  47 // CHECK-NEXT:      // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)  =>  (TWO:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
  48 // CHECK-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO),
  49 // CHECK-NEXT:      GIR_RootConstrainSelectedInstOperands,
  50 // CHECK-NEXT:      // GIR_Coverage, 1,
  51 // CHECK-NEXT:      GIR_Done,
  52 // CHECK-NEXT:    // Label 2: @[[NEXT_NUM_OPERANDS_LABEL_2]]
  53 // CHECK-NEXT:    GIM_Reject,
  54 // CHECK-NEXT:  // Label 0: @[[NEXT_OPCODE_LABEL]]
  55 // CHECK-NEXT:  GIM_Reject,