Bump version to 19.1.0-rc3
[llvm-project.git] / llvm / test / TableGen / dag-isel-subregs.td
blob52ac0377bd2c9f24c1f7d7cfcdcbb5b4584dcbb2
1 // RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
3 include "reg-with-subregs-common.td"
5 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
6 // CHECK: OPC_CheckChild1Integer, 0,
7 // CHECK: OPC_EmitStringInteger32, sub0_sub1,
8 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
9           (EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
11 // CHECK: OPC_CheckChild1Integer, 30,
12 // CHECK: OPC_EmitInteger32, 10|128,2/*266*/,
13 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
14           (EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;