llvm/test/TableGen/riscv-target-def.td

   1 // RUN: llvm-tblgen -gen-riscv-target-def -I %p/../../include %s | FileCheck %s
   2
   3 include "llvm/Target/Target.td"
   4
   5 class RISCVExtension<string name, int major, int minor, string desc,
   6                      list<SubtargetFeature> implies = [],
   7                      string fieldname = !subst("Feature", "Has", NAME),
   8                      string value = "true">
   9     : SubtargetFeature<name, fieldname, value, desc, implies> {
  10   int MajorVersion = major;
  11   int MinorVersion = minor;
  12   bit Experimental = false;
  13 }
  14
  15 class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
  16   int GroupID = groupID;
  17   int BitPos = bitPos;
  18 }
  19
  20 class RISCVExperimentalExtension<string name, int major, int minor, string desc,
  21                                  list<RISCVExtension> implies = [],
  22                                  string fieldname = !subst("Feature", "Has", NAME),
  23                                  string value = "true">
  24     : RISCVExtension<"experimental-"#name, major, minor, desc, implies,
  25                      fieldname, value> {
  26   let Experimental = true;
  27 }
  28
  29 def FeatureStdExtI
  30     : RISCVExtension<"i", 2, 1,
  31                      "'I' (Base Integer Instruction Set)">,
  32       RISCVExtensionBitmask<0, 8>;
  33
  34 def FeatureStdExtZicsr
  35     : RISCVExtension<"zicsr", 2, 0,
  36                      "'zicsr' (CSRs)">;
  37
  38 def FeatureStdExtZifencei
  39     : RISCVExtension<"zifencei", 2, 0,
  40                      "'Zifencei' (fence.i)">;
  41
  42 def FeatureStdExtF
  43     : RISCVExtension<"f", 2, 2,
  44                      "'F' (Single-Precision Floating-Point)",
  45                      [FeatureStdExtZicsr]>,
  46       RISCVExtensionBitmask<0, 5>;
  47
  48 def FeatureStdExtZidummy
  49     : RISCVExperimentalExtension<"zidummy", 0, 1,
  50                                  "Dummy">;
  51
  52 def Feature32Bit
  53     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
  54 def Feature64Bit
  55     : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
  56
  57 // Dummy feature that isn't an extension.
  58 def FeatureDummy
  59     : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
  60
  61 class RISCVProfile<string name, list<SubtargetFeature> features>
  62     : SubtargetFeature<name, "Is" # NAME, "true",
  63                        "RISC-V " # name # " profile", features> {
  64   bit Experimental = false;
  65 }
  66 class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
  67     : RISCVProfile<"experimental-"#name, features> {
  68   let Experimental = true;
  69 }
  70
  71 def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
  72 def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>;
  73 def ProfileDummy : RISCVProfile<"dummy", [Feature64Bit, FeatureStdExtI,
  74                                           FeatureStdExtF, FeatureStdExtZidummy]>;
  75 def RVI99U64 : RISCVExperimentalProfile<"rvi99u64", [Feature64Bit, FeatureStdExtI]>;
  76
  77 class RISCVProcessorModel<string n,
  78                           SchedMachineModel m,
  79                           list<SubtargetFeature> f,
  80                           list<SubtargetFeature> tunef = [],
  81                           string default_march = "">
  82     :  ProcessorModel<n, m, f, tunef> {
  83   string DefaultMarch = default_march;
  84 }
  85
  86 class RISCVTuneProcessorModel<string n,
  87                               SchedMachineModel m,
  88                               list<SubtargetFeature> tunef = [],
  89                               list<SubtargetFeature> f = []>
  90     : ProcessorModel<n, m, f,tunef>;
  91
  92 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
  93                                        NoSchedModel,
  94                                        [Feature32Bit,
  95                                         FeatureStdExtI]>;
  96 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
  97                                        NoSchedModel,
  98                                        [Feature64Bit,
  99                                         FeatureStdExtI]>;
 100 def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>;
 101
 102
 103 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
 104                                       NoSchedModel,
 105                                       [Feature32Bit,
 106                                        FeatureStdExtI,
 107                                        FeatureStdExtZifencei,
 108                                        FeatureStdExtZicsr,
 109                                        FeatureStdExtZidummy,
 110                                        FeatureDummy]>;
 111 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
 112                                       NoSchedModel,
 113                                       [Feature64Bit,
 114                                        FeatureStdExtI,
 115                                        FeatureStdExtZifencei,
 116                                        FeatureStdExtZicsr,
 117                                        FeatureStdExtZidummy,
 118                                        FeatureDummy]>;
 119 def ROCKET : RISCVTuneProcessorModel<"rocket",
 120                                      NoSchedModel>;
 121
 122 // CHECK:      #ifdef GET_SUPPORTED_EXTENSIONS
 123 // CHECK-NEXT: #undef GET_SUPPORTED_EXTENSIONS
 124
 125 // CHECK:      static const RISCVSupportedExtension SupportedExtensions[] = {
 126 // CHECK-NEXT:     {"f", {2, 2}},
 127 // CHECK-NEXT:     {"i", {2, 1}},
 128 // CHECK-NEXT:     {"zicsr", {2, 0}},
 129 // CHECK-NEXT:     {"zifencei", {2, 0}},
 130 // CHECK-NEXT: };
 131
 132 // CHECK:      static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
 133 // CHECK-NEXT:     {"zidummy", {0, 1}},
 134 // CHECK-NEXT: };
 135
 136 // CHECK:      #endif // GET_SUPPORTED_EXTENSIONS
 137
 138 // CHECK:      #ifdef GET_IMPLIED_EXTENSIONS
 139 // CHECK-NEXT: #undef GET_IMPLIED_EXTENSIONS
 140
 141 // CHECK:      static constexpr ImpliedExtsEntry ImpliedExts[] = {
 142 // CHECK-NEXT:       { {"f"}, "zicsr"},
 143 // CHECK-NEXT: };
 144
 145 // CHECK:      #endif // GET_IMPLIED_EXTENSIONS
 146
 147 // CHECK:      #ifdef GET_SUPPORTED_PROFILES
 148 // CHECK-NEXT: #undef GET_SUPPORTED_PROFILES
 149
 150 // CHECK:      static constexpr RISCVProfile SupportedProfiles[] = {
 151 // CHECK-NEXT:     {"dummy","rv64i2p1_f2p2_zidummy0p1"},
 152 // CHECK-NEXT:     {"rvi20u32","rv32i2p1"},
 153 // CHECK-NEXT:     {"rvi20u64","rv64i2p1"},
 154 // CHECK-NEXT: };
 155
 156 // CHECK:      static constexpr RISCVProfile SupportedExperimentalProfiles[] = {
 157 // CHECK-NEXT:     {"rvi99u64","rv64i2p1"},
 158 // CHECK-NEXT: };
 159
 160 // CHECK:      #endif // GET_SUPPORTED_PROFILES
 161
 162 // CHECK:      #ifndef PROC
 163 // CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
 164 // CHECK-NEXT: #endif
 165
 166 // CHECK:      PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
 167 // CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
 168 // CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
 169 // CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
 170
 171 // CHECK: #undef PROC
 172
 173 // CHECK:      #ifndef TUNE_PROC
 174 // CHECK-NEXT: #define TUNE_PROC(ENUM, NAME)
 175 // CHECK-NEXT: #endif
 176
 177 // CHECK: TUNE_PROC(GENERIC, "generic")
 178 // CHECK-NEXT: TUNE_PROC(ROCKET, "rocket")
 179
 180 // CHECK: #undef TUNE_PROC
 181
 182 // CHECK: #ifdef GET_RISCVExtensionBitmaskTable_IMPL
 183 // CHECK-NEXT: static const RISCVExtensionBitmask ExtensionBitmask[]={
 184 // CHECK-NEXT:     {"f", 0, 5ULL},
 185 // CHECK-NEXT:     {"i", 0, 8ULL},
 186 // CHECK-NEXT: };
 187 // CHECK-NEXT: #endif