1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2 ; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s
4 ; This test used to crash due to missing Or/Not cases in inferScalarTypeForRecipe.
5 define void @vplan_incomplete_cases_tc2(i8 %x, i8 %y) {
6 ; CHECK-LABEL: define void @vplan_incomplete_cases_tc2(
7 ; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
8 ; CHECK-NEXT: [[ENTRY:.*]]:
9 ; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
10 ; CHECK: [[LOOP_HEADER]]:
11 ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 0, %[[ENTRY]] ]
12 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[Y]]
13 ; CHECK-NEXT: [[EXTRACT_T:%.*]] = trunc i8 [[AND]] to i1
14 ; CHECK-NEXT: br i1 [[EXTRACT_T]], label %[[LATCH]], label %[[INDIRECT_LATCH:.*]]
15 ; CHECK: [[INDIRECT_LATCH]]:
16 ; CHECK-NEXT: br label %[[LATCH]]
18 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
19 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[IV]] to i32
20 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ZEXT]], 1
21 ; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]
23 ; CHECK-NEXT: ret void
28 loop.header: ; preds = %latch, %entry
29 %iv = phi i8 [ %iv.next, %latch ], [ 0, %entry ]
31 %extract.t = trunc i8 %and to i1
32 br i1 %extract.t, label %latch, label %indirect.latch
34 indirect.latch: ; preds = %loop.header
37 latch: ; preds = %indirect.latch, loop.header
38 %iv.next = add i8 %iv, 1
39 %zext = zext i8 %iv to i32
40 %cmp = icmp ult i32 %zext, 1
41 br i1 %cmp, label %loop.header, label %exit
43 exit: ; preds = %latch
47 ; This test used to crash due to missing the LogicalAnd case in inferScalarTypeForRecipe.
48 define void @vplan_incomplete_cases_tc3(i8 %x, i8 %y) {
49 ; CHECK-LABEL: define void @vplan_incomplete_cases_tc3(
50 ; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
51 ; CHECK-NEXT: [[ENTRY:.*]]:
52 ; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
53 ; CHECK: [[LOOP_HEADER]]:
54 ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 0, %[[ENTRY]] ]
55 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[Y]]
56 ; CHECK-NEXT: [[EXTRACT_T:%.*]] = trunc i8 [[AND]] to i1
57 ; CHECK-NEXT: br i1 [[EXTRACT_T]], label %[[LATCH]], label %[[INDIRECT_LATCH:.*]]
58 ; CHECK: [[INDIRECT_LATCH]]:
59 ; CHECK-NEXT: br label %[[LATCH]]
61 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
62 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[IV]] to i32
63 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ZEXT]], 2
64 ; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]
66 ; CHECK-NEXT: ret void
71 loop.header: ; preds = %latch, %entry
72 %iv = phi i8 [ %iv.next, %latch ], [ 0, %entry ]
74 %extract.t = trunc i8 %and to i1
75 br i1 %extract.t, label %latch, label %indirect.latch
77 indirect.latch: ; preds = %loop.header
80 latch: ; preds = %indirect.latch, loop.header
81 %iv.next = add i8 %iv, 1
82 %zext = zext i8 %iv to i32
83 %cmp = icmp ult i32 %zext, 2
84 br i1 %cmp, label %loop.header, label %exit
86 exit: ; preds = %latch