| blob | aa9a070a7945092d96cb68a35785a3640778e4c6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
2 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-20 | FileCheck %s
4 define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.ptr, ptr %add.ptr64) {
5 ; CHECK-LABEL: define i32 @test(
6 ; CHECK-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
7 ; CHECK-NEXT: entry:
8 ; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[PIX1]], align 1
9 ; CHECK-NEXT: [[CONV1:%.*]] = zext i8 [[TMP0]] to i32
10 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[PIX1]], i32 0
11 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <2 x i32> zeroinitializer
12 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i64> <i64 4, i64 6>
13 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> poison, ptr [[PIX2]], i32 0
14 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x ptr> [[TMP4]], <2 x ptr> poison, <2 x i32> zeroinitializer
15 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, <2 x ptr> [[TMP5]], <2 x i64> <i64 4, i64 6>
16 ; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr i8, ptr [[PIX1]], i64 1
17 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, <2 x ptr> [[TMP5]], <2 x i64> <i64 1, i64 3>
18 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i64> <i64 5, i64 7>
19 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, <2 x ptr> [[TMP5]], <2 x i64> <i64 5, i64 7>
20 ; CHECK-NEXT: [[ARRAYIDX22:%.*]] = getelementptr i8, ptr [[PIX2]], i64 2
21 ; CHECK-NEXT: [[ARRAYIDX32:%.*]] = getelementptr i8, ptr [[PIX1]], i64 3
22 ; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[ARRAYIDX32]], align 1
23 ; CHECK-NEXT: [[CONV33:%.*]] = zext i8 [[TMP10]] to i32
24 ; CHECK-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
25 ; CHECK-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
26 ; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[ADD_PTR3]], align 1
27 ; CHECK-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP11]] to i32
28 ; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[ADD_PTR644]], align 1
29 ; CHECK-NEXT: [[ARRAYIDX8_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 1
30 ; CHECK-NEXT: [[ARRAYIDX22_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 2
31 ; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr [[ARRAYIDX22_1]], align 1
32 ; CHECK-NEXT: [[ARRAYIDX32_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 3
33 ; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX32_1]], align 1
34 ; CHECK-NEXT: [[CONV33_1:%.*]] = zext i8 [[TMP14]] to i32
35 ; CHECK-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
36 ; CHECK-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
37 ; CHECK-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
38 ; CHECK-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
39 ; CHECK-NEXT: [[TMP15:%.*]] = load <2 x i8>, ptr [[ADD_PTR_1]], align 1
40 ; CHECK-NEXT: [[TMP16:%.*]] = zext <2 x i8> [[TMP15]] to <2 x i32>
41 ; CHECK-NEXT: [[TMP17:%.*]] = load <2 x i8>, ptr [[ADD_PTR64_1]], align 1
42 ; CHECK-NEXT: [[TMP18:%.*]] = zext <2 x i8> [[TMP17]] to <2 x i32>
43 ; CHECK-NEXT: [[TMP19:%.*]] = sub <2 x i32> [[TMP16]], [[TMP18]]
44 ; CHECK-NEXT: [[TMP20:%.*]] = load <2 x i8>, ptr [[ARRAYIDX3_2]], align 1
45 ; CHECK-NEXT: [[TMP21:%.*]] = zext <2 x i8> [[TMP20]] to <2 x i32>
46 ; CHECK-NEXT: [[TMP22:%.*]] = load <2 x i8>, ptr [[ARRAYIDX5_2]], align 1
47 ; CHECK-NEXT: [[TMP23:%.*]] = zext <2 x i8> [[TMP22]] to <2 x i32>
48 ; CHECK-NEXT: [[TMP24:%.*]] = sub <2 x i32> [[TMP21]], [[TMP23]]
49 ; CHECK-NEXT: [[TMP25:%.*]] = shl <2 x i32> [[TMP24]], <i32 16, i32 16>
50 ; CHECK-NEXT: [[TMP26:%.*]] = add <2 x i32> [[TMP25]], [[TMP19]]
51 ; CHECK-NEXT: [[ARRAYIDX20_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 2
52 ; CHECK-NEXT: [[ARRAYIDX22_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 2
53 ; CHECK-NEXT: [[ARRAYIDX25_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 6
54 ; CHECK-NEXT: [[ARRAYIDX27_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 6
55 ; CHECK-NEXT: [[TMP27:%.*]] = load <2 x i8>, ptr [[ARRAYIDX20_2]], align 1
56 ; CHECK-NEXT: [[TMP28:%.*]] = zext <2 x i8> [[TMP27]] to <2 x i32>
57 ; CHECK-NEXT: [[TMP29:%.*]] = load <2 x i8>, ptr [[ARRAYIDX22_2]], align 1
58 ; CHECK-NEXT: [[TMP30:%.*]] = zext <2 x i8> [[TMP29]] to <2 x i32>
59 ; CHECK-NEXT: [[TMP31:%.*]] = sub <2 x i32> [[TMP28]], [[TMP30]]
60 ; CHECK-NEXT: [[TMP32:%.*]] = load <2 x i8>, ptr [[ARRAYIDX25_2]], align 1
61 ; CHECK-NEXT: [[TMP33:%.*]] = zext <2 x i8> [[TMP32]] to <2 x i32>
62 ; CHECK-NEXT: [[TMP34:%.*]] = load <2 x i8>, ptr [[ARRAYIDX27_2]], align 1
63 ; CHECK-NEXT: [[TMP35:%.*]] = zext <2 x i8> [[TMP34]] to <2 x i32>
64 ; CHECK-NEXT: [[TMP36:%.*]] = sub <2 x i32> [[TMP33]], [[TMP35]]
65 ; CHECK-NEXT: [[TMP37:%.*]] = shl <2 x i32> [[TMP36]], <i32 16, i32 16>
66 ; CHECK-NEXT: [[TMP38:%.*]] = add <2 x i32> [[TMP37]], [[TMP31]]
67 ; CHECK-NEXT: [[ADD44_2:%.*]] = extractelement <2 x i32> [[TMP26]], i32 0
68 ; CHECK-NEXT: [[CONV:%.*]] = extractelement <2 x i32> [[TMP26]], i32 1
69 ; CHECK-NEXT: [[ADD44_3:%.*]] = add i32 [[CONV]], [[ADD44_2]]
70 ; CHECK-NEXT: [[SUB51_2:%.*]] = sub i32 [[ADD44_2]], [[CONV]]
71 ; CHECK-NEXT: [[SUB45_2:%.*]] = extractelement <2 x i32> [[TMP38]], i32 0
72 ; CHECK-NEXT: [[SUB47_2:%.*]] = extractelement <2 x i32> [[TMP38]], i32 1
73 ; CHECK-NEXT: [[ADD46_2:%.*]] = add i32 [[SUB47_2]], [[SUB45_2]]
74 ; CHECK-NEXT: [[SUB59_2:%.*]] = sub i32 [[SUB45_2]], [[SUB47_2]]
75 ; CHECK-NEXT: [[ADD48_2:%.*]] = add i32 [[ADD46_2]], [[ADD44_3]]
76 ; CHECK-NEXT: [[TMP43:%.*]] = load i8, ptr null, align 1
77 ; CHECK-NEXT: [[ARRAYIDX20_3:%.*]] = getelementptr i8, ptr null, i64 2
78 ; CHECK-NEXT: [[ARRAYIDX22_3:%.*]] = getelementptr i8, ptr null, i64 2
79 ; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr null, align 1
80 ; CHECK-NEXT: [[TMP45:%.*]] = insertelement <2 x ptr> <ptr poison, ptr null>, ptr [[ARRAYIDX20_3]], i32 0
81 ; CHECK-NEXT: [[TMP46:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP45]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
82 ; CHECK-NEXT: [[TMP47:%.*]] = zext <2 x i8> [[TMP46]] to <2 x i32>
83 ; CHECK-NEXT: [[TMP48:%.*]] = insertelement <2 x ptr> <ptr poison, ptr null>, ptr [[ARRAYIDX22_3]], i32 0
84 ; CHECK-NEXT: [[TMP49:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP48]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
85 ; CHECK-NEXT: [[TMP50:%.*]] = zext <2 x i8> [[TMP49]] to <2 x i32>
86 ; CHECK-NEXT: [[TMP51:%.*]] = sub <2 x i32> [[TMP47]], [[TMP50]]
87 ; CHECK-NEXT: [[TMP52:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> <i1 true, i1 true>, i32 2)
88 ; CHECK-NEXT: [[TMP53:%.*]] = zext <2 x i8> [[TMP52]] to <2 x i32>
89 ; CHECK-NEXT: [[TMP54:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> getelementptr (i8, <2 x ptr> zeroinitializer, <2 x i64> <i64 6, i64 4>), i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
90 ; CHECK-NEXT: [[TMP55:%.*]] = zext <2 x i8> [[TMP54]] to <2 x i32>
91 ; CHECK-NEXT: [[TMP56:%.*]] = sub <2 x i32> [[TMP53]], [[TMP55]]
92 ; CHECK-NEXT: [[TMP57:%.*]] = shl <2 x i32> [[TMP56]], <i32 16, i32 16>
93 ; CHECK-NEXT: [[TMP58:%.*]] = add <2 x i32> [[TMP57]], [[TMP51]]
94 ; CHECK-NEXT: [[TMP59:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> getelementptr (i8, <2 x ptr> zeroinitializer, <2 x i64> <i64 3, i64 1>), i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
95 ; CHECK-NEXT: [[TMP60:%.*]] = zext <2 x i8> [[TMP59]] to <2 x i32>
96 ; CHECK-NEXT: [[TMP61:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> getelementptr (i8, <2 x ptr> zeroinitializer, <2 x i64> <i64 3, i64 1>), i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
97 ; CHECK-NEXT: [[TMP62:%.*]] = zext <2 x i8> [[TMP61]] to <2 x i32>
98 ; CHECK-NEXT: [[TMP63:%.*]] = sub <2 x i32> [[TMP60]], [[TMP62]]
99 ; CHECK-NEXT: [[TMP64:%.*]] = insertelement <2 x i8> poison, i8 [[TMP44]], i32 0
100 ; CHECK-NEXT: [[TMP65:%.*]] = insertelement <2 x i8> [[TMP64]], i8 [[TMP43]], i32 1
101 ; CHECK-NEXT: [[TMP66:%.*]] = zext <2 x i8> [[TMP65]] to <2 x i32>
102 ; CHECK-NEXT: [[TMP67:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> getelementptr (i8, <2 x ptr> zeroinitializer, <2 x i64> <i64 7, i64 5>), i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
103 ; CHECK-NEXT: [[TMP68:%.*]] = zext <2 x i8> [[TMP67]] to <2 x i32>
104 ; CHECK-NEXT: [[TMP69:%.*]] = sub <2 x i32> [[TMP66]], [[TMP68]]
105 ; CHECK-NEXT: [[TMP70:%.*]] = shl <2 x i32> [[TMP69]], <i32 16, i32 16>
106 ; CHECK-NEXT: [[TMP71:%.*]] = add <2 x i32> [[TMP70]], [[TMP63]]
107 ; CHECK-NEXT: [[TMP72:%.*]] = add <2 x i32> [[TMP71]], [[TMP58]]
108 ; CHECK-NEXT: [[TMP190:%.*]] = sub <2 x i32> [[TMP58]], [[TMP71]]
109 ; CHECK-NEXT: [[TMP74:%.*]] = extractelement <2 x i32> [[TMP72]], i32 0
110 ; CHECK-NEXT: [[TMP75:%.*]] = extractelement <2 x i32> [[TMP72]], i32 1
111 ; CHECK-NEXT: [[ADD48_3:%.*]] = add i32 [[TMP74]], [[TMP75]]
112 ; CHECK-NEXT: [[ADD94:%.*]] = add i32 [[ADD48_3]], [[ADD48_2]]
113 ; CHECK-NEXT: [[SUB102:%.*]] = sub i32 [[ADD48_2]], [[ADD48_3]]
114 ; CHECK-NEXT: [[TMP79:%.*]] = extractelement <2 x i32> [[TMP47]], i32 1
115 ; CHECK-NEXT: [[SHR_I49_2:%.*]] = lshr i32 [[TMP79]], 15
116 ; CHECK-NEXT: [[AND_I50_2:%.*]] = and i32 [[SHR_I49_2]], 65537
117 ; CHECK-NEXT: [[MUL_I51_2:%.*]] = mul i32 [[AND_I50_2]], 65535
118 ; CHECK-NEXT: [[SHR_I49_3:%.*]] = lshr i32 [[ADD46_2]], 15
119 ; CHECK-NEXT: [[AND_I50_3:%.*]] = and i32 [[SHR_I49_3]], 65537
120 ; CHECK-NEXT: [[MUL_I51_3:%.*]] = mul i32 [[AND_I50_3]], 65535
121 ; CHECK-NEXT: [[TMP107:%.*]] = extractelement <2 x i32> [[TMP16]], i32 0
122 ; CHECK-NEXT: [[SHR_I49_5:%.*]] = lshr i32 [[TMP107]], 15
123 ; CHECK-NEXT: [[AND_I50_5:%.*]] = and i32 [[SHR_I49_5]], 65537
124 ; CHECK-NEXT: [[MUL_I51_5:%.*]] = mul i32 [[AND_I50_5]], 65535
125 ; CHECK-NEXT: [[SHR_I49_4:%.*]] = lshr i32 [[CONV_1]], 15
126 ; CHECK-NEXT: [[AND_I50_4:%.*]] = and i32 [[SHR_I49_4]], 65537
127 ; CHECK-NEXT: [[MUL_I51_4:%.*]] = mul i32 [[AND_I50_4]], 65535
128 ; CHECK-NEXT: [[SHR_I49_6:%.*]] = lshr i32 [[CONV1]], 15
129 ; CHECK-NEXT: [[AND_I50_6:%.*]] = and i32 [[SHR_I49_6]], 65537
130 ; CHECK-NEXT: [[MUL_I51_6:%.*]] = mul i32 [[AND_I50_6]], 65535
131 ; CHECK-NEXT: [[TMP78:%.*]] = load <2 x i8>, ptr [[ARRAYIDX8]], align 1
132 ; CHECK-NEXT: [[TMP102:%.*]] = zext <2 x i8> [[TMP78]] to <2 x i32>
133 ; CHECK-NEXT: [[TMP80:%.*]] = insertelement <2 x ptr> [[TMP5]], ptr [[ARRAYIDX22]], i32 1
134 ; CHECK-NEXT: [[TMP81:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP80]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
135 ; CHECK-NEXT: [[TMP82:%.*]] = zext <2 x i8> [[TMP81]] to <2 x i32>
136 ; CHECK-NEXT: [[TMP83:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP3]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
137 ; CHECK-NEXT: [[TMP84:%.*]] = zext <2 x i8> [[TMP83]] to <2 x i32>
138 ; CHECK-NEXT: [[TMP85:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP6]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
139 ; CHECK-NEXT: [[TMP86:%.*]] = zext <2 x i8> [[TMP85]] to <2 x i32>
140 ; CHECK-NEXT: [[TMP87:%.*]] = sub <2 x i32> [[TMP84]], [[TMP86]]
141 ; CHECK-NEXT: [[TMP88:%.*]] = shl <2 x i32> [[TMP87]], <i32 16, i32 16>
142 ; CHECK-NEXT: [[TMP89:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP7]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
143 ; CHECK-NEXT: [[TMP90:%.*]] = zext <2 x i8> [[TMP89]] to <2 x i32>
144 ; CHECK-NEXT: [[TMP91:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP8]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
145 ; CHECK-NEXT: [[TMP92:%.*]] = zext <2 x i8> [[TMP91]] to <2 x i32>
146 ; CHECK-NEXT: [[TMP93:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP9]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
147 ; CHECK-NEXT: [[TMP94:%.*]] = zext <2 x i8> [[TMP93]] to <2 x i32>
148 ; CHECK-NEXT: [[TMP95:%.*]] = sub <2 x i32> [[TMP92]], [[TMP94]]
149 ; CHECK-NEXT: [[TMP96:%.*]] = shl <2 x i32> [[TMP95]], <i32 16, i32 16>
150 ; CHECK-NEXT: [[TMP97:%.*]] = insertelement <2 x i32> [[TMP102]], i32 [[CONV33]], i32 1
151 ; CHECK-NEXT: [[TMP98:%.*]] = sub <2 x i32> [[TMP97]], [[TMP90]]
152 ; CHECK-NEXT: [[TMP104:%.*]] = add <2 x i32> [[TMP96]], [[TMP98]]
153 ; CHECK-NEXT: [[TMP100:%.*]] = insertelement <2 x i32> [[TMP102]], i32 [[CONV1]], i32 0
154 ; CHECK-NEXT: [[TMP101:%.*]] = sub <2 x i32> [[TMP100]], [[TMP82]]
155 ; CHECK-NEXT: [[TMP200:%.*]] = add <2 x i32> [[TMP88]], [[TMP101]]
156 ; CHECK-NEXT: [[TMP128:%.*]] = shufflevector <2 x i32> [[TMP104]], <2 x i32> [[TMP200]], <2 x i32> <i32 0, i32 2>
157 ; CHECK-NEXT: [[TMP106:%.*]] = add <2 x i32> [[TMP104]], [[TMP200]]
158 ; CHECK-NEXT: [[TMP105:%.*]] = sub <2 x i32> [[TMP200]], [[TMP104]]
159 ; CHECK-NEXT: [[TMP238:%.*]] = extractelement <2 x i32> [[TMP106]], i32 0
160 ; CHECK-NEXT: [[TMP108:%.*]] = extractelement <2 x i32> [[TMP106]], i32 1
161 ; CHECK-NEXT: [[ADD48:%.*]] = add i32 [[TMP108]], [[TMP238]]
162 ; CHECK-NEXT: [[TMP142:%.*]] = extractelement <2 x i32> [[TMP105]], i32 1
163 ; CHECK-NEXT: [[SHR_I59_1:%.*]] = lshr i32 [[TMP108]], 15
164 ; CHECK-NEXT: [[AND_I60_1:%.*]] = and i32 [[SHR_I59_1]], 65537
165 ; CHECK-NEXT: [[MUL_I61_1:%.*]] = mul i32 [[AND_I60_1]], 65535
166 ; CHECK-NEXT: [[SHR_I59_4:%.*]] = lshr i32 [[TMP142]], 15
167 ; CHECK-NEXT: [[AND_I60_4:%.*]] = and i32 [[SHR_I59_4]], 65537
168 ; CHECK-NEXT: [[MUL_I61_4:%.*]] = mul i32 [[AND_I60_4]], 65535
169 ; CHECK-NEXT: [[TMP109:%.*]] = load <2 x i8>, ptr [[ARRAYIDX8_1]], align 1
170 ; CHECK-NEXT: [[TMP110:%.*]] = zext <2 x i8> [[TMP109]] to <2 x i32>
171 ; CHECK-NEXT: [[TMP111:%.*]] = insertelement <2 x i8> poison, i8 [[TMP12]], i32 0
172 ; CHECK-NEXT: [[TMP112:%.*]] = insertelement <2 x i8> [[TMP111]], i8 [[TMP13]], i32 1
173 ; CHECK-NEXT: [[TMP113:%.*]] = zext <2 x i8> [[TMP112]] to <2 x i32>
174 ; CHECK-NEXT: [[TMP114:%.*]] = insertelement <2 x ptr> poison, ptr [[ADD_PTR3]], i32 0
175 ; CHECK-NEXT: [[TMP115:%.*]] = shufflevector <2 x ptr> [[TMP114]], <2 x ptr> poison, <2 x i32> zeroinitializer
176 ; CHECK-NEXT: [[TMP116:%.*]] = getelementptr i8, <2 x ptr> [[TMP115]], <2 x i64> <i64 4, i64 6>
177 ; CHECK-NEXT: [[TMP117:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP116]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
178 ; CHECK-NEXT: [[TMP118:%.*]] = zext <2 x i8> [[TMP117]] to <2 x i32>
179 ; CHECK-NEXT: [[TMP119:%.*]] = insertelement <2 x ptr> poison, ptr [[ADD_PTR644]], i32 0
180 ; CHECK-NEXT: [[TMP120:%.*]] = shufflevector <2 x ptr> [[TMP119]], <2 x ptr> poison, <2 x i32> zeroinitializer
181 ; CHECK-NEXT: [[TMP121:%.*]] = getelementptr i8, <2 x ptr> [[TMP120]], <2 x i64> <i64 4, i64 6>
182 ; CHECK-NEXT: [[TMP122:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP121]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
183 ; CHECK-NEXT: [[TMP123:%.*]] = zext <2 x i8> [[TMP122]] to <2 x i32>
184 ; CHECK-NEXT: [[TMP124:%.*]] = sub <2 x i32> [[TMP118]], [[TMP123]]
185 ; CHECK-NEXT: [[TMP125:%.*]] = shl <2 x i32> [[TMP124]], <i32 16, i32 16>
186 ; CHECK-NEXT: [[TMP126:%.*]] = getelementptr i8, <2 x ptr> [[TMP120]], <2 x i64> <i64 1, i64 3>
187 ; CHECK-NEXT: [[TMP127:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP126]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
188 ; CHECK-NEXT: [[TMP144:%.*]] = zext <2 x i8> [[TMP127]] to <2 x i32>
189 ; CHECK-NEXT: [[TMP129:%.*]] = getelementptr i8, <2 x ptr> [[TMP115]], <2 x i64> <i64 5, i64 7>
190 ; CHECK-NEXT: [[TMP130:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP129]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
191 ; CHECK-NEXT: [[TMP131:%.*]] = zext <2 x i8> [[TMP130]] to <2 x i32>
192 ; CHECK-NEXT: [[TMP132:%.*]] = getelementptr i8, <2 x ptr> [[TMP120]], <2 x i64> <i64 5, i64 7>
193 ; CHECK-NEXT: [[TMP133:%.*]] = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> [[TMP132]], i32 1, <2 x i1> <i1 true, i1 true>, <2 x i8> poison)
194 ; CHECK-NEXT: [[TMP134:%.*]] = zext <2 x i8> [[TMP133]] to <2 x i32>
195 ; CHECK-NEXT: [[TMP135:%.*]] = sub <2 x i32> [[TMP131]], [[TMP134]]
196 ; CHECK-NEXT: [[TMP136:%.*]] = shl <2 x i32> [[TMP135]], <i32 16, i32 16>
197 ; CHECK-NEXT: [[TMP137:%.*]] = insertelement <2 x i32> [[TMP110]], i32 [[CONV33_1]], i32 1
198 ; CHECK-NEXT: [[TMP138:%.*]] = sub <2 x i32> [[TMP137]], [[TMP144]]
199 ; CHECK-NEXT: [[TMP139:%.*]] = add <2 x i32> [[TMP136]], [[TMP138]]
200 ; CHECK-NEXT: [[TMP140:%.*]] = insertelement <2 x i32> [[TMP110]], i32 [[CONV_1]], i32 0
201 ; CHECK-NEXT: [[TMP141:%.*]] = sub <2 x i32> [[TMP140]], [[TMP113]]
202 ; CHECK-NEXT: [[TMP155:%.*]] = add <2 x i32> [[TMP125]], [[TMP141]]
203 ; CHECK-NEXT: [[TMP143:%.*]] = add <2 x i32> [[TMP139]], [[TMP155]]
204 ; CHECK-NEXT: [[TMP189:%.*]] = sub <2 x i32> [[TMP155]], [[TMP139]]
205 ; CHECK-NEXT: [[TMP145:%.*]] = extractelement <2 x i32> [[TMP143]], i32 0
206 ; CHECK-NEXT: [[TMP146:%.*]] = extractelement <2 x i32> [[TMP143]], i32 1
207 ; CHECK-NEXT: [[ADD48_1:%.*]] = add i32 [[TMP146]], [[TMP145]]
208 ; CHECK-NEXT: [[SHR_I54:%.*]] = lshr i32 [[TMP146]], 15
209 ; CHECK-NEXT: [[AND_I55:%.*]] = and i32 [[SHR_I54]], 65537
210 ; CHECK-NEXT: [[MUL_I56:%.*]] = mul i32 [[AND_I55]], 65535
211 ; CHECK-NEXT: [[TMP147:%.*]] = lshr <2 x i32> [[TMP110]], <i32 15, i32 15>
212 ; CHECK-NEXT: [[TMP148:%.*]] = and <2 x i32> [[TMP147]], <i32 65537, i32 65537>
213 ; CHECK-NEXT: [[TMP149:%.*]] = mul <2 x i32> [[TMP148]], <i32 65535, i32 65535>
214 ; CHECK-NEXT: [[ADD78:%.*]] = add i32 [[ADD48_1]], [[ADD48]]
215 ; CHECK-NEXT: [[SUB86:%.*]] = sub i32 [[ADD48]], [[ADD48_1]]
216 ; CHECK-NEXT: [[ADD103:%.*]] = add i32 [[ADD94]], [[ADD78]]
217 ; CHECK-NEXT: [[SUB104:%.*]] = sub i32 [[ADD78]], [[ADD94]]
218 ; CHECK-NEXT: [[ADD105:%.*]] = add i32 [[SUB102]], [[SUB86]]
219 ; CHECK-NEXT: [[SUB106:%.*]] = sub i32 [[SUB86]], [[SUB102]]
220 ; CHECK-NEXT: [[ADD_I:%.*]] = add i32 [[MUL_I51_2]], [[ADD103]]
221 ; CHECK-NEXT: [[XOR_I:%.*]] = xor i32 [[ADD_I]], [[TMP79]]
222 ; CHECK-NEXT: [[ADD_I52:%.*]] = add i32 [[MUL_I51_3]], [[ADD105]]
223 ; CHECK-NEXT: [[XOR_I53:%.*]] = xor i32 [[ADD_I52]], [[ADD46_2]]
224 ; CHECK-NEXT: [[ADD_I57:%.*]] = add i32 [[MUL_I56]], [[SUB104]]
225 ; CHECK-NEXT: [[XOR_I58:%.*]] = xor i32 [[ADD_I57]], [[TMP146]]
226 ; CHECK-NEXT: [[ADD_I62:%.*]] = add i32 [[MUL_I61_1]], [[SUB106]]
227 ; CHECK-NEXT: [[XOR_I63:%.*]] = xor i32 [[ADD_I62]], [[TMP108]]
228 ; CHECK-NEXT: [[ADD110:%.*]] = add i32 [[XOR_I53]], [[XOR_I]]
229 ; CHECK-NEXT: [[ADD112:%.*]] = add i32 [[ADD110]], [[XOR_I58]]
230 ; CHECK-NEXT: [[ADD113:%.*]] = add i32 [[ADD112]], [[XOR_I63]]
231 ; CHECK-NEXT: [[TMP150:%.*]] = shufflevector <2 x i32> [[TMP105]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
232 ; CHECK-NEXT: [[TMP151:%.*]] = insertelement <2 x i32> [[TMP150]], i32 [[SUB59_2]], i32 1
233 ; CHECK-NEXT: [[TMP152:%.*]] = insertelement <2 x i32> [[TMP105]], i32 [[SUB51_2]], i32 1
234 ; CHECK-NEXT: [[TMP153:%.*]] = add <2 x i32> [[TMP151]], [[TMP152]]
235 ; CHECK-NEXT: [[TMP154:%.*]] = shufflevector <2 x i32> [[TMP189]], <2 x i32> [[TMP190]], <2 x i32> <i32 1, i32 2>
236 ; CHECK-NEXT: [[TMP184:%.*]] = shufflevector <2 x i32> [[TMP189]], <2 x i32> [[TMP190]], <2 x i32> <i32 0, i32 3>
237 ; CHECK-NEXT: [[TMP156:%.*]] = add <2 x i32> [[TMP154]], [[TMP184]]
238 ; CHECK-NEXT: [[TMP157:%.*]] = extractelement <2 x i32> [[TMP153]], i32 1
239 ; CHECK-NEXT: [[TMP158:%.*]] = extractelement <2 x i32> [[TMP156]], i32 1
240 ; CHECK-NEXT: [[TMP159:%.*]] = shufflevector <2 x i32> [[TMP156]], <2 x i32> [[TMP153]], <2 x i32> <i32 1, i32 3>
241 ; CHECK-NEXT: [[ADD78_2:%.*]] = add i32 [[TMP158]], [[TMP157]]
242 ; CHECK-NEXT: [[TMP160:%.*]] = extractelement <2 x i32> [[TMP153]], i32 0
243 ; CHECK-NEXT: [[TMP161:%.*]] = extractelement <2 x i32> [[TMP156]], i32 0
244 ; CHECK-NEXT: [[TMP162:%.*]] = shufflevector <2 x i32> [[TMP156]], <2 x i32> [[TMP153]], <2 x i32> <i32 0, i32 2>
245 ; CHECK-NEXT: [[ADD94_1:%.*]] = add i32 [[TMP161]], [[TMP160]]
246 ; CHECK-NEXT: [[TMP163:%.*]] = sub <2 x i32> [[TMP153]], [[TMP156]]
247 ; CHECK-NEXT: [[TMP164:%.*]] = extractelement <2 x i32> [[TMP163]], i32 0
248 ; CHECK-NEXT: [[TMP165:%.*]] = extractelement <2 x i32> [[TMP163]], i32 1
249 ; CHECK-NEXT: [[ADD105_1:%.*]] = add i32 [[TMP165]], [[TMP164]]
250 ; CHECK-NEXT: [[SUB106_1:%.*]] = sub i32 [[TMP164]], [[TMP165]]
251 ; CHECK-NEXT: [[ADD_I52_1:%.*]] = add i32 [[MUL_I51_5]], [[ADD105_1]]
252 ; CHECK-NEXT: [[XOR_I53_1:%.*]] = xor i32 [[ADD_I52_1]], [[TMP107]]
253 ; CHECK-NEXT: [[TMP166:%.*]] = shufflevector <2 x i32> [[TMP16]], <2 x i32> [[TMP189]], <2 x i32> <i32 1, i32 3>
254 ; CHECK-NEXT: [[TMP167:%.*]] = lshr <2 x i32> [[TMP166]], <i32 15, i32 15>
255 ; CHECK-NEXT: [[TMP168:%.*]] = and <2 x i32> [[TMP167]], <i32 65537, i32 65537>
256 ; CHECK-NEXT: [[TMP169:%.*]] = mul <2 x i32> [[TMP168]], <i32 65535, i32 65535>
257 ; CHECK-NEXT: [[TMP172:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_1]], i32 0
258 ; CHECK-NEXT: [[TMP171:%.*]] = shufflevector <2 x i32> [[TMP172]], <2 x i32> poison, <2 x i32> zeroinitializer
259 ; CHECK-NEXT: [[TMP208:%.*]] = insertelement <2 x i32> poison, i32 [[ADD78_2]], i32 0
260 ; CHECK-NEXT: [[TMP209:%.*]] = shufflevector <2 x i32> [[TMP208]], <2 x i32> poison, <2 x i32> zeroinitializer
261 ; CHECK-NEXT: [[TMP282:%.*]] = add <2 x i32> [[TMP171]], [[TMP209]]
262 ; CHECK-NEXT: [[TMP211:%.*]] = sub <2 x i32> [[TMP171]], [[TMP209]]
263 ; CHECK-NEXT: [[TMP283:%.*]] = shufflevector <2 x i32> [[TMP282]], <2 x i32> [[TMP211]], <2 x i32> <i32 0, i32 3>
264 ; CHECK-NEXT: [[TMP177:%.*]] = add <2 x i32> [[TMP169]], [[TMP283]]
265 ; CHECK-NEXT: [[TMP178:%.*]] = xor <2 x i32> [[TMP177]], [[TMP166]]
266 ; CHECK-NEXT: [[ADD_I62_1:%.*]] = add i32 [[MUL_I61_4]], [[SUB106_1]]
267 ; CHECK-NEXT: [[XOR_I63_1:%.*]] = xor i32 [[ADD_I62_1]], [[TMP142]]
268 ; CHECK-NEXT: [[ADD108_1:%.*]] = add i32 [[XOR_I53_1]], [[ADD113]]
269 ; CHECK-NEXT: [[TMP179:%.*]] = extractelement <2 x i32> [[TMP178]], i32 0
270 ; CHECK-NEXT: [[ADD110_1:%.*]] = add i32 [[ADD108_1]], [[TMP179]]
271 ; CHECK-NEXT: [[TMP180:%.*]] = extractelement <2 x i32> [[TMP178]], i32 1
272 ; CHECK-NEXT: [[ADD112_1:%.*]] = add i32 [[ADD110_1]], [[TMP180]]
273 ; CHECK-NEXT: [[ADD113_1:%.*]] = add i32 [[ADD112_1]], [[XOR_I63_1]]
274 ; CHECK-NEXT: [[TMP181:%.*]] = shufflevector <2 x i32> [[TMP106]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
275 ; CHECK-NEXT: [[TMP182:%.*]] = insertelement <2 x i32> [[TMP181]], i32 [[ADD44_3]], i32 0
276 ; CHECK-NEXT: [[TMP183:%.*]] = insertelement <2 x i32> [[TMP106]], i32 [[ADD46_2]], i32 0
277 ; CHECK-NEXT: [[TMP195:%.*]] = sub <2 x i32> [[TMP182]], [[TMP183]]
278 ; CHECK-NEXT: [[TMP185:%.*]] = shufflevector <2 x i32> [[TMP72]], <2 x i32> [[TMP143]], <2 x i32> <i32 1, i32 2>
279 ; CHECK-NEXT: [[TMP186:%.*]] = shufflevector <2 x i32> [[TMP72]], <2 x i32> [[TMP143]], <2 x i32> <i32 0, i32 3>
280 ; CHECK-NEXT: [[TMP187:%.*]] = sub <2 x i32> [[TMP185]], [[TMP186]]
281 ; CHECK-NEXT: [[TMP188:%.*]] = extractelement <2 x i32> [[TMP195]], i32 0
282 ; CHECK-NEXT: [[TMP196:%.*]] = extractelement <2 x i32> [[TMP187]], i32 0
283 ; CHECK-NEXT: [[TMP199:%.*]] = shufflevector <2 x i32> [[TMP187]], <2 x i32> [[TMP195]], <2 x i32> <i32 0, i32 2>
284 ; CHECK-NEXT: [[ADD94_4:%.*]] = add i32 [[TMP196]], [[TMP188]]
285 ; CHECK-NEXT: [[TMP191:%.*]] = extractelement <2 x i32> [[TMP195]], i32 1
286 ; CHECK-NEXT: [[TMP192:%.*]] = extractelement <2 x i32> [[TMP187]], i32 1
287 ; CHECK-NEXT: [[TMP193:%.*]] = shufflevector <2 x i32> [[TMP187]], <2 x i32> [[TMP195]], <2 x i32> <i32 1, i32 3>
288 ; CHECK-NEXT: [[ADD94_2:%.*]] = add i32 [[TMP192]], [[TMP191]]
289 ; CHECK-NEXT: [[TMP194:%.*]] = sub <2 x i32> [[TMP195]], [[TMP187]]
290 ; CHECK-NEXT: [[TMP244:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_2]], i32 0
291 ; CHECK-NEXT: [[TMP245:%.*]] = shufflevector <2 x i32> [[TMP244]], <2 x i32> poison, <2 x i32> zeroinitializer
292 ; CHECK-NEXT: [[TMP197:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_4]], i32 0
293 ; CHECK-NEXT: [[TMP198:%.*]] = shufflevector <2 x i32> [[TMP197]], <2 x i32> poison, <2 x i32> zeroinitializer
294 ; CHECK-NEXT: [[TMP216:%.*]] = add <2 x i32> [[TMP245]], [[TMP198]]
295 ; CHECK-NEXT: [[TMP210:%.*]] = sub <2 x i32> [[TMP245]], [[TMP198]]
296 ; CHECK-NEXT: [[TMP221:%.*]] = shufflevector <2 x i32> [[TMP216]], <2 x i32> [[TMP210]], <2 x i32> <i32 0, i32 3>
297 ; CHECK-NEXT: [[TMP215:%.*]] = extractelement <2 x i32> [[TMP194]], i32 0
298 ; CHECK-NEXT: [[TMP203:%.*]] = extractelement <2 x i32> [[TMP194]], i32 1
299 ; CHECK-NEXT: [[ADD105_2:%.*]] = add i32 [[TMP215]], [[TMP203]]
300 ; CHECK-NEXT: [[SUB106_2:%.*]] = sub i32 [[TMP203]], [[TMP215]]
301 ; CHECK-NEXT: [[ADD_I52_2:%.*]] = add i32 [[MUL_I51_4]], [[ADD105_2]]
302 ; CHECK-NEXT: [[XOR_I53_2:%.*]] = xor i32 [[ADD_I52_2]], [[CONV_1]]
303 ; CHECK-NEXT: [[TMP266:%.*]] = add <2 x i32> [[TMP149]], [[TMP221]]
304 ; CHECK-NEXT: [[TMP267:%.*]] = xor <2 x i32> [[TMP266]], [[TMP110]]
305 ; CHECK-NEXT: [[SHR_I59_2:%.*]] = lshr i32 [[TMP238]], 15
306 ; CHECK-NEXT: [[AND_I60_2:%.*]] = and i32 [[SHR_I59_2]], 65537
307 ; CHECK-NEXT: [[MUL_I61_2:%.*]] = mul i32 [[AND_I60_2]], 65535
308 ; CHECK-NEXT: [[ADD_I62_2:%.*]] = add i32 [[MUL_I61_2]], [[SUB106_2]]
309 ; CHECK-NEXT: [[XOR_I63_2:%.*]] = xor i32 [[ADD_I62_2]], [[TMP238]]
310 ; CHECK-NEXT: [[ADD108_2:%.*]] = add i32 [[XOR_I53_2]], [[ADD113_1]]
311 ; CHECK-NEXT: [[TMP206:%.*]] = extractelement <2 x i32> [[TMP267]], i32 0
312 ; CHECK-NEXT: [[ADD110_2:%.*]] = add i32 [[ADD108_2]], [[TMP206]]
313 ; CHECK-NEXT: [[TMP207:%.*]] = extractelement <2 x i32> [[TMP267]], i32 1
314 ; CHECK-NEXT: [[ADD112_2:%.*]] = add i32 [[ADD110_2]], [[TMP207]]
315 ; CHECK-NEXT: [[ADD113_2:%.*]] = add i32 [[ADD112_2]], [[XOR_I63_2]]
316 ; CHECK-NEXT: [[TMP222:%.*]] = insertelement <2 x i32> [[TMP150]], i32 [[SUB51_2]], i32 0
317 ; CHECK-NEXT: [[TMP225:%.*]] = insertelement <2 x i32> [[TMP105]], i32 [[SUB59_2]], i32 0
318 ; CHECK-NEXT: [[TMP226:%.*]] = sub <2 x i32> [[TMP222]], [[TMP225]]
319 ; CHECK-NEXT: [[TMP227:%.*]] = shufflevector <2 x i32> [[TMP190]], <2 x i32> [[TMP189]], <2 x i32> <i32 1, i32 2>
320 ; CHECK-NEXT: [[TMP212:%.*]] = shufflevector <2 x i32> [[TMP190]], <2 x i32> [[TMP189]], <2 x i32> <i32 0, i32 3>
321 ; CHECK-NEXT: [[TMP213:%.*]] = sub <2 x i32> [[TMP227]], [[TMP212]]
322 ; CHECK-NEXT: [[TMP214:%.*]] = extractelement <2 x i32> [[TMP226]], i32 0
323 ; CHECK-NEXT: [[TMP237:%.*]] = extractelement <2 x i32> [[TMP213]], i32 0
324 ; CHECK-NEXT: [[TMP239:%.*]] = shufflevector <2 x i32> [[TMP213]], <2 x i32> [[TMP226]], <2 x i32> <i32 0, i32 2>
325 ; CHECK-NEXT: [[ADD94_5:%.*]] = add i32 [[TMP237]], [[TMP214]]
326 ; CHECK-NEXT: [[TMP217:%.*]] = extractelement <2 x i32> [[TMP226]], i32 1
327 ; CHECK-NEXT: [[TMP218:%.*]] = extractelement <2 x i32> [[TMP213]], i32 1
328 ; CHECK-NEXT: [[TMP219:%.*]] = shufflevector <2 x i32> [[TMP213]], <2 x i32> [[TMP226]], <2 x i32> <i32 1, i32 3>
329 ; CHECK-NEXT: [[ADD94_3:%.*]] = add i32 [[TMP218]], [[TMP217]]
330 ; CHECK-NEXT: [[TMP240:%.*]] = sub <2 x i32> [[TMP226]], [[TMP213]]
331 ; CHECK-NEXT: [[TMP223:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_3]], i32 0
332 ; CHECK-NEXT: [[TMP224:%.*]] = shufflevector <2 x i32> [[TMP223]], <2 x i32> poison, <2 x i32> zeroinitializer
333 ; CHECK-NEXT: [[TMP241:%.*]] = insertelement <2 x i32> poison, i32 [[ADD94_5]], i32 0
334 ; CHECK-NEXT: [[TMP242:%.*]] = shufflevector <2 x i32> [[TMP241]], <2 x i32> poison, <2 x i32> zeroinitializer
335 ; CHECK-NEXT: [[TMP261:%.*]] = add <2 x i32> [[TMP224]], [[TMP242]]
336 ; CHECK-NEXT: [[TMP262:%.*]] = sub <2 x i32> [[TMP224]], [[TMP242]]
337 ; CHECK-NEXT: [[TMP220:%.*]] = shufflevector <2 x i32> [[TMP261]], <2 x i32> [[TMP262]], <2 x i32> <i32 0, i32 3>
338 ; CHECK-NEXT: [[TMP228:%.*]] = extractelement <2 x i32> [[TMP240]], i32 0
339 ; CHECK-NEXT: [[TMP229:%.*]] = extractelement <2 x i32> [[TMP240]], i32 1
340 ; CHECK-NEXT: [[ADD105_3:%.*]] = add i32 [[TMP228]], [[TMP229]]
341 ; CHECK-NEXT: [[SUB106_3:%.*]] = sub i32 [[TMP229]], [[TMP228]]
342 ; CHECK-NEXT: [[ADD_I52_3:%.*]] = add i32 [[MUL_I51_6]], [[ADD105_3]]
343 ; CHECK-NEXT: [[XOR_I53_3:%.*]] = xor i32 [[ADD_I52_3]], [[CONV1]]
344 ; CHECK-NEXT: [[TMP230:%.*]] = lshr <2 x i32> [[TMP102]], <i32 15, i32 15>
345 ; CHECK-NEXT: [[TMP231:%.*]] = and <2 x i32> [[TMP230]], <i32 65537, i32 65537>
346 ; CHECK-NEXT: [[TMP232:%.*]] = mul <2 x i32> [[TMP231]], <i32 65535, i32 65535>
347 ; CHECK-NEXT: [[TMP233:%.*]] = add <2 x i32> [[TMP232]], [[TMP220]]
348 ; CHECK-NEXT: [[TMP234:%.*]] = xor <2 x i32> [[TMP233]], [[TMP102]]
349 ; CHECK-NEXT: [[SHR_I59_3:%.*]] = lshr i32 [[CONV33]], 15
350 ; CHECK-NEXT: [[AND_I60_3:%.*]] = and i32 [[SHR_I59_3]], 65537
351 ; CHECK-NEXT: [[MUL_I61_3:%.*]] = mul i32 [[AND_I60_3]], 65535
352 ; CHECK-NEXT: [[ADD_I62_3:%.*]] = add i32 [[MUL_I61_3]], [[SUB106_3]]
353 ; CHECK-NEXT: [[XOR_I63_3:%.*]] = xor i32 [[ADD_I62_3]], [[CONV33]]
354 ; CHECK-NEXT: [[ADD108_3:%.*]] = add i32 [[XOR_I53_3]], [[ADD113_2]]
355 ; CHECK-NEXT: [[TMP235:%.*]] = extractelement <2 x i32> [[TMP234]], i32 0
356 ; CHECK-NEXT: [[ADD110_3:%.*]] = add i32 [[ADD108_3]], [[TMP235]]
357 ; CHECK-NEXT: [[TMP236:%.*]] = extractelement <2 x i32> [[TMP234]], i32 1
358 ; CHECK-NEXT: [[ADD112_3:%.*]] = add i32 [[ADD110_3]], [[TMP236]]
359 ; CHECK-NEXT: [[ADD113_3:%.*]] = add i32 [[ADD112_3]], [[XOR_I63_3]]
360 ; CHECK-NEXT: ret i32 [[ADD113_3]]
361 ;
362 entry:
363 %0 = load i8, ptr %pix1, align 1
364 %conv = zext i8 %0 to i32
365 %1 = load i8, ptr %pix2, align 1
366 %conv2 = zext i8 %1 to i32
367 %sub = sub i32 %conv, %conv2
368 %arrayidx3 = getelementptr i8, ptr %pix1, i64 4
369 %2 = load i8, ptr %arrayidx3, align 1
370 %conv4 = zext i8 %2 to i32
371 %arrayidx5 = getelementptr i8, ptr %pix2, i64 4
372 %3 = load i8, ptr %arrayidx5, align 1
373 %conv6 = zext i8 %3 to i32
374 %sub7 = sub i32 %conv4, %conv6
375 %shl = shl i32 %sub7, 16
376 %add = add i32 %shl, %sub
377 %arrayidx8 = getelementptr i8, ptr %pix1, i64 1
378 %4 = load i8, ptr %arrayidx8, align 1
379 %conv9 = zext i8 %4 to i32
380 %arrayidx10 = getelementptr i8, ptr %pix2, i64 1
381 %5 = load i8, ptr %arrayidx10, align 1
382 %conv11 = zext i8 %5 to i32
383 %sub12 = sub i32 %conv9, %conv11
384 %arrayidx13 = getelementptr i8, ptr %pix1, i64 5
385 %6 = load i8, ptr %arrayidx13, align 1
386 %conv14 = zext i8 %6 to i32
387 %arrayidx15 = getelementptr i8, ptr %pix2, i64 5
388 %7 = load i8, ptr %arrayidx15, align 1
389 %conv16 = zext i8 %7 to i32
390 %sub17 = sub i32 %conv14, %conv16
391 %shl18 = shl i32 %sub17, 16
392 %add19 = add i32 %shl18, %sub12
393 %arrayidx20 = getelementptr i8, ptr %pix1, i64 2
394 %8 = load i8, ptr %arrayidx20, align 1
395 %conv21 = zext i8 %8 to i32
396 %arrayidx22 = getelementptr i8, ptr %pix2, i64 2
397 %9 = load i8, ptr %arrayidx22, align 1
398 %conv23 = zext i8 %9 to i32
399 %sub24 = sub i32 %conv21, %conv23
400 %arrayidx25 = getelementptr i8, ptr %pix1, i64 6
401 %10 = load i8, ptr %arrayidx25, align 1
402 %conv26 = zext i8 %10 to i32
403 %arrayidx27 = getelementptr i8, ptr %pix2, i64 6
404 %11 = load i8, ptr %arrayidx27, align 1
405 %conv28 = zext i8 %11 to i32
406 %sub29 = sub i32 %conv26, %conv28
407 %shl30 = shl i32 %sub29, 16
408 %add31 = add i32 %shl30, %sub24
409 %arrayidx32 = getelementptr i8, ptr %pix1, i64 3
410 %12 = load i8, ptr %arrayidx32, align 1
411 %conv33 = zext i8 %12 to i32
412 %arrayidx34 = getelementptr i8, ptr %pix2, i64 3
413 %13 = load i8, ptr %arrayidx34, align 1
414 %conv35 = zext i8 %13 to i32
415 %sub36 = sub i32 %conv33, %conv35
416 %arrayidx37 = getelementptr i8, ptr %pix1, i64 7
417 %14 = load i8, ptr %arrayidx37, align 1
418 %conv38 = zext i8 %14 to i32
419 %arrayidx39 = getelementptr i8, ptr %pix2, i64 7
420 %15 = load i8, ptr %arrayidx39, align 1
421 %conv40 = zext i8 %15 to i32
422 %sub41 = sub i32 %conv38, %conv40
423 %shl42 = shl i32 %sub41, 16
424 %add43 = add i32 %shl42, %sub36
425 %add44 = add i32 %add19, %add
426 %sub45 = sub i32 %add, %add19
427 %add46 = add i32 %add43, %add31
428 %sub47 = sub i32 %add31, %add43
429 %add48 = add i32 %add46, %add44
430 %sub51 = sub i32 %add44, %add46
431 %add55 = add i32 %sub47, %sub45
432 %sub59 = sub i32 %sub45, %sub47
433 %add.ptr3 = getelementptr i8, ptr %pix1, i64 %idx.ext
434 %add.ptr644 = getelementptr i8, ptr %pix2, i64 %idx.ext63
435 %16 = load i8, ptr %add.ptr3, align 1
436 %conv.1 = zext i8 %16 to i32
437 %17 = load i8, ptr %add.ptr644, align 1
438 %conv2.1 = zext i8 %17 to i32
439 %sub.1 = sub i32 %conv.1, %conv2.1
440 %arrayidx3.1 = getelementptr i8, ptr %add.ptr3, i64 4
441 %18 = load i8, ptr %arrayidx3.1, align 1
442 %conv4.1 = zext i8 %18 to i32
443 %arrayidx5.1 = getelementptr i8, ptr %add.ptr644, i64 4
444 %19 = load i8, ptr %arrayidx5.1, align 1
445 %conv6.1 = zext i8 %19 to i32
446 %sub7.1 = sub i32 %conv4.1, %conv6.1
447 %shl.1 = shl i32 %sub7.1, 16
448 %add.1 = add i32 %shl.1, %sub.1
449 %arrayidx8.1 = getelementptr i8, ptr %add.ptr3, i64 1
450 %20 = load i8, ptr %arrayidx8.1, align 1
451 %conv9.1 = zext i8 %20 to i32
452 %arrayidx10.1 = getelementptr i8, ptr %add.ptr644, i64 1
453 %21 = load i8, ptr %arrayidx10.1, align 1
454 %conv11.1 = zext i8 %21 to i32
455 %sub12.1 = sub i32 %conv9.1, %conv11.1
456 %arrayidx13.1 = getelementptr i8, ptr %add.ptr3, i64 5
457 %22 = load i8, ptr %arrayidx13.1, align 1
458 %conv14.1 = zext i8 %22 to i32
459 %arrayidx15.1 = getelementptr i8, ptr %add.ptr644, i64 5
460 %23 = load i8, ptr %arrayidx15.1, align 1
461 %conv16.1 = zext i8 %23 to i32
462 %sub17.1 = sub i32 %conv14.1, %conv16.1
463 %shl18.1 = shl i32 %sub17.1, 16
464 %add19.1 = add i32 %shl18.1, %sub12.1
465 %arrayidx20.1 = getelementptr i8, ptr %add.ptr3, i64 2
466 %24 = load i8, ptr %arrayidx20.1, align 1
467 %conv21.1 = zext i8 %24 to i32
468 %arrayidx22.1 = getelementptr i8, ptr %add.ptr644, i64 2
469 %25 = load i8, ptr %arrayidx22.1, align 1
470 %conv23.1 = zext i8 %25 to i32
471 %sub24.1 = sub i32 %conv21.1, %conv23.1
472 %arrayidx25.1 = getelementptr i8, ptr %add.ptr3, i64 6
473 %26 = load i8, ptr %arrayidx25.1, align 1
474 %conv26.1 = zext i8 %26 to i32
475 %arrayidx27.1 = getelementptr i8, ptr %add.ptr644, i64 6
476 %27 = load i8, ptr %arrayidx27.1, align 1
477 %conv28.1 = zext i8 %27 to i32
478 %sub29.1 = sub i32 %conv26.1, %conv28.1
479 %shl30.1 = shl i32 %sub29.1, 16
480 %add31.1 = add i32 %shl30.1, %sub24.1
481 %arrayidx32.1 = getelementptr i8, ptr %add.ptr3, i64 3
482 %28 = load i8, ptr %arrayidx32.1, align 1
483 %conv33.1 = zext i8 %28 to i32
484 %arrayidx34.1 = getelementptr i8, ptr %add.ptr644, i64 3
485 %29 = load i8, ptr %arrayidx34.1, align 1
486 %conv35.1 = zext i8 %29 to i32
487 %sub36.1 = sub i32 %conv33.1, %conv35.1
488 %arrayidx37.1 = getelementptr i8, ptr %add.ptr3, i64 7
489 %30 = load i8, ptr %arrayidx37.1, align 1
490 %conv38.1 = zext i8 %30 to i32
491 %arrayidx39.1 = getelementptr i8, ptr %add.ptr644, i64 7
492 %31 = load i8, ptr %arrayidx39.1, align 1
493 %conv40.1 = zext i8 %31 to i32
494 %sub41.1 = sub i32 %conv38.1, %conv40.1
495 %shl42.1 = shl i32 %sub41.1, 16
496 %add43.1 = add i32 %shl42.1, %sub36.1
497 %add44.1 = add i32 %add19.1, %add.1
498 %sub45.1 = sub i32 %add.1, %add19.1
499 %add46.1 = add i32 %add43.1, %add31.1
500 %sub47.1 = sub i32 %add31.1, %add43.1
501 %add48.1 = add i32 %add46.1, %add44.1
502 %sub51.1 = sub i32 %add44.1, %add46.1
503 %add55.1 = add i32 %sub47.1, %sub45.1
504 %sub59.1 = sub i32 %sub45.1, %sub47.1
505 %add.ptr.1 = getelementptr i8, ptr %add.ptr, i64 %idx.ext
506 %add.ptr64.1 = getelementptr i8, ptr %add.ptr64, i64 %idx.ext63
507 %32 = load i8, ptr %add.ptr.1, align 1
508 %conv.2 = zext i8 %32 to i32
509 %33 = load i8, ptr %add.ptr64.1, align 1
510 %conv2.2 = zext i8 %33 to i32
511 %sub.2 = sub i32 %conv.2, %conv2.2
512 %arrayidx3.2 = getelementptr i8, ptr %add.ptr.1, i64 4
513 %34 = load i8, ptr %arrayidx3.2, align 1
514 %conv4.2 = zext i8 %34 to i32
515 %arrayidx5.2 = getelementptr i8, ptr %add.ptr64.1, i64 4
516 %35 = load i8, ptr %arrayidx5.2, align 1
517 %conv6.2 = zext i8 %35 to i32
518 %sub7.2 = sub i32 %conv4.2, %conv6.2
519 %shl.2 = shl i32 %sub7.2, 16
520 %add.2 = add i32 %shl.2, %sub.2
521 %arrayidx8.2 = getelementptr i8, ptr %add.ptr.1, i64 1
522 %36 = load i8, ptr %arrayidx8.2, align 1
523 %conv9.2 = zext i8 %36 to i32
524 %arrayidx10.2 = getelementptr i8, ptr %add.ptr64.1, i64 1
525 %37 = load i8, ptr %arrayidx10.2, align 1
526 %conv11.2 = zext i8 %37 to i32
527 %sub12.2 = sub i32 %conv9.2, %conv11.2
528 %arrayidx13.2 = getelementptr i8, ptr %add.ptr.1, i64 5
529 %38 = load i8, ptr %arrayidx13.2, align 1
530 %conv14.2 = zext i8 %38 to i32
531 %arrayidx15.2 = getelementptr i8, ptr %add.ptr64.1, i64 5
532 %39 = load i8, ptr %arrayidx15.2, align 1
533 %conv16.2 = zext i8 %39 to i32
534 %sub17.2 = sub i32 %conv14.2, %conv16.2
535 %shl18.2 = shl i32 %sub17.2, 16
536 %add19.2 = add i32 %shl18.2, %sub12.2
537 %arrayidx20.2 = getelementptr i8, ptr %add.ptr.1, i64 2
538 %40 = load i8, ptr %arrayidx20.2, align 1
539 %conv21.2 = zext i8 %40 to i32
540 %arrayidx22.2 = getelementptr i8, ptr %add.ptr64.1, i64 2
541 %41 = load i8, ptr %arrayidx22.2, align 1
542 %conv23.2 = zext i8 %41 to i32
543 %sub24.2 = sub i32 %conv21.2, %conv23.2
544 %arrayidx25.2 = getelementptr i8, ptr %add.ptr.1, i64 6
545 %42 = load i8, ptr %arrayidx25.2, align 1
546 %conv26.2 = zext i8 %42 to i32
547 %arrayidx27.2 = getelementptr i8, ptr %add.ptr64.1, i64 6
548 %43 = load i8, ptr %arrayidx27.2, align 1
549 %conv28.2 = zext i8 %43 to i32
550 %sub29.2 = sub i32 %conv26.2, %conv28.2
551 %shl30.2 = shl i32 %sub29.2, 16
552 %add31.2 = add i32 %shl30.2, %sub24.2
553 %arrayidx32.2 = getelementptr i8, ptr %add.ptr.1, i64 3
554 %44 = load i8, ptr %arrayidx32.2, align 1
555 %conv33.2 = zext i8 %44 to i32
556 %arrayidx34.2 = getelementptr i8, ptr %add.ptr64.1, i64 3
557 %45 = load i8, ptr %arrayidx34.2, align 1
558 %conv35.2 = zext i8 %45 to i32
559 %sub36.2 = sub i32 %conv33.2, %conv35.2
560 %arrayidx37.2 = getelementptr i8, ptr %add.ptr.1, i64 7
561 %46 = load i8, ptr %arrayidx37.2, align 1
562 %conv38.2 = zext i8 %46 to i32
563 %arrayidx39.2 = getelementptr i8, ptr %add.ptr64.1, i64 7
564 %47 = load i8, ptr %arrayidx39.2, align 1
565 %conv40.2 = zext i8 %47 to i32
566 %sub41.2 = sub i32 %conv38.2, %conv40.2
567 %shl42.2 = shl i32 %sub41.2, 16
568 %add43.2 = add i32 %shl42.2, %sub36.2
569 %add44.2 = add i32 %add19.2, %add.2
570 %sub45.2 = sub i32 %add.2, %add19.2
571 %add46.2 = add i32 %add43.2, %add31.2
572 %sub47.2 = sub i32 %add31.2, %add43.2
573 %add48.2 = add i32 %add46.2, %add44.2
574 %sub51.2 = sub i32 %add44.2, %add46.2
575 %add55.2 = add i32 %sub47.2, %sub45.2
576 %sub59.2 = sub i32 %sub45.2, %sub47.2
577 %48 = load i8, ptr null, align 1
578 %conv.3 = zext i8 %48 to i32
579 %49 = load i8, ptr null, align 1
580 %conv2.3 = zext i8 %49 to i32
581 %sub.3 = sub i32 %conv.3, %conv2.3
582 %arrayidx3.3 = getelementptr i8, ptr null, i64 4
583 %50 = load i8, ptr %arrayidx3.3, align 1
584 %conv4.3 = zext i8 %50 to i32
585 %arrayidx5.3 = getelementptr i8, ptr null, i64 4
586 %51 = load i8, ptr %arrayidx5.3, align 1
587 %conv6.3 = zext i8 %51 to i32
588 %sub7.3 = sub i32 %conv4.3, %conv6.3
589 %shl.3 = shl i32 %sub7.3, 16
590 %add.3 = add i32 %shl.3, %sub.3
591 %arrayidx8.3 = getelementptr i8, ptr null, i64 1
592 %52 = load i8, ptr %arrayidx8.3, align 1
593 %conv9.3 = zext i8 %52 to i32
594 %arrayidx10.3 = getelementptr i8, ptr null, i64 1
595 %53 = load i8, ptr %arrayidx10.3, align 1
596 %conv11.3 = zext i8 %53 to i32
597 %sub12.3 = sub i32 %conv9.3, %conv11.3
598 %54 = load i8, ptr null, align 1
599 %conv14.3 = zext i8 %54 to i32
600 %arrayidx15.3 = getelementptr i8, ptr null, i64 5
601 %55 = load i8, ptr %arrayidx15.3, align 1
602 %conv16.3 = zext i8 %55 to i32
603 %sub17.3 = sub i32 %conv14.3, %conv16.3
604 %shl18.3 = shl i32 %sub17.3, 16
605 %add19.3 = add i32 %shl18.3, %sub12.3
606 %arrayidx20.3 = getelementptr i8, ptr null, i64 2
607 %56 = load i8, ptr %arrayidx20.3, align 1
608 %conv21.3 = zext i8 %56 to i32
609 %arrayidx22.3 = getelementptr i8, ptr null, i64 2
610 %57 = load i8, ptr %arrayidx22.3, align 1
611 %conv23.3 = zext i8 %57 to i32
612 %sub24.3 = sub i32 %conv21.3, %conv23.3
613 %58 = load i8, ptr null, align 1
614 %conv26.3 = zext i8 %58 to i32
615 %arrayidx27.3 = getelementptr i8, ptr null, i64 6
616 %59 = load i8, ptr %arrayidx27.3, align 1
617 %conv28.3 = zext i8 %59 to i32
618 %sub29.3 = sub i32 %conv26.3, %conv28.3
619 %shl30.3 = shl i32 %sub29.3, 16
620 %add31.3 = add i32 %shl30.3, %sub24.3
621 %arrayidx32.3 = getelementptr i8, ptr null, i64 3
622 %60 = load i8, ptr %arrayidx32.3, align 1
623 %conv33.3 = zext i8 %60 to i32
624 %arrayidx34.3 = getelementptr i8, ptr null, i64 3
625 %61 = load i8, ptr %arrayidx34.3, align 1
626 %conv35.3 = zext i8 %61 to i32
627 %sub36.3 = sub i32 %conv33.3, %conv35.3
628 %62 = load i8, ptr null, align 1
629 %conv38.3 = zext i8 %62 to i32
630 %arrayidx39.3 = getelementptr i8, ptr null, i64 7
631 %63 = load i8, ptr %arrayidx39.3, align 1
632 %conv40.3 = zext i8 %63 to i32
633 %sub41.3 = sub i32 %conv38.3, %conv40.3
634 %shl42.3 = shl i32 %sub41.3, 16
635 %add43.3 = add i32 %shl42.3, %sub36.3
636 %add44.3 = add i32 %add19.3, %add.3
637 %sub45.3 = sub i32 %add.3, %add19.3
638 %add46.3 = add i32 %add43.3, %add31.3
639 %sub47.3 = sub i32 %add31.3, %add43.3
640 %add48.3 = add i32 %add46.3, %add44.3
641 %sub51.3 = sub i32 %add44.3, %add46.3
642 %add55.3 = add i32 %sub47.3, %sub45.3
643 %sub59.3 = sub i32 %sub45.3, %sub47.3
644 %add78 = add i32 %add48.1, %add48
645 %sub86 = sub i32 %add48, %add48.1
646 %add94 = add i32 %add48.3, %add48.2
647 %sub102 = sub i32 %add48.2, %add48.3
648 %add103 = add i32 %add94, %add78
649 %sub104 = sub i32 %add78, %add94
650 %add105 = add i32 %sub102, %sub86
651 %sub106 = sub i32 %sub86, %sub102
652 %shr.i = lshr i32 %conv.3, 15
653 %and.i = and i32 %shr.i, 65537
654 %mul.i = mul i32 %and.i, 65535
655 %add.i = add i32 %mul.i, %add103
656 %xor.i = xor i32 %add.i, %conv.3
657 %shr.i49 = lshr i32 %add46.2, 15
658 %and.i50 = and i32 %shr.i49, 65537
659 %mul.i51 = mul i32 %and.i50, 65535
660 %add.i52 = add i32 %mul.i51, %add105
661 %xor.i53 = xor i32 %add.i52, %add46.2
662 %shr.i54 = lshr i32 %add46.1, 15
663 %and.i55 = and i32 %shr.i54, 65537
664 %mul.i56 = mul i32 %and.i55, 65535
665 %add.i57 = add i32 %mul.i56, %sub104
666 %xor.i58 = xor i32 %add.i57, %add46.1
667 %shr.i59 = lshr i32 %add46, 15
668 %and.i60 = and i32 %shr.i59, 65537
669 %mul.i61 = mul i32 %and.i60, 65535
670 %add.i62 = add i32 %mul.i61, %sub106
671 %xor.i63 = xor i32 %add.i62, %add46
672 %add110 = add i32 %xor.i53, %xor.i
673 %add112 = add i32 %add110, %xor.i58
674 %add113 = add i32 %add112, %xor.i63
675 %add78.1 = add i32 %add55.1, %add55
676 %sub86.1 = sub i32 %add55, %add55.1
677 %add94.1 = add i32 %add55.3, %add55.2
678 %sub102.1 = sub i32 %add55.2, %add55.3
679 %add103.1 = add i32 %add94.1, %add78.1
680 %sub104.1 = sub i32 %add78.1, %add94.1
681 %add105.1 = add i32 %sub102.1, %sub86.1
682 %sub106.1 = sub i32 %sub86.1, %sub102.1
683 %shr.i.1 = lshr i32 %conv9.2, 15
684 %and.i.1 = and i32 %shr.i.1, 65537
685 %mul.i.1 = mul i32 %and.i.1, 65535
686 %add.i.1 = add i32 %mul.i.1, %add103.1
687 %xor.i.1 = xor i32 %add.i.1, %conv9.2
688 %shr.i49.1 = lshr i32 %conv.2, 15
689 %and.i50.1 = and i32 %shr.i49.1, 65537
690 %mul.i51.1 = mul i32 %and.i50.1, 65535
691 %add.i52.1 = add i32 %mul.i51.1, %add105.1
692 %xor.i53.1 = xor i32 %add.i52.1, %conv.2
693 %shr.i54.1 = lshr i32 %sub47.1, 15
694 %and.i55.1 = and i32 %shr.i54.1, 65537
695 %mul.i56.1 = mul i32 %and.i55.1, 65535
696 %add.i57.1 = add i32 %mul.i56.1, %sub104.1
697 %xor.i58.1 = xor i32 %add.i57.1, %sub47.1
698 %shr.i59.1 = lshr i32 %sub47, 15
699 %and.i60.1 = and i32 %shr.i59.1, 65537
700 %mul.i61.1 = mul i32 %and.i60.1, 65535
701 %add.i62.1 = add i32 %mul.i61.1, %sub106.1
702 %xor.i63.1 = xor i32 %add.i62.1, %sub47
703 %add108.1 = add i32 %xor.i53.1, %add113
704 %add110.1 = add i32 %add108.1, %xor.i.1
705 %add112.1 = add i32 %add110.1, %xor.i58.1
706 %add113.1 = add i32 %add112.1, %xor.i63.1
707 %add78.2 = add i32 %sub51.1, %sub51
708 %sub86.2 = sub i32 %sub51, %sub51.1
709 %add94.2 = add i32 %sub51.3, %sub51.2
710 %sub102.2 = sub i32 %sub51.2, %sub51.3
711 %add103.2 = add i32 %add94.2, %add78.2
712 %sub104.2 = sub i32 %add78.2, %add94.2
713 %add105.2 = add i32 %sub102.2, %sub86.2
714 %sub106.2 = sub i32 %sub86.2, %sub102.2
715 %shr.i.2 = lshr i32 %conv9.1, 15
716 %and.i.2 = and i32 %shr.i.2, 65537
717 %mul.i.2 = mul i32 %and.i.2, 65535
718 %add.i.2 = add i32 %mul.i.2, %add103.2
719 %xor.i.2 = xor i32 %add.i.2, %conv9.1
720 %shr.i49.2 = lshr i32 %conv.1, 15
721 %and.i50.2 = and i32 %shr.i49.2, 65537
722 %mul.i51.2 = mul i32 %and.i50.2, 65535
723 %add.i52.2 = add i32 %mul.i51.2, %add105.2
724 %xor.i53.2 = xor i32 %add.i52.2, %conv.1
725 %shr.i54.2 = lshr i32 %conv21.1, 15
726 %and.i55.2 = and i32 %shr.i54.2, 65537
727 %mul.i56.2 = mul i32 %and.i55.2, 65535
728 %add.i57.2 = add i32 %mul.i56.2, %sub104.2
729 %xor.i58.2 = xor i32 %add.i57.2, %conv21.1
730 %shr.i59.2 = lshr i32 %add44, 15
731 %and.i60.2 = and i32 %shr.i59.2, 65537
732 %mul.i61.2 = mul i32 %and.i60.2, 65535
733 %add.i62.2 = add i32 %mul.i61.2, %sub106.2
734 %xor.i63.2 = xor i32 %add.i62.2, %add44
735 %add108.2 = add i32 %xor.i53.2, %add113.1
736 %add110.2 = add i32 %add108.2, %xor.i.2
737 %add112.2 = add i32 %add110.2, %xor.i58.2
738 %add113.2 = add i32 %add112.2, %xor.i63.2
739 %add78.3 = add i32 %sub59.1, %sub59
740 %sub86.3 = sub i32 %sub59, %sub59.1
741 %add94.3 = add i32 %sub59.3, %sub59.2
742 %sub102.3 = sub i32 %sub59.2, %sub59.3
743 %add103.3 = add i32 %add94.3, %add78.3
744 %sub104.3 = sub i32 %add78.3, %add94.3
745 %add105.3 = add i32 %sub102.3, %sub86.3
746 %sub106.3 = sub i32 %sub86.3, %sub102.3
747 %shr.i.3 = lshr i32 %conv9, 15
748 %and.i.3 = and i32 %shr.i.3, 65537
749 %mul.i.3 = mul i32 %and.i.3, 65535
750 %add.i.3 = add i32 %mul.i.3, %add103.3
751 %xor.i.3 = xor i32 %add.i.3, %conv9
752 %shr.i49.3 = lshr i32 %conv, 15
753 %and.i50.3 = and i32 %shr.i49.3, 65537
754 %mul.i51.3 = mul i32 %and.i50.3, 65535
755 %add.i52.3 = add i32 %mul.i51.3, %add105.3
756 %xor.i53.3 = xor i32 %add.i52.3, %conv
757 %shr.i54.3 = lshr i32 %conv21, 15
758 %and.i55.3 = and i32 %shr.i54.3, 65537
759 %mul.i56.3 = mul i32 %and.i55.3, 65535
760 %add.i57.3 = add i32 %mul.i56.3, %sub104.3
761 %xor.i58.3 = xor i32 %add.i57.3, %conv21
762 %shr.i59.3 = lshr i32 %conv33, 15
763 %and.i60.3 = and i32 %shr.i59.3, 65537
764 %mul.i61.3 = mul i32 %and.i60.3, 65535
765 %add.i62.3 = add i32 %mul.i61.3, %sub106.3
766 %xor.i63.3 = xor i32 %add.i62.3, %conv33
767 %add108.3 = add i32 %xor.i53.3, %add113.2
768 %add110.3 = add i32 %add108.3, %xor.i.3
769 %add112.3 = add i32 %add110.3, %xor.i58.3
770 %add113.3 = add i32 %add112.3, %xor.i63.3
771 ret i32 %add113.3
772 }