| blob | c5f72f22580234c06ec6a945739bf2a4c43cd515 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx | FileCheck %s
4 define i32 @crash_reordering_undefs() {
5 ; CHECK-LABEL: @crash_reordering_undefs(
6 ; CHECK-NEXT: entry:
7 ; CHECK-NEXT: [[OR0:%.*]] = or i64 undef, undef
8 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i64 undef, [[OR0]]
9 ; CHECK-NEXT: [[ADD0:%.*]] = select i1 [[CMP0]], i32 65536, i32 65537
10 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 undef, undef
11 ; CHECK-NEXT: [[ADD2:%.*]] = select i1 [[CMP1]], i32 65536, i32 65537
12 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 undef, undef
13 ; CHECK-NEXT: [[ADD4:%.*]] = select i1 [[CMP2]], i32 65536, i32 65537
14 ; CHECK-NEXT: [[OR1:%.*]] = or i64 undef, undef
15 ; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i64 undef, [[OR1]]
16 ; CHECK-NEXT: [[ADD9:%.*]] = select i1 [[CMP3]], i32 65536, i32 65537
17 ; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 undef, [[ADD0]]
18 ; CHECK-NEXT: [[OP_RDX1:%.*]] = add i32 [[ADD2]], [[ADD4]]
19 ; CHECK-NEXT: [[OP_RDX2:%.*]] = add i32 [[OP_RDX]], [[OP_RDX1]]
20 ; CHECK-NEXT: [[OP_RDX3:%.*]] = add i32 [[OP_RDX2]], [[ADD9]]
21 ; CHECK-NEXT: ret i32 [[OP_RDX3]]
22 ;
23 entry:
24 %or0 = or i64 undef, undef
25 %cmp0 = icmp eq i64 undef, %or0
26 %add0 = select i1 %cmp0, i32 65536, i32 65537
27 %add1 = add i32 undef, %add0
28 %cmp1 = icmp eq i64 undef, undef
29 %add2 = select i1 %cmp1, i32 65536, i32 65537
30 %add3 = add i32 %add1, %add2
31 %cmp2 = icmp eq i64 undef, undef
32 %add4 = select i1 %cmp2, i32 65536, i32 65537
33 %add5 = add i32 %add3, %add4
34 %add6 = add i32 %add5, undef
35 %add7 = add i32 %add6, undef
36 %add8 = add i32 %add7, undef
37 %or1 = or i64 undef, undef
38 %cmp3 = icmp eq i64 undef, %or1
39 %add9 = select i1 %cmp3, i32 65536, i32 65537
40 %add10 = add i32 %add8, %add9
41 %add11 = add i32 %add10, undef
42 ret i32 %add11
43 }