1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -S -passes=sroa < %s | FileCheck %s
4 ; Check that SROA can work with target extension types correctly.
6 target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
8 define target("spirv.DeviceEvent") @basic_alloc(target("spirv.DeviceEvent") %arg) {
9 ; CHECK-LABEL: @basic_alloc(
10 ; CHECK-NEXT: ret target("spirv.DeviceEvent") [[ARG:%.*]]
12 %val = alloca target("spirv.DeviceEvent")
13 store target("spirv.DeviceEvent") %arg, ptr %val
14 %ret = load target("spirv.DeviceEvent"), ptr %val
15 ret target("spirv.DeviceEvent") %ret
18 define target("spirv.DeviceEvent") @via_memcpy(target("spirv.DeviceEvent") %arg) {
19 ; CHECK-LABEL: @via_memcpy(
20 ; CHECK-NEXT: ret target("spirv.DeviceEvent") [[ARG:%.*]]
22 %val = alloca target("spirv.DeviceEvent")
23 %bar = alloca target("spirv.DeviceEvent")
24 store target("spirv.DeviceEvent") %arg, ptr %val
25 call void @llvm.memcpy.p0.p0.i64(ptr %bar, ptr %val, i64 8, i1 false)
26 %ret = load target("spirv.DeviceEvent"), ptr %bar
27 ret target("spirv.DeviceEvent") %ret
30 define target("spirv.DeviceEvent") @nobitcast(ptr %arg) {
31 ; CHECK-LABEL: @nobitcast(
32 ; CHECK-NEXT: [[VAL:%.*]] = alloca target("spirv.DeviceEvent"), align 8
33 ; CHECK-NEXT: store ptr [[ARG:%.*]], ptr [[VAL]], align 8
34 ; CHECK-NEXT: [[VAL_0_RET:%.*]] = load target("spirv.DeviceEvent"), ptr [[VAL]], align 8
35 ; CHECK-NEXT: ret target("spirv.DeviceEvent") [[VAL_0_RET]]
37 %val = alloca target("spirv.DeviceEvent")
38 store ptr %arg, ptr %val
39 %ret = load target("spirv.DeviceEvent"), ptr %val
40 ret target("spirv.DeviceEvent") %ret
43 define target("spirv.DeviceEvent") @viai64(target("spirv.DeviceEvent") %arg) {
44 ; CHECK-LABEL: @viai64(
45 ; CHECK-NEXT: [[VAL:%.*]] = alloca target("spirv.DeviceEvent"), align 8
46 ; CHECK-NEXT: [[BAR:%.*]] = alloca target("spirv.DeviceEvent"), align 8
47 ; CHECK-NEXT: store target("spirv.DeviceEvent") [[ARG:%.*]], ptr [[VAL]], align 8
48 ; CHECK-NEXT: [[VAL_0_IMEMCPY:%.*]] = load i64, ptr [[VAL]], align 8
49 ; CHECK-NEXT: store i64 [[VAL_0_IMEMCPY]], ptr [[BAR]], align 8
50 ; CHECK-NEXT: [[BAR_0_RET:%.*]] = load target("spirv.DeviceEvent"), ptr [[BAR]], align 8
51 ; CHECK-NEXT: ret target("spirv.DeviceEvent") [[BAR_0_RET]]
53 %val = alloca target("spirv.DeviceEvent")
54 %bar = alloca target("spirv.DeviceEvent")
55 store target("spirv.DeviceEvent") %arg, ptr %val
56 %imemcpy = load i64, ptr %val
57 store i64 %imemcpy, ptr %bar
58 %ret = load target("spirv.DeviceEvent"), ptr %bar
59 ret target("spirv.DeviceEvent") %ret
62 declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1)