llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

   1 //===- llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp ----------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "llvm/MC/MCRegisterInfo.h"
  10 #include "llvm/MC/MCTargetOptions.h"
  11 #include "llvm/MC/TargetRegistry.h"
  12 #include "llvm/Support/TargetSelect.h"
  13 #include "llvm/Target/TargetMachine.h"
  14 #include "gtest/gtest.h"
  15 #include <mutex>
  16 #include <thread>
  17
  18 using namespace llvm;
  19
  20 std::once_flag flag;
  21
  22 void InitializeAMDGPUTarget() {
  23   std::call_once(flag, []() {
  24     LLVMInitializeAMDGPUTargetInfo();
  25     LLVMInitializeAMDGPUTarget();
  26     LLVMInitializeAMDGPUTargetMC();
  27   });
  28 }
  29
  30 std::unique_ptr<LLVMTargetMachine>
  31 createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
  32   InitializeAMDGPUTarget();
  33
  34   std::string Error;
  35   const Target *T = TargetRegistry::lookupTarget(TStr, Error);
  36   if (!T)
  37     return nullptr;
  38
  39   TargetOptions Options;
  40   return std::unique_ptr<LLVMTargetMachine>(
  41       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
  42           TStr, CPU, FS, Options, std::nullopt, std::nullopt)));
  43 }
  44
  45 TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
  46   for (auto Triple :
  47        {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
  48     auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
  49     if (TM && TM->getMCRegisterInfo()) {
  50       auto MRI = TM->getMCRegisterInfo();
  51       // Wave64 Dwarf register mapping test numbers
  52       // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
  53       // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
  54       // A0 => 3072, A255 => 3327
  55       for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
  56         MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
  57         EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
  58         EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
  59       }
  60     }
  61   }
  62 }
  63
  64 TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
  65   for (auto Triple :
  66        {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
  67     auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
  68     if (TM && TM->getMCRegisterInfo()) {
  69       auto MRI = TM->getMCRegisterInfo();
  70       // Wave32 Dwarf register mapping test numbers
  71       // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
  72       // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
  73       // A0 => 2048, A255 => 2303
  74       for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
  75         MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
  76         EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
  77         EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
  78       }
  79     }
  80   }
  81 }