clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

   1 // REQUIRES: riscv-registered-target
   2
   3 // RUN: %clang_cc1 -triple riscv32 -target-feature +v \
   4 // RUN:     -O2 -emit-llvm %s -o - \
   5 // RUN:     | FileCheck %s
   6 // RUN: %clang_cc1 -triple riscv64 -target-feature +v \
   7 // RUN:     -O2 -emit-llvm %s -o - \
   8 // RUN:     | FileCheck %s
   9
  10 // Test RISC-V V-extension specific inline assembly constraints.
  11 #include <riscv_vector.h>
  12
  13 void test_v_reg() {
  14   asm volatile(
  15       "vsetvli x1, x0, e32,m2,tu,mu\n"
  16       "vadd.vv v1, v2, v3, v0.t"
  17       :
  18       :
  19       : "v1", "x1");
  20 // CHECK-LABEL: define{{.*}} @test_v_reg
  21 // CHECK: "~{v1},~{x1}"
  22 }
  23
  24 vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) {
  25 // CHECK-LABEL: define{{.*}} @test_vr
  26 // CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
  27   vint32m1_t ret;
  28   asm volatile ("vadd.vv %0, %1, %2" : "=vr"(ret) : "vr"(a), "vr"(b));
  29   return ret;
  30 }
  31
  32 vbool1_t test_vm(vbool1_t a, vbool1_t b) {
  33 // CHECK-LABEL: define{{.*}} @test_vm
  34 // CHECK: %0 = tail call <vscale x 64 x i1> asm sideeffect "vmand.mm $0, $1, $2", "=^vm,^vm,^vm"(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
  35   vbool1_t ret;
  36   asm volatile ("vmand.mm %0, %1, %2" : "=vm"(ret) : "vm"(a), "vm"(b));
  37   return ret;
  38 }