Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / clang / test / CodeGen / RISCV / rvb-intrinsics / zbkb.c
blob9be7cc6a0fb7ea0902e98a2ce1275536e85079a6
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkb -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV32ZBKB
5 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
6 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
7 // RUN: | FileCheck %s -check-prefix=RV64ZBKB
9 #include <stdint.h>
11 // RV32ZBKB-LABEL: @brev8_32(
12 // RV32ZBKB-NEXT: entry:
13 // RV32ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
14 // RV32ZBKB-NEXT: ret i32 [[TMP0]]
16 // RV64ZBKB-LABEL: @brev8_32(
17 // RV64ZBKB-NEXT: entry:
18 // RV64ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
19 // RV64ZBKB-NEXT: ret i32 [[TMP0]]
21 uint32_t brev8_32(uint32_t rs1)
23 return __builtin_riscv_brev8_32(rs1);
26 #if __riscv_xlen == 64
27 // RV64ZBKB-LABEL: @brev8_64(
28 // RV64ZBKB-NEXT: entry:
29 // RV64ZBKB-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[RS1:%.*]])
30 // RV64ZBKB-NEXT: ret i64 [[TMP0]]
32 uint64_t brev8_64(uint64_t rs1)
34 return __builtin_riscv_brev8_64(rs1);
36 #endif
38 #if __riscv_xlen == 32
39 // RV32ZBKB-LABEL: @zip(
40 // RV32ZBKB-NEXT: entry:
41 // RV32ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[RS1:%.*]])
42 // RV32ZBKB-NEXT: ret i32 [[TMP0]]
44 uint32_t zip(uint32_t rs1)
46 return __builtin_riscv_zip_32(rs1);
49 // RV32ZBKB-LABEL: @unzip(
50 // RV32ZBKB-NEXT: entry:
51 // RV32ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.unzip.i32(i32 [[RS1:%.*]])
52 // RV32ZBKB-NEXT: ret i32 [[TMP0]]
54 uint32_t unzip(uint32_t rs1)
56 return __builtin_riscv_unzip_32(rs1);
58 #endif