1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV32ZBKC
5 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
6 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
7 // RUN: | FileCheck %s -check-prefix=RV64ZBKC
11 #if __riscv_xlen == 64
12 // RV64ZBKC-LABEL: @clmul_64(
13 // RV64ZBKC-NEXT: entry:
14 // RV64ZBKC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
15 // RV64ZBKC-NEXT: ret i64 [[TMP0]]
17 uint64_t clmul_64(uint64_t a
, uint64_t b
) {
18 return __builtin_riscv_clmul_64(a
, b
);
21 // RV64ZBKC-LABEL: @clmulh_64(
22 // RV64ZBKC-NEXT: entry:
23 // RV64ZBKC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[A:%.*]], i64 [[B:%.*]])
24 // RV64ZBKC-NEXT: ret i64 [[TMP0]]
26 uint64_t clmulh_64(uint64_t a
, uint64_t b
) {
27 return __builtin_riscv_clmulh_64(a
, b
);
31 // RV32ZBKC-LABEL: @clmul_32(
32 // RV32ZBKC-NEXT: entry:
33 // RV32ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
34 // RV32ZBKC-NEXT: ret i32 [[TMP0]]
36 // RV64ZBKC-LABEL: @clmul_32(
37 // RV64ZBKC-NEXT: entry:
38 // RV64ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
39 // RV64ZBKC-NEXT: ret i32 [[TMP0]]
41 uint32_t clmul_32(uint32_t a
, uint32_t b
) {
42 return __builtin_riscv_clmul_32(a
, b
);
45 #if __riscv_xlen == 32
46 // RV32ZBKC-LABEL: @clmulh_32(
47 // RV32ZBKC-NEXT: entry:
48 // RV32ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
49 // RV32ZBKC-NEXT: ret i32 [[TMP0]]
51 uint32_t clmulh_32(uint32_t a
, uint32_t b
) {
52 return __builtin_riscv_clmulh_32(a
, b
);