clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
   4 // RUN:   -target-feature +experimental-zvbb \
   5 // RUN:   -target-feature +experimental-zvbc \
   6 // RUN:   -target-feature +experimental-zvkg \
   7 // RUN:   -target-feature +experimental-zvkned \
   8 // RUN:   -target-feature +experimental-zvknhb \
   9 // RUN:   -target-feature +experimental-zvksed \
  10 // RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
  11 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
  12 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
  13
  14 #include <riscv_vector.h>
  15
  16 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1
  17 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  18 // CHECK-RV64-NEXT:  entry:
  19 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], i64 [[VL]])
  20 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
  21 //
  22 vuint64m1_t test_vclmul_vv_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {
  23   return __riscv_vclmul_vv_u64m1(vs2, vs1, vl);
  24 }
  25
  26 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1
  27 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  28 // CHECK-RV64-NEXT:  entry:
  29 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])
  30 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
  31 //
  32 vuint64m1_t test_vclmul_vx_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
  33   return __riscv_vclmul_vx_u64m1(vs2, rs1, vl);
  34 }
  35
  36 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2
  37 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  38 // CHECK-RV64-NEXT:  entry:
  39 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], i64 [[VL]])
  40 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  41 //
  42 vuint64m2_t test_vclmul_vv_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {
  43   return __riscv_vclmul_vv_u64m2(vs2, vs1, vl);
  44 }
  45
  46 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2
  47 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  48 // CHECK-RV64-NEXT:  entry:
  49 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])
  50 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  51 //
  52 vuint64m2_t test_vclmul_vx_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {
  53   return __riscv_vclmul_vx_u64m2(vs2, rs1, vl);
  54 }
  55
  56 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4
  57 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  58 // CHECK-RV64-NEXT:  entry:
  59 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], i64 [[VL]])
  60 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
  61 //
  62 vuint64m4_t test_vclmul_vv_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
  63   return __riscv_vclmul_vv_u64m4(vs2, vs1, vl);
  64 }
  65
  66 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4
  67 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  68 // CHECK-RV64-NEXT:  entry:
  69 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])
  70 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
  71 //
  72 vuint64m4_t test_vclmul_vx_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {
  73   return __riscv_vclmul_vx_u64m4(vs2, rs1, vl);
  74 }
  75
  76 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8
  77 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  78 // CHECK-RV64-NEXT:  entry:
  79 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], i64 [[VL]])
  80 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
  81 //
  82 vuint64m8_t test_vclmul_vv_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {
  83   return __riscv_vclmul_vv_u64m8(vs2, vs1, vl);
  84 }
  85
  86 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8
  87 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  88 // CHECK-RV64-NEXT:  entry:
  89 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])
  90 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
  91 //
  92 vuint64m8_t test_vclmul_vx_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {
  93   return __riscv_vclmul_vx_u64m8(vs2, rs1, vl);
  94 }
  95
  96 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m
  97 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  98 // CHECK-RV64-NEXT:  entry:
  99 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 100 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 101 //
 102 vuint64m1_t test_vclmul_vv_u64m1_m(vbool64_t mask, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {
 103   return __riscv_vclmul_vv_u64m1_m(mask, vs2, vs1, vl);
 104 }
 105
 106 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m
 107 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 108 // CHECK-RV64-NEXT:  entry:
 109 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 110 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 111 //
 112 vuint64m1_t test_vclmul_vx_u64m1_m(vbool64_t mask, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
 113   return __riscv_vclmul_vx_u64m1_m(mask, vs2, rs1, vl);
 114 }
 115
 116 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_m
 117 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 118 // CHECK-RV64-NEXT:  entry:
 119 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 120 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 121 //
 122 vuint64m2_t test_vclmul_vv_u64m2_m(vbool32_t mask, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {
 123   return __riscv_vclmul_vv_u64m2_m(mask, vs2, vs1, vl);
 124 }
 125
 126 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_m
 127 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 128 // CHECK-RV64-NEXT:  entry:
 129 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 130 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 131 //
 132 vuint64m2_t test_vclmul_vx_u64m2_m(vbool32_t mask, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
 133   return __riscv_vclmul_vx_u64m2_m(mask, vs2, rs1, vl);
 134 }
 135
 136 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_m
 137 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 138 // CHECK-RV64-NEXT:  entry:
 139 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 140 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 141 //
 142 vuint64m4_t test_vclmul_vv_u64m4_m(vbool16_t mask, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
 143   return __riscv_vclmul_vv_u64m4_m(mask, vs2, vs1, vl);
 144 }
 145
 146 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_m
 147 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 148 // CHECK-RV64-NEXT:  entry:
 149 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 150 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 151 //
 152 vuint64m4_t test_vclmul_vx_u64m4_m(vbool16_t mask, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
 153   return __riscv_vclmul_vx_u64m4_m(mask, vs2, rs1, vl);
 154 }
 155
 156 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_m
 157 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 158 // CHECK-RV64-NEXT:  entry:
 159 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 160 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 161 //
 162 vuint64m8_t test_vclmul_vv_u64m8_m(vbool8_t mask, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {
 163   return __riscv_vclmul_vv_u64m8_m(mask, vs2, vs1, vl);
 164 }
 165
 166 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_m
 167 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 168 // CHECK-RV64-NEXT:  entry:
 169 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 170 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 171 //
 172 vuint64m8_t test_vclmul_vx_u64m8_m(vbool8_t mask, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
 173   return __riscv_vclmul_vx_u64m8_m(mask, vs2, rs1, vl);
 174 }
 175