clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
   4 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   5 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   6
   7 #include <riscv_vector.h>
   8
   9 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vlm_v_b1
  10 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  11 // CHECK-RV64-NEXT:  entry:
  12 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.i64(ptr [[BASE]], i64 [[VL]])
  13 // CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
  14 //
  15 vbool1_t test_vlm_v_b1(const uint8_t *base, size_t vl) {
  16   return __riscv_vlm_v_b1(base, vl);
  17 }
  18
  19 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vlm_v_b2
  20 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  21 // CHECK-RV64-NEXT:  entry:
  22 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.i64(ptr [[BASE]], i64 [[VL]])
  23 // CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
  24 //
  25 vbool2_t test_vlm_v_b2(const uint8_t *base, size_t vl) {
  26   return __riscv_vlm_v_b2(base, vl);
  27 }
  28
  29 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vlm_v_b4
  30 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  31 // CHECK-RV64-NEXT:  entry:
  32 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.i64(ptr [[BASE]], i64 [[VL]])
  33 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
  34 //
  35 vbool4_t test_vlm_v_b4(const uint8_t *base, size_t vl) {
  36   return __riscv_vlm_v_b4(base, vl);
  37 }
  38
  39 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vlm_v_b8
  40 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  41 // CHECK-RV64-NEXT:  entry:
  42 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.i64(ptr [[BASE]], i64 [[VL]])
  43 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
  44 //
  45 vbool8_t test_vlm_v_b8(const uint8_t *base, size_t vl) {
  46   return __riscv_vlm_v_b8(base, vl);
  47 }
  48
  49 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vlm_v_b16
  50 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  51 // CHECK-RV64-NEXT:  entry:
  52 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.i64(ptr [[BASE]], i64 [[VL]])
  53 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
  54 //
  55 vbool16_t test_vlm_v_b16(const uint8_t *base, size_t vl) {
  56   return __riscv_vlm_v_b16(base, vl);
  57 }
  58
  59 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vlm_v_b32
  60 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  61 // CHECK-RV64-NEXT:  entry:
  62 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.i64(ptr [[BASE]], i64 [[VL]])
  63 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
  64 //
  65 vbool32_t test_vlm_v_b32(const uint8_t *base, size_t vl) {
  66   return __riscv_vlm_v_b32(base, vl);
  67 }
  68
  69 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vlm_v_b64
  70 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  71 // CHECK-RV64-NEXT:  entry:
  72 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.i64(ptr [[BASE]], i64 [[VL]])
  73 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
  74 //
  75 vbool64_t test_vlm_v_b64(const uint8_t *base, size_t vl) {
  76   return __riscv_vlm_v_b64(base, vl);
  77 }
  78