1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
8 #include <riscv_vector.h>
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2
11 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
16 vfloat32mf2_t
test_vlse32_v_f32mf2(const float *base
, ptrdiff_t bstride
, size_t vl
) {
17 return __riscv_vlse32_v_f32mf2(base
, bstride
, vl
);
20 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1
21 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.i64(<vscale x 2 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
26 vfloat32m1_t
test_vlse32_v_f32m1(const float *base
, ptrdiff_t bstride
, size_t vl
) {
27 return __riscv_vlse32_v_f32m1(base
, bstride
, vl
);
30 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2
31 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.i64(<vscale x 4 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
36 vfloat32m2_t
test_vlse32_v_f32m2(const float *base
, ptrdiff_t bstride
, size_t vl
) {
37 return __riscv_vlse32_v_f32m2(base
, bstride
, vl
);
40 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4
41 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.i64(<vscale x 8 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
46 vfloat32m4_t
test_vlse32_v_f32m4(const float *base
, ptrdiff_t bstride
, size_t vl
) {
47 return __riscv_vlse32_v_f32m4(base
, bstride
, vl
);
50 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8
51 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.i64(<vscale x 16 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
56 vfloat32m8_t
test_vlse32_v_f32m8(const float *base
, ptrdiff_t bstride
, size_t vl
) {
57 return __riscv_vlse32_v_f32m8(base
, bstride
, vl
);
60 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2
61 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
66 vint32mf2_t
test_vlse32_v_i32mf2(const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
67 return __riscv_vlse32_v_i32mf2(base
, bstride
, vl
);
70 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1
71 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
76 vint32m1_t
test_vlse32_v_i32m1(const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
77 return __riscv_vlse32_v_i32m1(base
, bstride
, vl
);
80 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2
81 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
86 vint32m2_t
test_vlse32_v_i32m2(const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
87 return __riscv_vlse32_v_i32m2(base
, bstride
, vl
);
90 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4
91 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
96 vint32m4_t
test_vlse32_v_i32m4(const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
97 return __riscv_vlse32_v_i32m4(base
, bstride
, vl
);
100 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8
101 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
106 vint32m8_t
test_vlse32_v_i32m8(const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
107 return __riscv_vlse32_v_i32m8(base
, bstride
, vl
);
110 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2
111 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
116 vuint32mf2_t
test_vlse32_v_u32mf2(const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
117 return __riscv_vlse32_v_u32mf2(base
, bstride
, vl
);
120 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1
121 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
126 vuint32m1_t
test_vlse32_v_u32m1(const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
127 return __riscv_vlse32_v_u32m1(base
, bstride
, vl
);
130 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlse32_v_u32m2
131 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
136 vuint32m2_t
test_vlse32_v_u32m2(const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
137 return __riscv_vlse32_v_u32m2(base
, bstride
, vl
);
140 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlse32_v_u32m4
141 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
146 vuint32m4_t
test_vlse32_v_u32m4(const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
147 return __riscv_vlse32_v_u32m4(base
, bstride
, vl
);
150 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlse32_v_u32m8
151 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
156 vuint32m8_t
test_vlse32_v_u32m8(const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
157 return __riscv_vlse32_v_u32m8(base
, bstride
, vl
);
160 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_m
161 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
164 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
166 vfloat32mf2_t
test_vlse32_v_f32mf2_m(vbool64_t mask
, const float *base
, ptrdiff_t bstride
, size_t vl
) {
167 return __riscv_vlse32_v_f32mf2_m(mask
, base
, bstride
, vl
);
170 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_m
171 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.i64(<vscale x 2 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
174 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
176 vfloat32m1_t
test_vlse32_v_f32m1_m(vbool32_t mask
, const float *base
, ptrdiff_t bstride
, size_t vl
) {
177 return __riscv_vlse32_v_f32m1_m(mask
, base
, bstride
, vl
);
180 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_m
181 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.i64(<vscale x 4 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
184 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
186 vfloat32m2_t
test_vlse32_v_f32m2_m(vbool16_t mask
, const float *base
, ptrdiff_t bstride
, size_t vl
) {
187 return __riscv_vlse32_v_f32m2_m(mask
, base
, bstride
, vl
);
190 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_m
191 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.i64(<vscale x 8 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
194 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
196 vfloat32m4_t
test_vlse32_v_f32m4_m(vbool8_t mask
, const float *base
, ptrdiff_t bstride
, size_t vl
) {
197 return __riscv_vlse32_v_f32m4_m(mask
, base
, bstride
, vl
);
200 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_m
201 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.i64(<vscale x 16 x float> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
204 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
206 vfloat32m8_t
test_vlse32_v_f32m8_m(vbool4_t mask
, const float *base
, ptrdiff_t bstride
, size_t vl
) {
207 return __riscv_vlse32_v_f32m8_m(mask
, base
, bstride
, vl
);
210 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_m
211 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
214 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
216 vint32mf2_t
test_vlse32_v_i32mf2_m(vbool64_t mask
, const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
217 return __riscv_vlse32_v_i32mf2_m(mask
, base
, bstride
, vl
);
220 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_m
221 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i64(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
224 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
226 vint32m1_t
test_vlse32_v_i32m1_m(vbool32_t mask
, const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
227 return __riscv_vlse32_v_i32m1_m(mask
, base
, bstride
, vl
);
230 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_m
231 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i64(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
234 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
236 vint32m2_t
test_vlse32_v_i32m2_m(vbool16_t mask
, const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
237 return __riscv_vlse32_v_i32m2_m(mask
, base
, bstride
, vl
);
240 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_m
241 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i64(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
244 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
246 vint32m4_t
test_vlse32_v_i32m4_m(vbool8_t mask
, const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
247 return __riscv_vlse32_v_i32m4_m(mask
, base
, bstride
, vl
);
250 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8_m
251 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
252 // CHECK-RV64-NEXT: entry:
253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i64(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
254 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
256 vint32m8_t
test_vlse32_v_i32m8_m(vbool4_t mask
, const int32_t *base
, ptrdiff_t bstride
, size_t vl
) {
257 return __riscv_vlse32_v_i32m8_m(mask
, base
, bstride
, vl
);
260 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2_m
261 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
262 // CHECK-RV64-NEXT: entry:
263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
264 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
266 vuint32mf2_t
test_vlse32_v_u32mf2_m(vbool64_t mask
, const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
267 return __riscv_vlse32_v_u32mf2_m(mask
, base
, bstride
, vl
);
270 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1_m
271 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i64(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
274 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
276 vuint32m1_t
test_vlse32_v_u32m1_m(vbool32_t mask
, const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
277 return __riscv_vlse32_v_u32m1_m(mask
, base
, bstride
, vl
);
280 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlse32_v_u32m2_m
281 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
282 // CHECK-RV64-NEXT: entry:
283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i64(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
284 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
286 vuint32m2_t
test_vlse32_v_u32m2_m(vbool16_t mask
, const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
287 return __riscv_vlse32_v_u32m2_m(mask
, base
, bstride
, vl
);
290 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlse32_v_u32m4_m
291 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
292 // CHECK-RV64-NEXT: entry:
293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i64(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
294 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
296 vuint32m4_t
test_vlse32_v_u32m4_m(vbool8_t mask
, const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
297 return __riscv_vlse32_v_u32m4_m(mask
, base
, bstride
, vl
);
300 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlse32_v_u32m8_m
301 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
302 // CHECK-RV64-NEXT: entry:
303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i64(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
304 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
306 vuint32m8_t
test_vlse32_v_u32m8_m(vbool4_t mask
, const uint32_t *base
, ptrdiff_t bstride
, size_t vl
) {
307 return __riscv_vlse32_v_u32m8_m(mask
, base
, bstride
, vl
);