clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
   4 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   5 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   6
   7 #include <riscv_vector.h>
   8
   9 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4
  10 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  11 // CHECK-RV64-NEXT:  entry:
  12 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[SRC]], i16 0, i64 [[VL]])
  13 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  14 //
  15 vuint16mf4_t test_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src, size_t vl) {
  16   return __riscv_vwcvtu_x_x_v_u16mf4(src, vl);
  17 }
  18
  19 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2
  20 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  21 // CHECK-RV64-NEXT:  entry:
  22 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[SRC]], i16 0, i64 [[VL]])
  23 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  24 //
  25 vuint16mf2_t test_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src, size_t vl) {
  26   return __riscv_vwcvtu_x_x_v_u16mf2(src, vl);
  27 }
  28
  29 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1
  30 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  31 // CHECK-RV64-NEXT:  entry:
  32 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[SRC]], i16 0, i64 [[VL]])
  33 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  34 //
  35 vuint16m1_t test_vwcvtu_x_x_v_u16m1(vuint8mf2_t src, size_t vl) {
  36   return __riscv_vwcvtu_x_x_v_u16m1(src, vl);
  37 }
  38
  39 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2
  40 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  41 // CHECK-RV64-NEXT:  entry:
  42 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[SRC]], i16 0, i64 [[VL]])
  43 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  44 //
  45 vuint16m2_t test_vwcvtu_x_x_v_u16m2(vuint8m1_t src, size_t vl) {
  46   return __riscv_vwcvtu_x_x_v_u16m2(src, vl);
  47 }
  48
  49 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4
  50 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  51 // CHECK-RV64-NEXT:  entry:
  52 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[SRC]], i16 0, i64 [[VL]])
  53 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
  54 //
  55 vuint16m4_t test_vwcvtu_x_x_v_u16m4(vuint8m2_t src, size_t vl) {
  56   return __riscv_vwcvtu_x_x_v_u16m4(src, vl);
  57 }
  58
  59 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8
  60 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  61 // CHECK-RV64-NEXT:  entry:
  62 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[SRC]], i16 0, i64 [[VL]])
  63 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
  64 //
  65 vuint16m8_t test_vwcvtu_x_x_v_u16m8(vuint8m4_t src, size_t vl) {
  66   return __riscv_vwcvtu_x_x_v_u16m8(src, vl);
  67 }
  68
  69 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2
  70 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  71 // CHECK-RV64-NEXT:  entry:
  72 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[SRC]], i32 0, i64 [[VL]])
  73 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
  74 //
  75 vuint32mf2_t test_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src, size_t vl) {
  76   return __riscv_vwcvtu_x_x_v_u32mf2(src, vl);
  77 }
  78
  79 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1
  80 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  81 // CHECK-RV64-NEXT:  entry:
  82 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[SRC]], i32 0, i64 [[VL]])
  83 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  84 //
  85 vuint32m1_t test_vwcvtu_x_x_v_u32m1(vuint16mf2_t src, size_t vl) {
  86   return __riscv_vwcvtu_x_x_v_u32m1(src, vl);
  87 }
  88
  89 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2
  90 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  91 // CHECK-RV64-NEXT:  entry:
  92 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[SRC]], i32 0, i64 [[VL]])
  93 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  94 //
  95 vuint32m2_t test_vwcvtu_x_x_v_u32m2(vuint16m1_t src, size_t vl) {
  96   return __riscv_vwcvtu_x_x_v_u32m2(src, vl);
  97 }
  98
  99 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4
 100 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 101 // CHECK-RV64-NEXT:  entry:
 102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[SRC]], i32 0, i64 [[VL]])
 103 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 104 //
 105 vuint32m4_t test_vwcvtu_x_x_v_u32m4(vuint16m2_t src, size_t vl) {
 106   return __riscv_vwcvtu_x_x_v_u32m4(src, vl);
 107 }
 108
 109 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8
 110 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 111 // CHECK-RV64-NEXT:  entry:
 112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[SRC]], i32 0, i64 [[VL]])
 113 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 114 //
 115 vuint32m8_t test_vwcvtu_x_x_v_u32m8(vuint16m4_t src, size_t vl) {
 116   return __riscv_vwcvtu_x_x_v_u32m8(src, vl);
 117 }
 118
 119 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1
 120 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 121 // CHECK-RV64-NEXT:  entry:
 122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])
 123 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 124 //
 125 vuint64m1_t test_vwcvtu_x_x_v_u64m1(vuint32mf2_t src, size_t vl) {
 126   return __riscv_vwcvtu_x_x_v_u64m1(src, vl);
 127 }
 128
 129 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64m2
 130 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 131 // CHECK-RV64-NEXT:  entry:
 132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])
 133 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 134 //
 135 vuint64m2_t test_vwcvtu_x_x_v_u64m2(vuint32m1_t src, size_t vl) {
 136   return __riscv_vwcvtu_x_x_v_u64m2(src, vl);
 137 }
 138
 139 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwcvtu_x_x_v_u64m4
 140 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 141 // CHECK-RV64-NEXT:  entry:
 142 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])
 143 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 144 //
 145 vuint64m4_t test_vwcvtu_x_x_v_u64m4(vuint32m2_t src, size_t vl) {
 146   return __riscv_vwcvtu_x_x_v_u64m4(src, vl);
 147 }
 148
 149 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwcvtu_x_x_v_u64m8
 150 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 151 // CHECK-RV64-NEXT:  entry:
 152 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.nxv8i64.nxv8i32.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])
 153 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 154 //
 155 vuint64m8_t test_vwcvtu_x_x_v_u64m8(vuint32m4_t src, size_t vl) {
 156   return __riscv_vwcvtu_x_x_v_u64m8(src, vl);
 157 }
 158
 159 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_m
 160 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 161 // CHECK-RV64-NEXT:  entry:
 162 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[SRC]], i16 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 163 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 164 //
 165 vuint16mf4_t test_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask, vuint8mf8_t src, size_t vl) {
 166   return __riscv_vwcvtu_x_x_v_u16mf4_m(mask, src, vl);
 167 }
 168
 169 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_m
 170 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 171 // CHECK-RV64-NEXT:  entry:
 172 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[SRC]], i16 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 173 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 174 //
 175 vuint16mf2_t test_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask, vuint8mf4_t src, size_t vl) {
 176   return __riscv_vwcvtu_x_x_v_u16mf2_m(mask, src, vl);
 177 }
 178
 179 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_m
 180 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 181 // CHECK-RV64-NEXT:  entry:
 182 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[SRC]], i16 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 183 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 184 //
 185 vuint16m1_t test_vwcvtu_x_x_v_u16m1_m(vbool16_t mask, vuint8mf2_t src, size_t vl) {
 186   return __riscv_vwcvtu_x_x_v_u16m1_m(mask, src, vl);
 187 }
 188
 189 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_m
 190 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 191 // CHECK-RV64-NEXT:  entry:
 192 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[SRC]], i16 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 193 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 194 //
 195 vuint16m2_t test_vwcvtu_x_x_v_u16m2_m(vbool8_t mask, vuint8m1_t src, size_t vl) {
 196   return __riscv_vwcvtu_x_x_v_u16m2_m(mask, src, vl);
 197 }
 198
 199 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_m
 200 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 201 // CHECK-RV64-NEXT:  entry:
 202 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[SRC]], i16 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
 203 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 204 //
 205 vuint16m4_t test_vwcvtu_x_x_v_u16m4_m(vbool4_t mask, vuint8m2_t src, size_t vl) {
 206   return __riscv_vwcvtu_x_x_v_u16m4_m(mask, src, vl);
 207 }
 208
 209 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_m
 210 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 211 // CHECK-RV64-NEXT:  entry:
 212 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[SRC]], i16 0, <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
 213 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 214 //
 215 vuint16m8_t test_vwcvtu_x_x_v_u16m8_m(vbool2_t mask, vuint8m4_t src, size_t vl) {
 216   return __riscv_vwcvtu_x_x_v_u16m8_m(mask, src, vl);
 217 }
 218
 219 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_m
 220 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 221 // CHECK-RV64-NEXT:  entry:
 222 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[SRC]], i32 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 223 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 224 //
 225 vuint32mf2_t test_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask, vuint16mf4_t src, size_t vl) {
 226   return __riscv_vwcvtu_x_x_v_u32mf2_m(mask, src, vl);
 227 }
 228
 229 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_m
 230 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 231 // CHECK-RV64-NEXT:  entry:
 232 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[SRC]], i32 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 233 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 234 //
 235 vuint32m1_t test_vwcvtu_x_x_v_u32m1_m(vbool32_t mask, vuint16mf2_t src, size_t vl) {
 236   return __riscv_vwcvtu_x_x_v_u32m1_m(mask, src, vl);
 237 }
 238
 239 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_m
 240 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 241 // CHECK-RV64-NEXT:  entry:
 242 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[SRC]], i32 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 243 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 244 //
 245 vuint32m2_t test_vwcvtu_x_x_v_u32m2_m(vbool16_t mask, vuint16m1_t src, size_t vl) {
 246   return __riscv_vwcvtu_x_x_v_u32m2_m(mask, src, vl);
 247 }
 248
 249 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_m
 250 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 251 // CHECK-RV64-NEXT:  entry:
 252 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[SRC]], i32 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 253 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 254 //
 255 vuint32m4_t test_vwcvtu_x_x_v_u32m4_m(vbool8_t mask, vuint16m2_t src, size_t vl) {
 256   return __riscv_vwcvtu_x_x_v_u32m4_m(mask, src, vl);
 257 }
 258
 259 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8_m
 260 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 261 // CHECK-RV64-NEXT:  entry:
 262 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[SRC]], i32 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
 263 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 264 //
 265 vuint32m8_t test_vwcvtu_x_x_v_u32m8_m(vbool4_t mask, vuint16m4_t src, size_t vl) {
 266   return __riscv_vwcvtu_x_x_v_u32m8_m(mask, src, vl);
 267 }
 268
 269 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1_m
 270 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 271 // CHECK-RV64-NEXT:  entry:
 272 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 273 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 274 //
 275 vuint64m1_t test_vwcvtu_x_x_v_u64m1_m(vbool64_t mask, vuint32mf2_t src, size_t vl) {
 276   return __riscv_vwcvtu_x_x_v_u64m1_m(mask, src, vl);
 277 }
 278
 279 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64m2_m
 280 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 281 // CHECK-RV64-NEXT:  entry:
 282 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 283 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 284 //
 285 vuint64m2_t test_vwcvtu_x_x_v_u64m2_m(vbool32_t mask, vuint32m1_t src, size_t vl) {
 286   return __riscv_vwcvtu_x_x_v_u64m2_m(mask, src, vl);
 287 }
 288
 289 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwcvtu_x_x_v_u64m4_m
 290 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 291 // CHECK-RV64-NEXT:  entry:
 292 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 293 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 294 //
 295 vuint64m4_t test_vwcvtu_x_x_v_u64m4_m(vbool16_t mask, vuint32m2_t src, size_t vl) {
 296   return __riscv_vwcvtu_x_x_v_u64m4_m(mask, src, vl);
 297 }
 298
 299 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwcvtu_x_x_v_u64m8_m
 300 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 301 // CHECK-RV64-NEXT:  entry:
 302 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 303 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 304 //
 305 vuint64m8_t test_vwcvtu_x_x_v_u64m8_m(vbool8_t mask, vuint32m4_t src, size_t vl) {
 306   return __riscv_vwcvtu_x_x_v_u64m8_m(mask, src, vl);
 307 }
 308