clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
   4 // RUN:   -target-feature +zvfh -disable-O0-optnone  \
   5 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   6 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   7
   8 #include <riscv_vector.h>
   9
  10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4
  11 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  12 // CHECK-RV64-NEXT:  entry:
  13 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], i64 [[VL]], i64 3)
  14 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  15 //
  16 vint16mf4_t test_vwmaccus_vx_i16mf4(vint16mf4_t vd, uint8_t rs1, vint8mf8_t vs2, size_t vl) {
  17   return __riscv_vwmaccus_vx_i16mf4(vd, rs1, vs2, vl);
  18 }
  19
  20 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2
  21 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  22 // CHECK-RV64-NEXT:  entry:
  23 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], i64 [[VL]], i64 3)
  24 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  25 //
  26 vint16mf2_t test_vwmaccus_vx_i16mf2(vint16mf2_t vd, uint8_t rs1, vint8mf4_t vs2, size_t vl) {
  27   return __riscv_vwmaccus_vx_i16mf2(vd, rs1, vs2, vl);
  28 }
  29
  30 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1
  31 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  32 // CHECK-RV64-NEXT:  entry:
  33 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
  34 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  35 //
  36 vint16m1_t test_vwmaccus_vx_i16m1(vint16m1_t vd, uint8_t rs1, vint8mf2_t vs2, size_t vl) {
  37   return __riscv_vwmaccus_vx_i16m1(vd, rs1, vs2, vl);
  38 }
  39
  40 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2
  41 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  42 // CHECK-RV64-NEXT:  entry:
  43 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
  44 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  45 //
  46 vint16m2_t test_vwmaccus_vx_i16m2(vint16m2_t vd, uint8_t rs1, vint8m1_t vs2, size_t vl) {
  47   return __riscv_vwmaccus_vx_i16m2(vd, rs1, vs2, vl);
  48 }
  49
  50 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4
  51 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  52 // CHECK-RV64-NEXT:  entry:
  53 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
  54 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
  55 //
  56 vint16m4_t test_vwmaccus_vx_i16m4(vint16m4_t vd, uint8_t rs1, vint8m2_t vs2, size_t vl) {
  57   return __riscv_vwmaccus_vx_i16m4(vd, rs1, vs2, vl);
  58 }
  59
  60 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8
  61 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  62 // CHECK-RV64-NEXT:  entry:
  63 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
  64 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
  65 //
  66 vint16m8_t test_vwmaccus_vx_i16m8(vint16m8_t vd, uint8_t rs1, vint8m4_t vs2, size_t vl) {
  67   return __riscv_vwmaccus_vx_i16m8(vd, rs1, vs2, vl);
  68 }
  69
  70 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2
  71 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  72 // CHECK-RV64-NEXT:  entry:
  73 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], i64 [[VL]], i64 3)
  74 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
  75 //
  76 vint32mf2_t test_vwmaccus_vx_i32mf2(vint32mf2_t vd, uint16_t rs1, vint16mf4_t vs2, size_t vl) {
  77   return __riscv_vwmaccus_vx_i32mf2(vd, rs1, vs2, vl);
  78 }
  79
  80 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1
  81 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  82 // CHECK-RV64-NEXT:  entry:
  83 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], i64 [[VL]], i64 3)
  84 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  85 //
  86 vint32m1_t test_vwmaccus_vx_i32m1(vint32m1_t vd, uint16_t rs1, vint16mf2_t vs2, size_t vl) {
  87   return __riscv_vwmaccus_vx_i32m1(vd, rs1, vs2, vl);
  88 }
  89
  90 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2
  91 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  92 // CHECK-RV64-NEXT:  entry:
  93 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], i64 [[VL]], i64 3)
  94 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  95 //
  96 vint32m2_t test_vwmaccus_vx_i32m2(vint32m2_t vd, uint16_t rs1, vint16m1_t vs2, size_t vl) {
  97   return __riscv_vwmaccus_vx_i32m2(vd, rs1, vs2, vl);
  98 }
  99
 100 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwmaccus_vx_i32m4
 101 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 102 // CHECK-RV64-NEXT:  entry:
 103 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], i64 [[VL]], i64 3)
 104 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 105 //
 106 vint32m4_t test_vwmaccus_vx_i32m4(vint32m4_t vd, uint16_t rs1, vint16m2_t vs2, size_t vl) {
 107   return __riscv_vwmaccus_vx_i32m4(vd, rs1, vs2, vl);
 108 }
 109
 110 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwmaccus_vx_i32m8
 111 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 112 // CHECK-RV64-NEXT:  entry:
 113 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], i64 [[VL]], i64 3)
 114 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 115 //
 116 vint32m8_t test_vwmaccus_vx_i32m8(vint32m8_t vd, uint16_t rs1, vint16m4_t vs2, size_t vl) {
 117   return __riscv_vwmaccus_vx_i32m8(vd, rs1, vs2, vl);
 118 }
 119
 120 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwmaccus_vx_i64m1
 121 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 122 // CHECK-RV64-NEXT:  entry:
 123 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 3)
 124 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 125 //
 126 vint64m1_t test_vwmaccus_vx_i64m1(vint64m1_t vd, uint32_t rs1, vint32mf2_t vs2, size_t vl) {
 127   return __riscv_vwmaccus_vx_i64m1(vd, rs1, vs2, vl);
 128 }
 129
 130 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwmaccus_vx_i64m2
 131 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 132 // CHECK-RV64-NEXT:  entry:
 133 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 3)
 134 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 135 //
 136 vint64m2_t test_vwmaccus_vx_i64m2(vint64m2_t vd, uint32_t rs1, vint32m1_t vs2, size_t vl) {
 137   return __riscv_vwmaccus_vx_i64m2(vd, rs1, vs2, vl);
 138 }
 139
 140 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwmaccus_vx_i64m4
 141 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 142 // CHECK-RV64-NEXT:  entry:
 143 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 3)
 144 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 145 //
 146 vint64m4_t test_vwmaccus_vx_i64m4(vint64m4_t vd, uint32_t rs1, vint32m2_t vs2, size_t vl) {
 147   return __riscv_vwmaccus_vx_i64m4(vd, rs1, vs2, vl);
 148 }
 149
 150 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwmaccus_vx_i64m8
 151 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 152 // CHECK-RV64-NEXT:  entry:
 153 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 3)
 154 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 155 //
 156 vint64m8_t test_vwmaccus_vx_i64m8(vint64m8_t vd, uint32_t rs1, vint32m4_t vs2, size_t vl) {
 157   return __riscv_vwmaccus_vx_i64m8(vd, rs1, vs2, vl);
 158 }
 159
 160 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_m
 161 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 162 // CHECK-RV64-NEXT:  entry:
 163 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 164 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 165 //
 166 vint16mf4_t test_vwmaccus_vx_i16mf4_m(vbool64_t mask, vint16mf4_t vd, uint8_t rs1, vint8mf8_t vs2, size_t vl) {
 167   return __riscv_vwmaccus_vx_i16mf4_m(mask, vd, rs1, vs2, vl);
 168 }
 169
 170 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_m
 171 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 172 // CHECK-RV64-NEXT:  entry:
 173 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 174 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 175 //
 176 vint16mf2_t test_vwmaccus_vx_i16mf2_m(vbool32_t mask, vint16mf2_t vd, uint8_t rs1, vint8mf4_t vs2, size_t vl) {
 177   return __riscv_vwmaccus_vx_i16mf2_m(mask, vd, rs1, vs2, vl);
 178 }
 179
 180 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_m
 181 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 182 // CHECK-RV64-NEXT:  entry:
 183 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 184 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 185 //
 186 vint16m1_t test_vwmaccus_vx_i16m1_m(vbool16_t mask, vint16m1_t vd, uint8_t rs1, vint8mf2_t vs2, size_t vl) {
 187   return __riscv_vwmaccus_vx_i16m1_m(mask, vd, rs1, vs2, vl);
 188 }
 189
 190 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_m
 191 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 192 // CHECK-RV64-NEXT:  entry:
 193 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 194 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 195 //
 196 vint16m2_t test_vwmaccus_vx_i16m2_m(vbool8_t mask, vint16m2_t vd, uint8_t rs1, vint8m1_t vs2, size_t vl) {
 197   return __riscv_vwmaccus_vx_i16m2_m(mask, vd, rs1, vs2, vl);
 198 }
 199
 200 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_m
 201 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 202 // CHECK-RV64-NEXT:  entry:
 203 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
 204 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 205 //
 206 vint16m4_t test_vwmaccus_vx_i16m4_m(vbool4_t mask, vint16m4_t vd, uint8_t rs1, vint8m2_t vs2, size_t vl) {
 207   return __riscv_vwmaccus_vx_i16m4_m(mask, vd, rs1, vs2, vl);
 208 }
 209
 210 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_m
 211 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 212 // CHECK-RV64-NEXT:  entry:
 213 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
 214 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 215 //
 216 vint16m8_t test_vwmaccus_vx_i16m8_m(vbool2_t mask, vint16m8_t vd, uint8_t rs1, vint8m4_t vs2, size_t vl) {
 217   return __riscv_vwmaccus_vx_i16m8_m(mask, vd, rs1, vs2, vl);
 218 }
 219
 220 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_m
 221 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 222 // CHECK-RV64-NEXT:  entry:
 223 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 224 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 225 //
 226 vint32mf2_t test_vwmaccus_vx_i32mf2_m(vbool64_t mask, vint32mf2_t vd, uint16_t rs1, vint16mf4_t vs2, size_t vl) {
 227   return __riscv_vwmaccus_vx_i32mf2_m(mask, vd, rs1, vs2, vl);
 228 }
 229
 230 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_m
 231 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 232 // CHECK-RV64-NEXT:  entry:
 233 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 234 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 235 //
 236 vint32m1_t test_vwmaccus_vx_i32m1_m(vbool32_t mask, vint32m1_t vd, uint16_t rs1, vint16mf2_t vs2, size_t vl) {
 237   return __riscv_vwmaccus_vx_i32m1_m(mask, vd, rs1, vs2, vl);
 238 }
 239
 240 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_m
 241 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 242 // CHECK-RV64-NEXT:  entry:
 243 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 244 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 245 //
 246 vint32m2_t test_vwmaccus_vx_i32m2_m(vbool16_t mask, vint32m2_t vd, uint16_t rs1, vint16m1_t vs2, size_t vl) {
 247   return __riscv_vwmaccus_vx_i32m2_m(mask, vd, rs1, vs2, vl);
 248 }
 249
 250 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwmaccus_vx_i32m4_m
 251 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 252 // CHECK-RV64-NEXT:  entry:
 253 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 254 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 255 //
 256 vint32m4_t test_vwmaccus_vx_i32m4_m(vbool8_t mask, vint32m4_t vd, uint16_t rs1, vint16m2_t vs2, size_t vl) {
 257   return __riscv_vwmaccus_vx_i32m4_m(mask, vd, rs1, vs2, vl);
 258 }
 259
 260 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwmaccus_vx_i32m8_m
 261 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 262 // CHECK-RV64-NEXT:  entry:
 263 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
 264 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 265 //
 266 vint32m8_t test_vwmaccus_vx_i32m8_m(vbool4_t mask, vint32m8_t vd, uint16_t rs1, vint16m4_t vs2, size_t vl) {
 267   return __riscv_vwmaccus_vx_i32m8_m(mask, vd, rs1, vs2, vl);
 268 }
 269
 270 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwmaccus_vx_i64m1_m
 271 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 272 // CHECK-RV64-NEXT:  entry:
 273 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
 274 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 275 //
 276 vint64m1_t test_vwmaccus_vx_i64m1_m(vbool64_t mask, vint64m1_t vd, uint32_t rs1, vint32mf2_t vs2, size_t vl) {
 277   return __riscv_vwmaccus_vx_i64m1_m(mask, vd, rs1, vs2, vl);
 278 }
 279
 280 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwmaccus_vx_i64m2_m
 281 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 282 // CHECK-RV64-NEXT:  entry:
 283 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
 284 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 285 //
 286 vint64m2_t test_vwmaccus_vx_i64m2_m(vbool32_t mask, vint64m2_t vd, uint32_t rs1, vint32m1_t vs2, size_t vl) {
 287   return __riscv_vwmaccus_vx_i64m2_m(mask, vd, rs1, vs2, vl);
 288 }
 289
 290 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwmaccus_vx_i64m4_m
 291 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 292 // CHECK-RV64-NEXT:  entry:
 293 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
 294 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 295 //
 296 vint64m4_t test_vwmaccus_vx_i64m4_m(vbool16_t mask, vint64m4_t vd, uint32_t rs1, vint32m2_t vs2, size_t vl) {
 297   return __riscv_vwmaccus_vx_i64m4_m(mask, vd, rs1, vs2, vl);
 298 }
 299
 300 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwmaccus_vx_i64m8_m
 301 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 302 // CHECK-RV64-NEXT:  entry:
 303 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
 304 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 305 //
 306 vint64m8_t test_vwmaccus_vx_i64m8_m(vbool8_t mask, vint64m8_t vd, uint32_t rs1, vint32m4_t vs2, size_t vl) {
 307   return __riscv_vwmaccus_vx_i64m8_m(mask, vd, rs1, vs2, vl);
 308 }
 309