1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
4 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7 #include <riscv_vector.h>
9 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1
10 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11 // CHECK-RV64-NEXT: entry:
12 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> [[OP1]], i64 [[VL]])
13 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
15 vuint64m1_t
test_vzext_vf8_u64m1(vuint8mf8_t op1
, size_t vl
) {
16 return __riscv_vzext_vf8_u64m1(op1
, vl
);
19 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2
20 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21 // CHECK-RV64-NEXT: entry:
22 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> [[OP1]], i64 [[VL]])
23 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
25 vuint64m2_t
test_vzext_vf8_u64m2(vuint8mf4_t op1
, size_t vl
) {
26 return __riscv_vzext_vf8_u64m2(op1
, vl
);
29 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4
30 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31 // CHECK-RV64-NEXT: entry:
32 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> [[OP1]], i64 [[VL]])
33 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
35 vuint64m4_t
test_vzext_vf8_u64m4(vuint8mf2_t op1
, size_t vl
) {
36 return __riscv_vzext_vf8_u64m4(op1
, vl
);
39 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8
40 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41 // CHECK-RV64-NEXT: entry:
42 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> [[OP1]], i64 [[VL]])
43 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
45 vuint64m8_t
test_vzext_vf8_u64m8(vuint8m1_t op1
, size_t vl
) {
46 return __riscv_vzext_vf8_u64m8(op1
, vl
);
49 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m
50 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51 // CHECK-RV64-NEXT: entry:
52 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
53 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
55 vuint64m1_t
test_vzext_vf8_u64m1_m(vbool64_t mask
, vuint8mf8_t op1
, size_t vl
) {
56 return __riscv_vzext_vf8_u64m1_m(mask
, op1
, vl
);
59 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m
60 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
61 // CHECK-RV64-NEXT: entry:
62 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
63 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
65 vuint64m2_t
test_vzext_vf8_u64m2_m(vbool32_t mask
, vuint8mf4_t op1
, size_t vl
) {
66 return __riscv_vzext_vf8_u64m2_m(mask
, op1
, vl
);
69 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m
70 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
71 // CHECK-RV64-NEXT: entry:
72 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
73 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
75 vuint64m4_t
test_vzext_vf8_u64m4_m(vbool16_t mask
, vuint8mf2_t op1
, size_t vl
) {
76 return __riscv_vzext_vf8_u64m4_m(mask
, op1
, vl
);
79 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m
80 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
81 // CHECK-RV64-NEXT: entry:
82 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
83 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
85 vuint64m8_t
test_vzext_vf8_u64m8_m(vbool8_t mask
, vuint8m1_t op1
, size_t vl
) {
86 return __riscv_vzext_vf8_u64m8_m(mask
, op1
, vl
);