clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
   4 // RUN:   -target-feature +experimental-zvbb \
   5 // RUN:   -target-feature +experimental-zvbc \
   6 // RUN:   -target-feature +experimental-zvkg \
   7 // RUN:   -target-feature +experimental-zvkned \
   8 // RUN:   -target-feature +experimental-zvknhb \
   9 // RUN:   -target-feature +experimental-zvksed \
  10 // RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
  11 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
  12 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
  13
  14 #include <riscv_vector.h>
  15
  16 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu
  17 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  18 // CHECK-RV64-NEXT:  entry:
  19 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)
  20 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
  21 //
  22 vuint32mf2_t test_vaesef_vv_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {
  23   return __riscv_vaesef_vv_tu(vd, vs2, vl);
  24 }
  25
  26 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu
  27 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  28 // CHECK-RV64-NEXT:  entry:
  29 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)
  30 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
  31 //
  32 vuint32mf2_t test_vaesef_vs_u32mf2_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {
  33   return __riscv_vaesef_vs_tu(vd, vs2, vl);
  34 }
  35
  36 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu
  37 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  38 // CHECK-RV64-NEXT:  entry:
  39 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)
  40 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  41 //
  42 vuint32m1_t test_vaesef_vs_u32mf2_u32m1_tu(vuint32m1_t vd, vuint32mf2_t vs2, size_t vl) {
  43   return __riscv_vaesef_vs_tu(vd, vs2, vl);
  44 }
  45
  46 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu
  47 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  48 // CHECK-RV64-NEXT:  entry:
  49 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)
  50 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  51 //
  52 vuint32m2_t test_vaesef_vs_u32mf2_u32m2_tu(vuint32m2_t vd, vuint32mf2_t vs2, size_t vl) {
  53   return __riscv_vaesef_vs_tu(vd, vs2, vl);
  54 }
  55
  56 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu
  57 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  58 // CHECK-RV64-NEXT:  entry:
  59 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)
  60 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
  61 //
  62 vuint32m4_t test_vaesef_vs_u32mf2_u32m4_tu(vuint32m4_t vd, vuint32mf2_t vs2, size_t vl) {
  63   return __riscv_vaesef_vs_tu(vd, vs2, vl);
  64 }
  65
  66 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu
  67 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  68 // CHECK-RV64-NEXT:  entry:
  69 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)
  70 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
  71 //
  72 vuint32m8_t test_vaesef_vs_u32mf2_u32m8_tu(vuint32m8_t vd, vuint32mf2_t vs2, size_t vl) {
  73   return __riscv_vaesef_vs_tu(vd, vs2, vl);
  74 }
  75
  76 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu
  77 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  78 // CHECK-RV64-NEXT:  entry:
  79 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)
  80 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  81 //
  82 vuint32m1_t test_vaesef_vv_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {
  83   return __riscv_vaesef_vv_tu(vd, vs2, vl);
  84 }
  85
  86 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu
  87 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  88 // CHECK-RV64-NEXT:  entry:
  89 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)
  90 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  91 //
  92 vuint32m1_t test_vaesef_vs_u32m1_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {
  93   return __riscv_vaesef_vs_tu(vd, vs2, vl);
  94 }
  95
  96 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu
  97 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  98 // CHECK-RV64-NEXT:  entry:
  99 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)
 100 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 101 //
 102 vuint32m2_t test_vaesef_vs_u32m1_u32m2_tu(vuint32m2_t vd, vuint32m1_t vs2, size_t vl) {
 103   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 104 }
 105
 106 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu
 107 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 108 // CHECK-RV64-NEXT:  entry:
 109 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)
 110 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 111 //
 112 vuint32m4_t test_vaesef_vs_u32m1_u32m4_tu(vuint32m4_t vd, vuint32m1_t vs2, size_t vl) {
 113   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 114 }
 115
 116 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32m1_u32m8_tu
 117 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 118 // CHECK-RV64-NEXT:  entry:
 119 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)
 120 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 121 //
 122 vuint32m8_t test_vaesef_vs_u32m1_u32m8_tu(vuint32m8_t vd, vuint32m1_t vs2, size_t vl) {
 123   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 124 }
 125
 126 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vaesef_vv_u32m2_tu
 127 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 128 // CHECK-RV64-NEXT:  entry:
 129 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vaesef.vv.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)
 130 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 131 //
 132 vuint32m2_t test_vaesef_vv_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {
 133   return __riscv_vaesef_vv_tu(vd, vs2, vl);
 134 }
 135
 136 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m2_u32m2_tu
 137 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 138 // CHECK-RV64-NEXT:  entry:
 139 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)
 140 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 141 //
 142 vuint32m2_t test_vaesef_vs_u32m2_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {
 143   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 144 }
 145
 146 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m2_u32m4_tu
 147 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 148 // CHECK-RV64-NEXT:  entry:
 149 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)
 150 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 151 //
 152 vuint32m4_t test_vaesef_vs_u32m2_u32m4_tu(vuint32m4_t vd, vuint32m2_t vs2, size_t vl) {
 153   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 154 }
 155
 156 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32m2_u32m8_tu
 157 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 158 // CHECK-RV64-NEXT:  entry:
 159 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv4i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)
 160 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 161 //
 162 vuint32m8_t test_vaesef_vs_u32m2_u32m8_tu(vuint32m8_t vd, vuint32m2_t vs2, size_t vl) {
 163   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 164 }
 165
 166 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vaesef_vv_u32m4_tu
 167 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 168 // CHECK-RV64-NEXT:  entry:
 169 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vaesef.vv.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)
 170 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 171 //
 172 vuint32m4_t test_vaesef_vv_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) {
 173   return __riscv_vaesef_vv_tu(vd, vs2, vl);
 174 }
 175
 176 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m4_u32m4_tu
 177 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 178 // CHECK-RV64-NEXT:  entry:
 179 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)
 180 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 181 //
 182 vuint32m4_t test_vaesef_vs_u32m4_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) {
 183   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 184 }
 185
 186 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32m4_u32m8_tu
 187 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 188 // CHECK-RV64-NEXT:  entry:
 189 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)
 190 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 191 //
 192 vuint32m8_t test_vaesef_vs_u32m4_u32m8_tu(vuint32m8_t vd, vuint32m4_t vs2, size_t vl) {
 193   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 194 }
 195
 196 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vaesef_vv_u32m8_tu
 197 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 198 // CHECK-RV64-NEXT:  entry:
 199 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaesef.vv.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 2)
 200 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 201 //
 202 vuint32m8_t test_vaesef_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) {
 203   return __riscv_vaesef_vv_tu(vd, vs2, vl);
 204 }
 205
 206 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32m8_u32m8_tu
 207 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 208 // CHECK-RV64-NEXT:  entry:
 209 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 2)
 210 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 211 //
 212 vuint32m8_t test_vaesef_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) {
 213   return __riscv_vaesef_vs_tu(vd, vs2, vl);
 214 }
 215