clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
   4 // RUN:   -target-feature +zvfh -disable-O0-optnone  \
   5 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   6 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   7
   8 #include <riscv_vector.h>
   9
  10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu
  11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  12 // CHECK-RV64-NEXT:  entry:
  13 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
  14 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
  15 //
  16 vbool64_t test_vmfgt_vv_f16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
  17   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  18 }
  19
  20 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu
  21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  22 // CHECK-RV64-NEXT:  entry:
  23 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
  24 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
  25 //
  26 vbool64_t test_vmfgt_vf_f16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
  27   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  28 }
  29
  30 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu
  31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  32 // CHECK-RV64-NEXT:  entry:
  33 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
  34 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
  35 //
  36 vbool32_t test_vmfgt_vv_f16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
  37   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  38 }
  39
  40 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu
  41 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  42 // CHECK-RV64-NEXT:  entry:
  43 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
  44 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
  45 //
  46 vbool32_t test_vmfgt_vf_f16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
  47   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  48 }
  49
  50 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu
  51 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  52 // CHECK-RV64-NEXT:  entry:
  53 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
  54 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
  55 //
  56 vbool16_t test_vmfgt_vv_f16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
  57   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  58 }
  59
  60 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu
  61 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  62 // CHECK-RV64-NEXT:  entry:
  63 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
  64 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
  65 //
  66 vbool16_t test_vmfgt_vf_f16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
  67   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  68 }
  69
  70 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu
  71 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  72 // CHECK-RV64-NEXT:  entry:
  73 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
  74 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
  75 //
  76 vbool8_t test_vmfgt_vv_f16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
  77   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  78 }
  79
  80 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8_mu
  81 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  82 // CHECK-RV64-NEXT:  entry:
  83 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
  84 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
  85 //
  86 vbool8_t test_vmfgt_vf_f16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
  87   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  88 }
  89
  90 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4_mu
  91 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  92 // CHECK-RV64-NEXT:  entry:
  93 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
  94 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
  95 //
  96 vbool4_t test_vmfgt_vv_f16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
  97   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
  98 }
  99
 100 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4_mu
 101 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 102 // CHECK-RV64-NEXT:  entry:
 103 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
 104 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 105 //
 106 vbool4_t test_vmfgt_vf_f16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
 107   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 108 }
 109
 110 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2_mu
 111 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 112 // CHECK-RV64-NEXT:  entry:
 113 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmfgt.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x half> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
 114 // CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
 115 //
 116 vbool2_t test_vmfgt_vv_f16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
 117   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 118 }
 119
 120 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmfgt_vf_f16m8_b2_mu
 121 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 122 // CHECK-RV64-NEXT:  entry:
 123 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmfgt.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], half [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
 124 // CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
 125 //
 126 vbool2_t test_vmfgt_vf_f16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
 127   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 128 }
 129
 130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f32mf2_b64_mu
 131 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 132 // CHECK-RV64-NEXT:  entry:
 133 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 134 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
 135 //
 136 vbool64_t test_vmfgt_vv_f32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
 137   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 138 }
 139
 140 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f32mf2_b64_mu
 141 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 142 // CHECK-RV64-NEXT:  entry:
 143 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 144 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
 145 //
 146 vbool64_t test_vmfgt_vf_f32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
 147   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 148 }
 149
 150 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f32m1_b32_mu
 151 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 152 // CHECK-RV64-NEXT:  entry:
 153 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 154 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
 155 //
 156 vbool32_t test_vmfgt_vv_f32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
 157   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 158 }
 159
 160 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f32m1_b32_mu
 161 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 162 // CHECK-RV64-NEXT:  entry:
 163 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 164 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
 165 //
 166 vbool32_t test_vmfgt_vf_f32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
 167   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 168 }
 169
 170 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f32m2_b16_mu
 171 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 172 // CHECK-RV64-NEXT:  entry:
 173 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 174 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
 175 //
 176 vbool16_t test_vmfgt_vv_f32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
 177   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 178 }
 179
 180 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f32m2_b16_mu
 181 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 182 // CHECK-RV64-NEXT:  entry:
 183 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 184 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
 185 //
 186 vbool16_t test_vmfgt_vf_f32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
 187   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 188 }
 189
 190 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f32m4_b8_mu
 191 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 192 // CHECK-RV64-NEXT:  entry:
 193 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 194 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
 195 //
 196 vbool8_t test_vmfgt_vv_f32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
 197   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 198 }
 199
 200 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f32m4_b8_mu
 201 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 202 // CHECK-RV64-NEXT:  entry:
 203 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 204 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
 205 //
 206 vbool8_t test_vmfgt_vf_f32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
 207   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 208 }
 209
 210 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f32m8_b4_mu
 211 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 212 // CHECK-RV64-NEXT:  entry:
 213 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x float> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
 214 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 215 //
 216 vbool4_t test_vmfgt_vv_f32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
 217   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 218 }
 219
 220 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f32m8_b4_mu
 221 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 222 // CHECK-RV64-NEXT:  entry:
 223 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f32.f32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], float [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
 224 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 225 //
 226 vbool4_t test_vmfgt_vf_f32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vfloat32m8_t op1, float op2, size_t vl) {
 227   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 228 }
 229
 230 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f64m1_b64_mu
 231 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 232 // CHECK-RV64-NEXT:  entry:
 233 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x double> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 234 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
 235 //
 236 vbool64_t test_vmfgt_vv_f64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
 237   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 238 }
 239
 240 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f64m1_b64_mu
 241 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 242 // CHECK-RV64-NEXT:  entry:
 243 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], double [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 244 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
 245 //
 246 vbool64_t test_vmfgt_vf_f64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vfloat64m1_t op1, double op2, size_t vl) {
 247   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 248 }
 249
 250 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f64m2_b32_mu
 251 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 252 // CHECK-RV64-NEXT:  entry:
 253 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x double> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 254 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
 255 //
 256 vbool32_t test_vmfgt_vv_f64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
 257   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 258 }
 259
 260 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f64m2_b32_mu
 261 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 262 // CHECK-RV64-NEXT:  entry:
 263 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], double [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 264 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
 265 //
 266 vbool32_t test_vmfgt_vf_f64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vfloat64m2_t op1, double op2, size_t vl) {
 267   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 268 }
 269
 270 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f64m4_b16_mu
 271 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 272 // CHECK-RV64-NEXT:  entry:
 273 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x double> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 274 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
 275 //
 276 vbool16_t test_vmfgt_vv_f64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
 277   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 278 }
 279
 280 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f64m4_b16_mu
 281 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 282 // CHECK-RV64-NEXT:  entry:
 283 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], double [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 284 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
 285 //
 286 vbool16_t test_vmfgt_vf_f64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vfloat64m4_t op1, double op2, size_t vl) {
 287   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 288 }
 289
 290 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f64m8_b8_mu
 291 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 292 // CHECK-RV64-NEXT:  entry:
 293 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x double> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 294 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
 295 //
 296 vbool8_t test_vmfgt_vv_f64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
 297   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 298 }
 299
 300 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f64m8_b8_mu
 301 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 302 // CHECK-RV64-NEXT:  entry:
 303 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], double [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 304 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
 305 //
 306 vbool8_t test_vmfgt_vf_f64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
 307   return __riscv_vmfgt_mu(mask, maskedoff, op1, op2, vl);
 308 }
 309