clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
   4 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   5 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   6
   7 #include <riscv_vector.h>
   8
   9 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu
  10 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  11 // CHECK-RV64-NEXT:  entry:
  12 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
  13 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  14 //
  15 vuint16mf4_t test_vwaddu_vv_u16mf4_tu(vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
  16   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
  17 }
  18
  19 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu
  20 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  21 // CHECK-RV64-NEXT:  entry:
  22 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
  23 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  24 //
  25 vuint16mf4_t test_vwaddu_vx_u16mf4_tu(vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
  26   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
  27 }
  28
  29 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu
  30 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  31 // CHECK-RV64-NEXT:  entry:
  32 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
  33 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  34 //
  35 vuint16mf4_t test_vwaddu_wv_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint8mf8_t op2, size_t vl) {
  36   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
  37 }
  38
  39 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu
  40 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  41 // CHECK-RV64-NEXT:  entry:
  42 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])
  43 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  44 //
  45 vuint16mf4_t test_vwaddu_wx_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t op1, uint8_t op2, size_t vl) {
  46   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
  47 }
  48
  49 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu
  50 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  51 // CHECK-RV64-NEXT:  entry:
  52 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
  53 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  54 //
  55 vuint16mf2_t test_vwaddu_vv_u16mf2_tu(vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
  56   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
  57 }
  58
  59 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu
  60 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  61 // CHECK-RV64-NEXT:  entry:
  62 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
  63 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  64 //
  65 vuint16mf2_t test_vwaddu_vx_u16mf2_tu(vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
  66   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
  67 }
  68
  69 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu
  70 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  71 // CHECK-RV64-NEXT:  entry:
  72 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
  73 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  74 //
  75 vuint16mf2_t test_vwaddu_wv_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint8mf4_t op2, size_t vl) {
  76   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
  77 }
  78
  79 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu
  80 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  81 // CHECK-RV64-NEXT:  entry:
  82 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])
  83 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  84 //
  85 vuint16mf2_t test_vwaddu_wx_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t op1, uint8_t op2, size_t vl) {
  86   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
  87 }
  88
  89 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu
  90 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  91 // CHECK-RV64-NEXT:  entry:
  92 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
  93 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  94 //
  95 vuint16m1_t test_vwaddu_vv_u16m1_tu(vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
  96   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
  97 }
  98
  99 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1_tu
 100 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 101 // CHECK-RV64-NEXT:  entry:
 102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
 103 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 104 //
 105 vuint16m1_t test_vwaddu_vx_u16m1_tu(vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
 106   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 107 }
 108
 109 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wv_u16m1_tu
 110 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 111 // CHECK-RV64-NEXT:  entry:
 112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
 113 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 114 //
 115 vuint16m1_t test_vwaddu_wv_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t op1, vuint8mf2_t op2, size_t vl) {
 116   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 117 }
 118
 119 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wx_u16m1_tu
 120 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 121 // CHECK-RV64-NEXT:  entry:
 122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])
 123 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 124 //
 125 vuint16m1_t test_vwaddu_wx_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t op1, uint8_t op2, size_t vl) {
 126   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 127 }
 128
 129 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vv_u16m2_tu
 130 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 131 // CHECK-RV64-NEXT:  entry:
 132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
 133 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 134 //
 135 vuint16m2_t test_vwaddu_vv_u16m2_tu(vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
 136   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 137 }
 138
 139 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vx_u16m2_tu
 140 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 141 // CHECK-RV64-NEXT:  entry:
 142 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
 143 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 144 //
 145 vuint16m2_t test_vwaddu_vx_u16m2_tu(vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
 146   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 147 }
 148
 149 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wv_u16m2_tu
 150 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 151 // CHECK-RV64-NEXT:  entry:
 152 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
 153 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 154 //
 155 vuint16m2_t test_vwaddu_wv_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t op1, vuint8m1_t op2, size_t vl) {
 156   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 157 }
 158
 159 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wx_u16m2_tu
 160 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 161 // CHECK-RV64-NEXT:  entry:
 162 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])
 163 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 164 //
 165 vuint16m2_t test_vwaddu_wx_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t op1, uint8_t op2, size_t vl) {
 166   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 167 }
 168
 169 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vv_u16m4_tu
 170 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 171 // CHECK-RV64-NEXT:  entry:
 172 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
 173 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 174 //
 175 vuint16m4_t test_vwaddu_vv_u16m4_tu(vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
 176   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 177 }
 178
 179 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vx_u16m4_tu
 180 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 181 // CHECK-RV64-NEXT:  entry:
 182 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
 183 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 184 //
 185 vuint16m4_t test_vwaddu_vx_u16m4_tu(vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
 186   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 187 }
 188
 189 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wv_u16m4_tu
 190 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 191 // CHECK-RV64-NEXT:  entry:
 192 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
 193 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 194 //
 195 vuint16m4_t test_vwaddu_wv_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t op1, vuint8m2_t op2, size_t vl) {
 196   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 197 }
 198
 199 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wx_u16m4_tu
 200 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 201 // CHECK-RV64-NEXT:  entry:
 202 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])
 203 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 204 //
 205 vuint16m4_t test_vwaddu_wx_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t op1, uint8_t op2, size_t vl) {
 206   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 207 }
 208
 209 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vv_u16m8_tu
 210 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 211 // CHECK-RV64-NEXT:  entry:
 212 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
 213 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 214 //
 215 vuint16m8_t test_vwaddu_vv_u16m8_tu(vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
 216   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 217 }
 218
 219 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vx_u16m8_tu
 220 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 221 // CHECK-RV64-NEXT:  entry:
 222 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
 223 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 224 //
 225 vuint16m8_t test_vwaddu_vx_u16m8_tu(vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
 226   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 227 }
 228
 229 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wv_u16m8_tu
 230 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 231 // CHECK-RV64-NEXT:  entry:
 232 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
 233 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 234 //
 235 vuint16m8_t test_vwaddu_wv_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t op1, vuint8m4_t op2, size_t vl) {
 236   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 237 }
 238
 239 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wx_u16m8_tu
 240 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 241 // CHECK-RV64-NEXT:  entry:
 242 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])
 243 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 244 //
 245 vuint16m8_t test_vwaddu_wx_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t op1, uint8_t op2, size_t vl) {
 246   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 247 }
 248
 249 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vv_u32mf2_tu
 250 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 251 // CHECK-RV64-NEXT:  entry:
 252 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
 253 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 254 //
 255 vuint32mf2_t test_vwaddu_vv_u32mf2_tu(vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
 256   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 257 }
 258
 259 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vx_u32mf2_tu
 260 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 261 // CHECK-RV64-NEXT:  entry:
 262 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
 263 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 264 //
 265 vuint32mf2_t test_vwaddu_vx_u32mf2_tu(vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
 266   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 267 }
 268
 269 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wv_u32mf2_tu
 270 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 271 // CHECK-RV64-NEXT:  entry:
 272 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
 273 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 274 //
 275 vuint32mf2_t test_vwaddu_wv_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint16mf4_t op2, size_t vl) {
 276   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 277 }
 278
 279 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wx_u32mf2_tu
 280 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 281 // CHECK-RV64-NEXT:  entry:
 282 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])
 283 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 284 //
 285 vuint32mf2_t test_vwaddu_wx_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t op1, uint16_t op2, size_t vl) {
 286   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 287 }
 288
 289 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vv_u32m1_tu
 290 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 291 // CHECK-RV64-NEXT:  entry:
 292 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
 293 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 294 //
 295 vuint32m1_t test_vwaddu_vv_u32m1_tu(vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
 296   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 297 }
 298
 299 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vx_u32m1_tu
 300 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 301 // CHECK-RV64-NEXT:  entry:
 302 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
 303 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 304 //
 305 vuint32m1_t test_vwaddu_vx_u32m1_tu(vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
 306   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 307 }
 308
 309 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wv_u32m1_tu
 310 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 311 // CHECK-RV64-NEXT:  entry:
 312 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
 313 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 314 //
 315 vuint32m1_t test_vwaddu_wv_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t op1, vuint16mf2_t op2, size_t vl) {
 316   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 317 }
 318
 319 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wx_u32m1_tu
 320 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 321 // CHECK-RV64-NEXT:  entry:
 322 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])
 323 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 324 //
 325 vuint32m1_t test_vwaddu_wx_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t op1, uint16_t op2, size_t vl) {
 326   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 327 }
 328
 329 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vv_u32m2_tu
 330 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 331 // CHECK-RV64-NEXT:  entry:
 332 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
 333 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 334 //
 335 vuint32m2_t test_vwaddu_vv_u32m2_tu(vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
 336   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 337 }
 338
 339 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vx_u32m2_tu
 340 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 341 // CHECK-RV64-NEXT:  entry:
 342 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
 343 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 344 //
 345 vuint32m2_t test_vwaddu_vx_u32m2_tu(vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
 346   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 347 }
 348
 349 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wv_u32m2_tu
 350 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 351 // CHECK-RV64-NEXT:  entry:
 352 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
 353 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 354 //
 355 vuint32m2_t test_vwaddu_wv_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t op1, vuint16m1_t op2, size_t vl) {
 356   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 357 }
 358
 359 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wx_u32m2_tu
 360 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 361 // CHECK-RV64-NEXT:  entry:
 362 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])
 363 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 364 //
 365 vuint32m2_t test_vwaddu_wx_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t op1, uint16_t op2, size_t vl) {
 366   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 367 }
 368
 369 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vv_u32m4_tu
 370 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 371 // CHECK-RV64-NEXT:  entry:
 372 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
 373 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 374 //
 375 vuint32m4_t test_vwaddu_vv_u32m4_tu(vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
 376   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 377 }
 378
 379 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vx_u32m4_tu
 380 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 381 // CHECK-RV64-NEXT:  entry:
 382 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
 383 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 384 //
 385 vuint32m4_t test_vwaddu_vx_u32m4_tu(vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
 386   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 387 }
 388
 389 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wv_u32m4_tu
 390 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 391 // CHECK-RV64-NEXT:  entry:
 392 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
 393 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 394 //
 395 vuint32m4_t test_vwaddu_wv_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t op1, vuint16m2_t op2, size_t vl) {
 396   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 397 }
 398
 399 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wx_u32m4_tu
 400 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 401 // CHECK-RV64-NEXT:  entry:
 402 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])
 403 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 404 //
 405 vuint32m4_t test_vwaddu_wx_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t op1, uint16_t op2, size_t vl) {
 406   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 407 }
 408
 409 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vv_u32m8_tu
 410 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 411 // CHECK-RV64-NEXT:  entry:
 412 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
 413 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 414 //
 415 vuint32m8_t test_vwaddu_vv_u32m8_tu(vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
 416   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 417 }
 418
 419 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vx_u32m8_tu
 420 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 421 // CHECK-RV64-NEXT:  entry:
 422 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
 423 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 424 //
 425 vuint32m8_t test_vwaddu_vx_u32m8_tu(vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
 426   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 427 }
 428
 429 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wv_u32m8_tu
 430 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 431 // CHECK-RV64-NEXT:  entry:
 432 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
 433 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 434 //
 435 vuint32m8_t test_vwaddu_wv_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t op1, vuint16m4_t op2, size_t vl) {
 436   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 437 }
 438
 439 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wx_u32m8_tu
 440 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 441 // CHECK-RV64-NEXT:  entry:
 442 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])
 443 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 444 //
 445 vuint32m8_t test_vwaddu_wx_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t op1, uint16_t op2, size_t vl) {
 446   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 447 }
 448
 449 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vv_u64m1_tu
 450 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 451 // CHECK-RV64-NEXT:  entry:
 452 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
 453 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 454 //
 455 vuint64m1_t test_vwaddu_vv_u64m1_tu(vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
 456   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 457 }
 458
 459 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vx_u64m1_tu
 460 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 461 // CHECK-RV64-NEXT:  entry:
 462 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
 463 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 464 //
 465 vuint64m1_t test_vwaddu_vx_u64m1_tu(vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
 466   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 467 }
 468
 469 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wv_u64m1_tu
 470 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 471 // CHECK-RV64-NEXT:  entry:
 472 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
 473 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 474 //
 475 vuint64m1_t test_vwaddu_wv_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t op1, vuint32mf2_t op2, size_t vl) {
 476   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 477 }
 478
 479 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wx_u64m1_tu
 480 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 481 // CHECK-RV64-NEXT:  entry:
 482 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])
 483 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 484 //
 485 vuint64m1_t test_vwaddu_wx_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t op1, uint32_t op2, size_t vl) {
 486   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 487 }
 488
 489 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vv_u64m2_tu
 490 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 491 // CHECK-RV64-NEXT:  entry:
 492 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
 493 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 494 //
 495 vuint64m2_t test_vwaddu_vv_u64m2_tu(vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
 496   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 497 }
 498
 499 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vx_u64m2_tu
 500 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 501 // CHECK-RV64-NEXT:  entry:
 502 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
 503 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 504 //
 505 vuint64m2_t test_vwaddu_vx_u64m2_tu(vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
 506   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 507 }
 508
 509 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wv_u64m2_tu
 510 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 511 // CHECK-RV64-NEXT:  entry:
 512 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
 513 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 514 //
 515 vuint64m2_t test_vwaddu_wv_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t op1, vuint32m1_t op2, size_t vl) {
 516   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 517 }
 518
 519 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wx_u64m2_tu
 520 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 521 // CHECK-RV64-NEXT:  entry:
 522 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])
 523 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 524 //
 525 vuint64m2_t test_vwaddu_wx_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t op1, uint32_t op2, size_t vl) {
 526   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 527 }
 528
 529 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vv_u64m4_tu
 530 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 531 // CHECK-RV64-NEXT:  entry:
 532 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
 533 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 534 //
 535 vuint64m4_t test_vwaddu_vv_u64m4_tu(vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
 536   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 537 }
 538
 539 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vx_u64m4_tu
 540 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 541 // CHECK-RV64-NEXT:  entry:
 542 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
 543 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 544 //
 545 vuint64m4_t test_vwaddu_vx_u64m4_tu(vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
 546   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 547 }
 548
 549 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wv_u64m4_tu
 550 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 551 // CHECK-RV64-NEXT:  entry:
 552 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
 553 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 554 //
 555 vuint64m4_t test_vwaddu_wv_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t op1, vuint32m2_t op2, size_t vl) {
 556   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 557 }
 558
 559 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wx_u64m4_tu
 560 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 561 // CHECK-RV64-NEXT:  entry:
 562 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])
 563 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 564 //
 565 vuint64m4_t test_vwaddu_wx_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t op1, uint32_t op2, size_t vl) {
 566   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 567 }
 568
 569 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vv_u64m8_tu
 570 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 571 // CHECK-RV64-NEXT:  entry:
 572 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
 573 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 574 //
 575 vuint64m8_t test_vwaddu_vv_u64m8_tu(vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
 576   return __riscv_vwaddu_vv_tu(maskedoff, op1, op2, vl);
 577 }
 578
 579 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vx_u64m8_tu
 580 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 581 // CHECK-RV64-NEXT:  entry:
 582 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
 583 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 584 //
 585 vuint64m8_t test_vwaddu_vx_u64m8_tu(vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
 586   return __riscv_vwaddu_vx_tu(maskedoff, op1, op2, vl);
 587 }
 588
 589 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wv_u64m8_tu
 590 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 591 // CHECK-RV64-NEXT:  entry:
 592 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
 593 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 594 //
 595 vuint64m8_t test_vwaddu_wv_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t op1, vuint32m4_t op2, size_t vl) {
 596   return __riscv_vwaddu_wv_tu(maskedoff, op1, op2, vl);
 597 }
 598
 599 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wx_u64m8_tu
 600 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 601 // CHECK-RV64-NEXT:  entry:
 602 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])
 603 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 604 //
 605 vuint64m8_t test_vwaddu_wx_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t op1, uint32_t op2, size_t vl) {
 606   return __riscv_vwaddu_wx_tu(maskedoff, op1, op2, vl);
 607 }
 608
 609 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tum
 610 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 611 // CHECK-RV64-NEXT:  entry:
 612 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 613 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 614 //
 615 vuint16mf4_t test_vwaddu_vv_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
 616   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 617 }
 618
 619 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tum
 620 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 621 // CHECK-RV64-NEXT:  entry:
 622 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 623 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 624 //
 625 vuint16mf4_t test_vwaddu_vx_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
 626   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 627 }
 628
 629 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tum
 630 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 631 // CHECK-RV64-NEXT:  entry:
 632 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 633 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 634 //
 635 vuint16mf4_t test_vwaddu_wv_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint8mf8_t op2, size_t vl) {
 636   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 637 }
 638
 639 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tum
 640 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 641 // CHECK-RV64-NEXT:  entry:
 642 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 643 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 644 //
 645 vuint16mf4_t test_vwaddu_wx_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint8_t op2, size_t vl) {
 646   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 647 }
 648
 649 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tum
 650 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 651 // CHECK-RV64-NEXT:  entry:
 652 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 653 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 654 //
 655 vuint16mf2_t test_vwaddu_vv_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
 656   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 657 }
 658
 659 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tum
 660 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 661 // CHECK-RV64-NEXT:  entry:
 662 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 663 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 664 //
 665 vuint16mf2_t test_vwaddu_vx_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
 666   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 667 }
 668
 669 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tum
 670 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 671 // CHECK-RV64-NEXT:  entry:
 672 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 673 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 674 //
 675 vuint16mf2_t test_vwaddu_wv_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint8mf4_t op2, size_t vl) {
 676   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 677 }
 678
 679 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tum
 680 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 681 // CHECK-RV64-NEXT:  entry:
 682 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 683 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 684 //
 685 vuint16mf2_t test_vwaddu_wx_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint8_t op2, size_t vl) {
 686   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 687 }
 688
 689 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tum
 690 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 691 // CHECK-RV64-NEXT:  entry:
 692 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 693 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 694 //
 695 vuint16m1_t test_vwaddu_vv_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
 696   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 697 }
 698
 699 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1_tum
 700 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 701 // CHECK-RV64-NEXT:  entry:
 702 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 703 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 704 //
 705 vuint16m1_t test_vwaddu_vx_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
 706   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 707 }
 708
 709 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wv_u16m1_tum
 710 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 711 // CHECK-RV64-NEXT:  entry:
 712 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 713 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 714 //
 715 vuint16m1_t test_vwaddu_wv_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint8mf2_t op2, size_t vl) {
 716   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 717 }
 718
 719 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wx_u16m1_tum
 720 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 721 // CHECK-RV64-NEXT:  entry:
 722 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 723 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 724 //
 725 vuint16m1_t test_vwaddu_wx_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint8_t op2, size_t vl) {
 726   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 727 }
 728
 729 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vv_u16m2_tum
 730 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 731 // CHECK-RV64-NEXT:  entry:
 732 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 733 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 734 //
 735 vuint16m2_t test_vwaddu_vv_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
 736   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 737 }
 738
 739 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vx_u16m2_tum
 740 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 741 // CHECK-RV64-NEXT:  entry:
 742 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 743 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 744 //
 745 vuint16m2_t test_vwaddu_vx_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
 746   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 747 }
 748
 749 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wv_u16m2_tum
 750 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 751 // CHECK-RV64-NEXT:  entry:
 752 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 753 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 754 //
 755 vuint16m2_t test_vwaddu_wv_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint8m1_t op2, size_t vl) {
 756   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 757 }
 758
 759 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wx_u16m2_tum
 760 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 761 // CHECK-RV64-NEXT:  entry:
 762 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 763 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 764 //
 765 vuint16m2_t test_vwaddu_wx_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint8_t op2, size_t vl) {
 766   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 767 }
 768
 769 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vv_u16m4_tum
 770 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 771 // CHECK-RV64-NEXT:  entry:
 772 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
 773 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 774 //
 775 vuint16m4_t test_vwaddu_vv_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
 776   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 777 }
 778
 779 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vx_u16m4_tum
 780 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 781 // CHECK-RV64-NEXT:  entry:
 782 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
 783 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 784 //
 785 vuint16m4_t test_vwaddu_vx_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
 786   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 787 }
 788
 789 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wv_u16m4_tum
 790 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 791 // CHECK-RV64-NEXT:  entry:
 792 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
 793 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 794 //
 795 vuint16m4_t test_vwaddu_wv_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint8m2_t op2, size_t vl) {
 796   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 797 }
 798
 799 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wx_u16m4_tum
 800 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 801 // CHECK-RV64-NEXT:  entry:
 802 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
 803 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 804 //
 805 vuint16m4_t test_vwaddu_wx_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint8_t op2, size_t vl) {
 806   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 807 }
 808
 809 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vv_u16m8_tum
 810 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 811 // CHECK-RV64-NEXT:  entry:
 812 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
 813 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 814 //
 815 vuint16m8_t test_vwaddu_vv_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
 816   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 817 }
 818
 819 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vx_u16m8_tum
 820 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 821 // CHECK-RV64-NEXT:  entry:
 822 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
 823 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 824 //
 825 vuint16m8_t test_vwaddu_vx_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
 826   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 827 }
 828
 829 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wv_u16m8_tum
 830 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 831 // CHECK-RV64-NEXT:  entry:
 832 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
 833 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 834 //
 835 vuint16m8_t test_vwaddu_wv_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint8m4_t op2, size_t vl) {
 836   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 837 }
 838
 839 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wx_u16m8_tum
 840 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 841 // CHECK-RV64-NEXT:  entry:
 842 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
 843 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 844 //
 845 vuint16m8_t test_vwaddu_wx_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint8_t op2, size_t vl) {
 846   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 847 }
 848
 849 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vv_u32mf2_tum
 850 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 851 // CHECK-RV64-NEXT:  entry:
 852 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 853 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 854 //
 855 vuint32mf2_t test_vwaddu_vv_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
 856   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 857 }
 858
 859 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vx_u32mf2_tum
 860 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 861 // CHECK-RV64-NEXT:  entry:
 862 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 863 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 864 //
 865 vuint32mf2_t test_vwaddu_vx_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
 866   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 867 }
 868
 869 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wv_u32mf2_tum
 870 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 871 // CHECK-RV64-NEXT:  entry:
 872 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 873 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 874 //
 875 vuint32mf2_t test_vwaddu_wv_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint16mf4_t op2, size_t vl) {
 876   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 877 }
 878
 879 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wx_u32mf2_tum
 880 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 881 // CHECK-RV64-NEXT:  entry:
 882 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 883 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 884 //
 885 vuint32mf2_t test_vwaddu_wx_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint16_t op2, size_t vl) {
 886   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 887 }
 888
 889 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vv_u32m1_tum
 890 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 891 // CHECK-RV64-NEXT:  entry:
 892 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 893 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 894 //
 895 vuint32m1_t test_vwaddu_vv_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
 896   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 897 }
 898
 899 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vx_u32m1_tum
 900 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 901 // CHECK-RV64-NEXT:  entry:
 902 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 903 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 904 //
 905 vuint32m1_t test_vwaddu_vx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
 906   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 907 }
 908
 909 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wv_u32m1_tum
 910 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 911 // CHECK-RV64-NEXT:  entry:
 912 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 913 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 914 //
 915 vuint32m1_t test_vwaddu_wv_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint16mf2_t op2, size_t vl) {
 916   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 917 }
 918
 919 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wx_u32m1_tum
 920 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 921 // CHECK-RV64-NEXT:  entry:
 922 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 923 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 924 //
 925 vuint32m1_t test_vwaddu_wx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint16_t op2, size_t vl) {
 926   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 927 }
 928
 929 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vv_u32m2_tum
 930 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 931 // CHECK-RV64-NEXT:  entry:
 932 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 933 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 934 //
 935 vuint32m2_t test_vwaddu_vv_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
 936   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 937 }
 938
 939 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vx_u32m2_tum
 940 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 941 // CHECK-RV64-NEXT:  entry:
 942 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 943 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 944 //
 945 vuint32m2_t test_vwaddu_vx_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
 946   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 947 }
 948
 949 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wv_u32m2_tum
 950 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 951 // CHECK-RV64-NEXT:  entry:
 952 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 953 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 954 //
 955 vuint32m2_t test_vwaddu_wv_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint16m1_t op2, size_t vl) {
 956   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 957 }
 958
 959 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wx_u32m2_tum
 960 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 961 // CHECK-RV64-NEXT:  entry:
 962 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 963 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 964 //
 965 vuint32m2_t test_vwaddu_wx_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint16_t op2, size_t vl) {
 966   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
 967 }
 968
 969 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vv_u32m4_tum
 970 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 971 // CHECK-RV64-NEXT:  entry:
 972 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 973 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 974 //
 975 vuint32m4_t test_vwaddu_vv_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
 976   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
 977 }
 978
 979 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vx_u32m4_tum
 980 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 981 // CHECK-RV64-NEXT:  entry:
 982 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 983 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 984 //
 985 vuint32m4_t test_vwaddu_vx_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
 986   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
 987 }
 988
 989 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wv_u32m4_tum
 990 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 991 // CHECK-RV64-NEXT:  entry:
 992 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 993 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 994 //
 995 vuint32m4_t test_vwaddu_wv_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint16m2_t op2, size_t vl) {
 996   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
 997 }
 998
 999 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wx_u32m4_tum
1000 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1001 // CHECK-RV64-NEXT:  entry:
1002 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
1003 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
1004 //
1005 vuint32m4_t test_vwaddu_wx_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint16_t op2, size_t vl) {
1006   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
1007 }
1008
1009 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vv_u32m8_tum
1010 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1011 // CHECK-RV64-NEXT:  entry:
1012 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
1013 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1014 //
1015 vuint32m8_t test_vwaddu_vv_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
1016   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
1017 }
1018
1019 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vx_u32m8_tum
1020 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1021 // CHECK-RV64-NEXT:  entry:
1022 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
1023 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1024 //
1025 vuint32m8_t test_vwaddu_vx_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
1026   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
1027 }
1028
1029 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wv_u32m8_tum
1030 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1031 // CHECK-RV64-NEXT:  entry:
1032 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
1033 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1034 //
1035 vuint32m8_t test_vwaddu_wv_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint16m4_t op2, size_t vl) {
1036   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
1037 }
1038
1039 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wx_u32m8_tum
1040 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1041 // CHECK-RV64-NEXT:  entry:
1042 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
1043 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1044 //
1045 vuint32m8_t test_vwaddu_wx_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint16_t op2, size_t vl) {
1046   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
1047 }
1048
1049 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vv_u64m1_tum
1050 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1051 // CHECK-RV64-NEXT:  entry:
1052 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
1053 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1054 //
1055 vuint64m1_t test_vwaddu_vv_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
1056   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
1057 }
1058
1059 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vx_u64m1_tum
1060 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1061 // CHECK-RV64-NEXT:  entry:
1062 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
1063 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1064 //
1065 vuint64m1_t test_vwaddu_vx_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
1066   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
1067 }
1068
1069 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wv_u64m1_tum
1070 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1071 // CHECK-RV64-NEXT:  entry:
1072 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
1073 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1074 //
1075 vuint64m1_t test_vwaddu_wv_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint32mf2_t op2, size_t vl) {
1076   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
1077 }
1078
1079 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wx_u64m1_tum
1080 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1081 // CHECK-RV64-NEXT:  entry:
1082 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
1083 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1084 //
1085 vuint64m1_t test_vwaddu_wx_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint32_t op2, size_t vl) {
1086   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
1087 }
1088
1089 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vv_u64m2_tum
1090 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1091 // CHECK-RV64-NEXT:  entry:
1092 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
1093 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1094 //
1095 vuint64m2_t test_vwaddu_vv_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
1096   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
1097 }
1098
1099 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vx_u64m2_tum
1100 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1101 // CHECK-RV64-NEXT:  entry:
1102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
1103 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1104 //
1105 vuint64m2_t test_vwaddu_vx_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
1106   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
1107 }
1108
1109 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wv_u64m2_tum
1110 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1111 // CHECK-RV64-NEXT:  entry:
1112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
1113 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1114 //
1115 vuint64m2_t test_vwaddu_wv_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint32m1_t op2, size_t vl) {
1116   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
1117 }
1118
1119 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wx_u64m2_tum
1120 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1121 // CHECK-RV64-NEXT:  entry:
1122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
1123 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1124 //
1125 vuint64m2_t test_vwaddu_wx_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint32_t op2, size_t vl) {
1126   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
1127 }
1128
1129 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vv_u64m4_tum
1130 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1131 // CHECK-RV64-NEXT:  entry:
1132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
1133 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1134 //
1135 vuint64m4_t test_vwaddu_vv_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
1136   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
1137 }
1138
1139 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vx_u64m4_tum
1140 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1141 // CHECK-RV64-NEXT:  entry:
1142 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
1143 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1144 //
1145 vuint64m4_t test_vwaddu_vx_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
1146   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
1147 }
1148
1149 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wv_u64m4_tum
1150 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1151 // CHECK-RV64-NEXT:  entry:
1152 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
1153 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1154 //
1155 vuint64m4_t test_vwaddu_wv_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint32m2_t op2, size_t vl) {
1156   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
1157 }
1158
1159 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wx_u64m4_tum
1160 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1161 // CHECK-RV64-NEXT:  entry:
1162 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
1163 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1164 //
1165 vuint64m4_t test_vwaddu_wx_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint32_t op2, size_t vl) {
1166   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
1167 }
1168
1169 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vv_u64m8_tum
1170 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1171 // CHECK-RV64-NEXT:  entry:
1172 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
1173 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1174 //
1175 vuint64m8_t test_vwaddu_vv_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
1176   return __riscv_vwaddu_vv_tum(mask, maskedoff, op1, op2, vl);
1177 }
1178
1179 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vx_u64m8_tum
1180 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1181 // CHECK-RV64-NEXT:  entry:
1182 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
1183 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1184 //
1185 vuint64m8_t test_vwaddu_vx_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
1186   return __riscv_vwaddu_vx_tum(mask, maskedoff, op1, op2, vl);
1187 }
1188
1189 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wv_u64m8_tum
1190 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1191 // CHECK-RV64-NEXT:  entry:
1192 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
1193 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1194 //
1195 vuint64m8_t test_vwaddu_wv_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint32m4_t op2, size_t vl) {
1196   return __riscv_vwaddu_wv_tum(mask, maskedoff, op1, op2, vl);
1197 }
1198
1199 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wx_u64m8_tum
1200 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1201 // CHECK-RV64-NEXT:  entry:
1202 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
1203 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1204 //
1205 vuint64m8_t test_vwaddu_wx_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint32_t op2, size_t vl) {
1206   return __riscv_vwaddu_wx_tum(mask, maskedoff, op1, op2, vl);
1207 }
1208
1209 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tumu
1210 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1211 // CHECK-RV64-NEXT:  entry:
1212 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1213 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1214 //
1215 vuint16mf4_t test_vwaddu_vv_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
1216   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1217 }
1218
1219 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tumu
1220 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1221 // CHECK-RV64-NEXT:  entry:
1222 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1223 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1224 //
1225 vuint16mf4_t test_vwaddu_vx_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
1226   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1227 }
1228
1229 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tumu
1230 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1231 // CHECK-RV64-NEXT:  entry:
1232 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1233 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1234 //
1235 vuint16mf4_t test_vwaddu_wv_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint8mf8_t op2, size_t vl) {
1236   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1237 }
1238
1239 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tumu
1240 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1241 // CHECK-RV64-NEXT:  entry:
1242 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1243 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1244 //
1245 vuint16mf4_t test_vwaddu_wx_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint8_t op2, size_t vl) {
1246   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1247 }
1248
1249 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tumu
1250 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1251 // CHECK-RV64-NEXT:  entry:
1252 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1253 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1254 //
1255 vuint16mf2_t test_vwaddu_vv_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
1256   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1257 }
1258
1259 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tumu
1260 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1261 // CHECK-RV64-NEXT:  entry:
1262 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1263 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1264 //
1265 vuint16mf2_t test_vwaddu_vx_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
1266   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1267 }
1268
1269 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tumu
1270 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1271 // CHECK-RV64-NEXT:  entry:
1272 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1273 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1274 //
1275 vuint16mf2_t test_vwaddu_wv_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint8mf4_t op2, size_t vl) {
1276   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1277 }
1278
1279 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tumu
1280 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1281 // CHECK-RV64-NEXT:  entry:
1282 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1283 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1284 //
1285 vuint16mf2_t test_vwaddu_wx_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint8_t op2, size_t vl) {
1286   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1287 }
1288
1289 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tumu
1290 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1291 // CHECK-RV64-NEXT:  entry:
1292 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1293 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1294 //
1295 vuint16m1_t test_vwaddu_vv_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
1296   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1297 }
1298
1299 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1_tumu
1300 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1301 // CHECK-RV64-NEXT:  entry:
1302 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1303 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1304 //
1305 vuint16m1_t test_vwaddu_vx_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
1306   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1307 }
1308
1309 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wv_u16m1_tumu
1310 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1311 // CHECK-RV64-NEXT:  entry:
1312 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1313 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1314 //
1315 vuint16m1_t test_vwaddu_wv_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint8mf2_t op2, size_t vl) {
1316   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1317 }
1318
1319 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wx_u16m1_tumu
1320 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1321 // CHECK-RV64-NEXT:  entry:
1322 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1323 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1324 //
1325 vuint16m1_t test_vwaddu_wx_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint8_t op2, size_t vl) {
1326   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1327 }
1328
1329 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vv_u16m2_tumu
1330 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1331 // CHECK-RV64-NEXT:  entry:
1332 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1333 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1334 //
1335 vuint16m2_t test_vwaddu_vv_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
1336   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1337 }
1338
1339 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vx_u16m2_tumu
1340 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1341 // CHECK-RV64-NEXT:  entry:
1342 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1343 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1344 //
1345 vuint16m2_t test_vwaddu_vx_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
1346   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1347 }
1348
1349 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wv_u16m2_tumu
1350 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1351 // CHECK-RV64-NEXT:  entry:
1352 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1353 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1354 //
1355 vuint16m2_t test_vwaddu_wv_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint8m1_t op2, size_t vl) {
1356   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1357 }
1358
1359 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wx_u16m2_tumu
1360 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1361 // CHECK-RV64-NEXT:  entry:
1362 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1363 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1364 //
1365 vuint16m2_t test_vwaddu_wx_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint8_t op2, size_t vl) {
1366   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1367 }
1368
1369 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vv_u16m4_tumu
1370 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1371 // CHECK-RV64-NEXT:  entry:
1372 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1373 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1374 //
1375 vuint16m4_t test_vwaddu_vv_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
1376   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1377 }
1378
1379 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vx_u16m4_tumu
1380 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1381 // CHECK-RV64-NEXT:  entry:
1382 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1383 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1384 //
1385 vuint16m4_t test_vwaddu_vx_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
1386   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1387 }
1388
1389 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wv_u16m4_tumu
1390 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1391 // CHECK-RV64-NEXT:  entry:
1392 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1393 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1394 //
1395 vuint16m4_t test_vwaddu_wv_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint8m2_t op2, size_t vl) {
1396   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1397 }
1398
1399 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wx_u16m4_tumu
1400 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1401 // CHECK-RV64-NEXT:  entry:
1402 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1403 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1404 //
1405 vuint16m4_t test_vwaddu_wx_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint8_t op2, size_t vl) {
1406   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1407 }
1408
1409 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vv_u16m8_tumu
1410 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1411 // CHECK-RV64-NEXT:  entry:
1412 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1413 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
1414 //
1415 vuint16m8_t test_vwaddu_vv_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
1416   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1417 }
1418
1419 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vx_u16m8_tumu
1420 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1421 // CHECK-RV64-NEXT:  entry:
1422 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1423 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
1424 //
1425 vuint16m8_t test_vwaddu_vx_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
1426   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1427 }
1428
1429 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wv_u16m8_tumu
1430 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1431 // CHECK-RV64-NEXT:  entry:
1432 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1433 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
1434 //
1435 vuint16m8_t test_vwaddu_wv_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint8m4_t op2, size_t vl) {
1436   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1437 }
1438
1439 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wx_u16m8_tumu
1440 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1441 // CHECK-RV64-NEXT:  entry:
1442 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1443 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
1444 //
1445 vuint16m8_t test_vwaddu_wx_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint8_t op2, size_t vl) {
1446   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1447 }
1448
1449 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vv_u32mf2_tumu
1450 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1451 // CHECK-RV64-NEXT:  entry:
1452 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1453 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
1454 //
1455 vuint32mf2_t test_vwaddu_vv_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
1456   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1457 }
1458
1459 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vx_u32mf2_tumu
1460 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1461 // CHECK-RV64-NEXT:  entry:
1462 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1463 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
1464 //
1465 vuint32mf2_t test_vwaddu_vx_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
1466   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1467 }
1468
1469 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wv_u32mf2_tumu
1470 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1471 // CHECK-RV64-NEXT:  entry:
1472 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1473 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
1474 //
1475 vuint32mf2_t test_vwaddu_wv_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint16mf4_t op2, size_t vl) {
1476   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1477 }
1478
1479 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wx_u32mf2_tumu
1480 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1481 // CHECK-RV64-NEXT:  entry:
1482 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1483 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
1484 //
1485 vuint32mf2_t test_vwaddu_wx_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint16_t op2, size_t vl) {
1486   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1487 }
1488
1489 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vv_u32m1_tumu
1490 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1491 // CHECK-RV64-NEXT:  entry:
1492 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1493 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
1494 //
1495 vuint32m1_t test_vwaddu_vv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
1496   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1497 }
1498
1499 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vx_u32m1_tumu
1500 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1501 // CHECK-RV64-NEXT:  entry:
1502 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1503 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
1504 //
1505 vuint32m1_t test_vwaddu_vx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
1506   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1507 }
1508
1509 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wv_u32m1_tumu
1510 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1511 // CHECK-RV64-NEXT:  entry:
1512 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1513 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
1514 //
1515 vuint32m1_t test_vwaddu_wv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint16mf2_t op2, size_t vl) {
1516   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1517 }
1518
1519 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wx_u32m1_tumu
1520 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1521 // CHECK-RV64-NEXT:  entry:
1522 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1523 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
1524 //
1525 vuint32m1_t test_vwaddu_wx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint16_t op2, size_t vl) {
1526   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1527 }
1528
1529 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vv_u32m2_tumu
1530 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1531 // CHECK-RV64-NEXT:  entry:
1532 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1533 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
1534 //
1535 vuint32m2_t test_vwaddu_vv_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
1536   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1537 }
1538
1539 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vx_u32m2_tumu
1540 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1541 // CHECK-RV64-NEXT:  entry:
1542 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1543 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
1544 //
1545 vuint32m2_t test_vwaddu_vx_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
1546   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1547 }
1548
1549 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wv_u32m2_tumu
1550 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1551 // CHECK-RV64-NEXT:  entry:
1552 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1553 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
1554 //
1555 vuint32m2_t test_vwaddu_wv_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint16m1_t op2, size_t vl) {
1556   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1557 }
1558
1559 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wx_u32m2_tumu
1560 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1561 // CHECK-RV64-NEXT:  entry:
1562 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1563 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
1564 //
1565 vuint32m2_t test_vwaddu_wx_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint16_t op2, size_t vl) {
1566   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1567 }
1568
1569 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vv_u32m4_tumu
1570 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1571 // CHECK-RV64-NEXT:  entry:
1572 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1573 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
1574 //
1575 vuint32m4_t test_vwaddu_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
1576   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1577 }
1578
1579 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vx_u32m4_tumu
1580 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1581 // CHECK-RV64-NEXT:  entry:
1582 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1583 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
1584 //
1585 vuint32m4_t test_vwaddu_vx_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
1586   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1587 }
1588
1589 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wv_u32m4_tumu
1590 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1591 // CHECK-RV64-NEXT:  entry:
1592 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1593 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
1594 //
1595 vuint32m4_t test_vwaddu_wv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint16m2_t op2, size_t vl) {
1596   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1597 }
1598
1599 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wx_u32m4_tumu
1600 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1601 // CHECK-RV64-NEXT:  entry:
1602 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1603 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
1604 //
1605 vuint32m4_t test_vwaddu_wx_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint16_t op2, size_t vl) {
1606   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1607 }
1608
1609 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vv_u32m8_tumu
1610 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1611 // CHECK-RV64-NEXT:  entry:
1612 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1613 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1614 //
1615 vuint32m8_t test_vwaddu_vv_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
1616   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1617 }
1618
1619 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vx_u32m8_tumu
1620 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1621 // CHECK-RV64-NEXT:  entry:
1622 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1623 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1624 //
1625 vuint32m8_t test_vwaddu_vx_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
1626   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1627 }
1628
1629 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wv_u32m8_tumu
1630 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1631 // CHECK-RV64-NEXT:  entry:
1632 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1633 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1634 //
1635 vuint32m8_t test_vwaddu_wv_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint16m4_t op2, size_t vl) {
1636   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1637 }
1638
1639 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wx_u32m8_tumu
1640 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1641 // CHECK-RV64-NEXT:  entry:
1642 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1643 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
1644 //
1645 vuint32m8_t test_vwaddu_wx_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint16_t op2, size_t vl) {
1646   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1647 }
1648
1649 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vv_u64m1_tumu
1650 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1651 // CHECK-RV64-NEXT:  entry:
1652 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1653 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1654 //
1655 vuint64m1_t test_vwaddu_vv_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
1656   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1657 }
1658
1659 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vx_u64m1_tumu
1660 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1661 // CHECK-RV64-NEXT:  entry:
1662 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1663 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1664 //
1665 vuint64m1_t test_vwaddu_vx_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
1666   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1667 }
1668
1669 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wv_u64m1_tumu
1670 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1671 // CHECK-RV64-NEXT:  entry:
1672 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1673 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1674 //
1675 vuint64m1_t test_vwaddu_wv_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint32mf2_t op2, size_t vl) {
1676   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1677 }
1678
1679 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wx_u64m1_tumu
1680 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1681 // CHECK-RV64-NEXT:  entry:
1682 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1683 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
1684 //
1685 vuint64m1_t test_vwaddu_wx_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint32_t op2, size_t vl) {
1686   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1687 }
1688
1689 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vv_u64m2_tumu
1690 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1691 // CHECK-RV64-NEXT:  entry:
1692 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1693 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1694 //
1695 vuint64m2_t test_vwaddu_vv_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
1696   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1697 }
1698
1699 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vx_u64m2_tumu
1700 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1701 // CHECK-RV64-NEXT:  entry:
1702 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1703 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1704 //
1705 vuint64m2_t test_vwaddu_vx_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
1706   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1707 }
1708
1709 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wv_u64m2_tumu
1710 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1711 // CHECK-RV64-NEXT:  entry:
1712 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1713 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1714 //
1715 vuint64m2_t test_vwaddu_wv_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint32m1_t op2, size_t vl) {
1716   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1717 }
1718
1719 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wx_u64m2_tumu
1720 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1721 // CHECK-RV64-NEXT:  entry:
1722 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1723 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
1724 //
1725 vuint64m2_t test_vwaddu_wx_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint32_t op2, size_t vl) {
1726   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1727 }
1728
1729 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vv_u64m4_tumu
1730 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1731 // CHECK-RV64-NEXT:  entry:
1732 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1733 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1734 //
1735 vuint64m4_t test_vwaddu_vv_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
1736   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1737 }
1738
1739 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vx_u64m4_tumu
1740 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1741 // CHECK-RV64-NEXT:  entry:
1742 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1743 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1744 //
1745 vuint64m4_t test_vwaddu_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
1746   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1747 }
1748
1749 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wv_u64m4_tumu
1750 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1751 // CHECK-RV64-NEXT:  entry:
1752 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1753 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1754 //
1755 vuint64m4_t test_vwaddu_wv_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint32m2_t op2, size_t vl) {
1756   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1757 }
1758
1759 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wx_u64m4_tumu
1760 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1761 // CHECK-RV64-NEXT:  entry:
1762 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1763 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
1764 //
1765 vuint64m4_t test_vwaddu_wx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint32_t op2, size_t vl) {
1766   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1767 }
1768
1769 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vv_u64m8_tumu
1770 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1771 // CHECK-RV64-NEXT:  entry:
1772 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1773 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1774 //
1775 vuint64m8_t test_vwaddu_vv_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
1776   return __riscv_vwaddu_vv_tumu(mask, maskedoff, op1, op2, vl);
1777 }
1778
1779 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vx_u64m8_tumu
1780 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1781 // CHECK-RV64-NEXT:  entry:
1782 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1783 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1784 //
1785 vuint64m8_t test_vwaddu_vx_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
1786   return __riscv_vwaddu_vx_tumu(mask, maskedoff, op1, op2, vl);
1787 }
1788
1789 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wv_u64m8_tumu
1790 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1791 // CHECK-RV64-NEXT:  entry:
1792 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1793 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1794 //
1795 vuint64m8_t test_vwaddu_wv_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint32m4_t op2, size_t vl) {
1796   return __riscv_vwaddu_wv_tumu(mask, maskedoff, op1, op2, vl);
1797 }
1798
1799 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wx_u64m8_tumu
1800 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1801 // CHECK-RV64-NEXT:  entry:
1802 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1803 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
1804 //
1805 vuint64m8_t test_vwaddu_wx_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint32_t op2, size_t vl) {
1806   return __riscv_vwaddu_wx_tumu(mask, maskedoff, op1, op2, vl);
1807 }
1808
1809 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_mu
1810 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1811 // CHECK-RV64-NEXT:  entry:
1812 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1813 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1814 //
1815 vuint16mf4_t test_vwaddu_vv_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
1816   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
1817 }
1818
1819 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_mu
1820 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1821 // CHECK-RV64-NEXT:  entry:
1822 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1823 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1824 //
1825 vuint16mf4_t test_vwaddu_vx_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
1826   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
1827 }
1828
1829 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_mu
1830 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1831 // CHECK-RV64-NEXT:  entry:
1832 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1833 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1834 //
1835 vuint16mf4_t test_vwaddu_wv_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint8mf8_t op2, size_t vl) {
1836   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
1837 }
1838
1839 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_mu
1840 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1841 // CHECK-RV64-NEXT:  entry:
1842 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1843 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
1844 //
1845 vuint16mf4_t test_vwaddu_wx_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint8_t op2, size_t vl) {
1846   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
1847 }
1848
1849 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_mu
1850 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1851 // CHECK-RV64-NEXT:  entry:
1852 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1853 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1854 //
1855 vuint16mf2_t test_vwaddu_vv_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
1856   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
1857 }
1858
1859 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_mu
1860 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1861 // CHECK-RV64-NEXT:  entry:
1862 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1863 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1864 //
1865 vuint16mf2_t test_vwaddu_vx_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
1866   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
1867 }
1868
1869 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_mu
1870 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1871 // CHECK-RV64-NEXT:  entry:
1872 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1873 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1874 //
1875 vuint16mf2_t test_vwaddu_wv_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint8mf4_t op2, size_t vl) {
1876   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
1877 }
1878
1879 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_mu
1880 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1881 // CHECK-RV64-NEXT:  entry:
1882 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1883 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
1884 //
1885 vuint16mf2_t test_vwaddu_wx_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint8_t op2, size_t vl) {
1886   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
1887 }
1888
1889 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_mu
1890 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1891 // CHECK-RV64-NEXT:  entry:
1892 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1893 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1894 //
1895 vuint16m1_t test_vwaddu_vv_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
1896   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
1897 }
1898
1899 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1_mu
1900 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1901 // CHECK-RV64-NEXT:  entry:
1902 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1903 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1904 //
1905 vuint16m1_t test_vwaddu_vx_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
1906   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
1907 }
1908
1909 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wv_u16m1_mu
1910 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1911 // CHECK-RV64-NEXT:  entry:
1912 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1913 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1914 //
1915 vuint16m1_t test_vwaddu_wv_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint8mf2_t op2, size_t vl) {
1916   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
1917 }
1918
1919 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wx_u16m1_mu
1920 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1921 // CHECK-RV64-NEXT:  entry:
1922 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1923 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
1924 //
1925 vuint16m1_t test_vwaddu_wx_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint8_t op2, size_t vl) {
1926   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
1927 }
1928
1929 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vv_u16m2_mu
1930 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1931 // CHECK-RV64-NEXT:  entry:
1932 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1933 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1934 //
1935 vuint16m2_t test_vwaddu_vv_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
1936   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
1937 }
1938
1939 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vx_u16m2_mu
1940 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1941 // CHECK-RV64-NEXT:  entry:
1942 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1943 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1944 //
1945 vuint16m2_t test_vwaddu_vx_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
1946   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
1947 }
1948
1949 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wv_u16m2_mu
1950 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1951 // CHECK-RV64-NEXT:  entry:
1952 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1953 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1954 //
1955 vuint16m2_t test_vwaddu_wv_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint8m1_t op2, size_t vl) {
1956   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
1957 }
1958
1959 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wx_u16m2_mu
1960 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1961 // CHECK-RV64-NEXT:  entry:
1962 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1963 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
1964 //
1965 vuint16m2_t test_vwaddu_wx_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint8_t op2, size_t vl) {
1966   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
1967 }
1968
1969 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vv_u16m4_mu
1970 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1971 // CHECK-RV64-NEXT:  entry:
1972 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1973 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1974 //
1975 vuint16m4_t test_vwaddu_vv_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
1976   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
1977 }
1978
1979 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vx_u16m4_mu
1980 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1981 // CHECK-RV64-NEXT:  entry:
1982 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1983 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1984 //
1985 vuint16m4_t test_vwaddu_vx_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
1986   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
1987 }
1988
1989 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wv_u16m4_mu
1990 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1991 // CHECK-RV64-NEXT:  entry:
1992 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1993 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
1994 //
1995 vuint16m4_t test_vwaddu_wv_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint8m2_t op2, size_t vl) {
1996   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
1997 }
1998
1999 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wx_u16m4_mu
2000 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2001 // CHECK-RV64-NEXT:  entry:
2002 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
2003 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
2004 //
2005 vuint16m4_t test_vwaddu_wx_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint8_t op2, size_t vl) {
2006   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2007 }
2008
2009 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vv_u16m8_mu
2010 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2011 // CHECK-RV64-NEXT:  entry:
2012 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
2013 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
2014 //
2015 vuint16m8_t test_vwaddu_vv_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
2016   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2017 }
2018
2019 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vx_u16m8_mu
2020 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2021 // CHECK-RV64-NEXT:  entry:
2022 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
2023 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
2024 //
2025 vuint16m8_t test_vwaddu_vx_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
2026   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2027 }
2028
2029 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wv_u16m8_mu
2030 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2031 // CHECK-RV64-NEXT:  entry:
2032 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
2033 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
2034 //
2035 vuint16m8_t test_vwaddu_wv_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint8m4_t op2, size_t vl) {
2036   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2037 }
2038
2039 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wx_u16m8_mu
2040 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2041 // CHECK-RV64-NEXT:  entry:
2042 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
2043 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
2044 //
2045 vuint16m8_t test_vwaddu_wx_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint8_t op2, size_t vl) {
2046   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2047 }
2048
2049 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vv_u32mf2_mu
2050 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2051 // CHECK-RV64-NEXT:  entry:
2052 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2053 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
2054 //
2055 vuint32mf2_t test_vwaddu_vv_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
2056   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2057 }
2058
2059 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vx_u32mf2_mu
2060 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2061 // CHECK-RV64-NEXT:  entry:
2062 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2063 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
2064 //
2065 vuint32mf2_t test_vwaddu_vx_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
2066   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2067 }
2068
2069 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wv_u32mf2_mu
2070 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2071 // CHECK-RV64-NEXT:  entry:
2072 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2073 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
2074 //
2075 vuint32mf2_t test_vwaddu_wv_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint16mf4_t op2, size_t vl) {
2076   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2077 }
2078
2079 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wx_u32mf2_mu
2080 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2081 // CHECK-RV64-NEXT:  entry:
2082 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2083 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
2084 //
2085 vuint32mf2_t test_vwaddu_wx_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint16_t op2, size_t vl) {
2086   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2087 }
2088
2089 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vv_u32m1_mu
2090 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2091 // CHECK-RV64-NEXT:  entry:
2092 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2093 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
2094 //
2095 vuint32m1_t test_vwaddu_vv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
2096   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2097 }
2098
2099 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vx_u32m1_mu
2100 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2101 // CHECK-RV64-NEXT:  entry:
2102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2103 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
2104 //
2105 vuint32m1_t test_vwaddu_vx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
2106   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2107 }
2108
2109 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wv_u32m1_mu
2110 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2111 // CHECK-RV64-NEXT:  entry:
2112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2113 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
2114 //
2115 vuint32m1_t test_vwaddu_wv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint16mf2_t op2, size_t vl) {
2116   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2117 }
2118
2119 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wx_u32m1_mu
2120 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2121 // CHECK-RV64-NEXT:  entry:
2122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2123 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
2124 //
2125 vuint32m1_t test_vwaddu_wx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint16_t op2, size_t vl) {
2126   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2127 }
2128
2129 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vv_u32m2_mu
2130 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2131 // CHECK-RV64-NEXT:  entry:
2132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2133 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
2134 //
2135 vuint32m2_t test_vwaddu_vv_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
2136   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2137 }
2138
2139 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vx_u32m2_mu
2140 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2141 // CHECK-RV64-NEXT:  entry:
2142 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2143 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
2144 //
2145 vuint32m2_t test_vwaddu_vx_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
2146   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2147 }
2148
2149 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wv_u32m2_mu
2150 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2151 // CHECK-RV64-NEXT:  entry:
2152 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2153 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
2154 //
2155 vuint32m2_t test_vwaddu_wv_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint16m1_t op2, size_t vl) {
2156   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2157 }
2158
2159 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wx_u32m2_mu
2160 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2161 // CHECK-RV64-NEXT:  entry:
2162 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2163 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
2164 //
2165 vuint32m2_t test_vwaddu_wx_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint16_t op2, size_t vl) {
2166   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2167 }
2168
2169 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vv_u32m4_mu
2170 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2171 // CHECK-RV64-NEXT:  entry:
2172 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2173 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
2174 //
2175 vuint32m4_t test_vwaddu_vv_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
2176   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2177 }
2178
2179 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vx_u32m4_mu
2180 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2181 // CHECK-RV64-NEXT:  entry:
2182 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2183 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
2184 //
2185 vuint32m4_t test_vwaddu_vx_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
2186   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2187 }
2188
2189 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wv_u32m4_mu
2190 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2191 // CHECK-RV64-NEXT:  entry:
2192 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2193 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
2194 //
2195 vuint32m4_t test_vwaddu_wv_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint16m2_t op2, size_t vl) {
2196   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2197 }
2198
2199 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wx_u32m4_mu
2200 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2201 // CHECK-RV64-NEXT:  entry:
2202 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2203 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
2204 //
2205 vuint32m4_t test_vwaddu_wx_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint16_t op2, size_t vl) {
2206   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2207 }
2208
2209 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vv_u32m8_mu
2210 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2211 // CHECK-RV64-NEXT:  entry:
2212 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
2213 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
2214 //
2215 vuint32m8_t test_vwaddu_vv_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
2216   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2217 }
2218
2219 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vx_u32m8_mu
2220 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2221 // CHECK-RV64-NEXT:  entry:
2222 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
2223 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
2224 //
2225 vuint32m8_t test_vwaddu_vx_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
2226   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2227 }
2228
2229 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wv_u32m8_mu
2230 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2231 // CHECK-RV64-NEXT:  entry:
2232 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
2233 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
2234 //
2235 vuint32m8_t test_vwaddu_wv_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint16m4_t op2, size_t vl) {
2236   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2237 }
2238
2239 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wx_u32m8_mu
2240 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2241 // CHECK-RV64-NEXT:  entry:
2242 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
2243 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
2244 //
2245 vuint32m8_t test_vwaddu_wx_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint16_t op2, size_t vl) {
2246   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2247 }
2248
2249 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vv_u64m1_mu
2250 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2251 // CHECK-RV64-NEXT:  entry:
2252 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2253 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
2254 //
2255 vuint64m1_t test_vwaddu_vv_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
2256   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2257 }
2258
2259 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vx_u64m1_mu
2260 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2261 // CHECK-RV64-NEXT:  entry:
2262 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2263 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
2264 //
2265 vuint64m1_t test_vwaddu_vx_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
2266   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2267 }
2268
2269 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wv_u64m1_mu
2270 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2271 // CHECK-RV64-NEXT:  entry:
2272 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2273 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
2274 //
2275 vuint64m1_t test_vwaddu_wv_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint32mf2_t op2, size_t vl) {
2276   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2277 }
2278
2279 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wx_u64m1_mu
2280 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2281 // CHECK-RV64-NEXT:  entry:
2282 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
2283 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
2284 //
2285 vuint64m1_t test_vwaddu_wx_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint32_t op2, size_t vl) {
2286   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2287 }
2288
2289 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vv_u64m2_mu
2290 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2291 // CHECK-RV64-NEXT:  entry:
2292 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2293 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
2294 //
2295 vuint64m2_t test_vwaddu_vv_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
2296   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2297 }
2298
2299 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vx_u64m2_mu
2300 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2301 // CHECK-RV64-NEXT:  entry:
2302 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2303 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
2304 //
2305 vuint64m2_t test_vwaddu_vx_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
2306   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2307 }
2308
2309 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wv_u64m2_mu
2310 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2311 // CHECK-RV64-NEXT:  entry:
2312 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2313 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
2314 //
2315 vuint64m2_t test_vwaddu_wv_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint32m1_t op2, size_t vl) {
2316   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2317 }
2318
2319 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wx_u64m2_mu
2320 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2321 // CHECK-RV64-NEXT:  entry:
2322 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
2323 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
2324 //
2325 vuint64m2_t test_vwaddu_wx_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint32_t op2, size_t vl) {
2326   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2327 }
2328
2329 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vv_u64m4_mu
2330 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2331 // CHECK-RV64-NEXT:  entry:
2332 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2333 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
2334 //
2335 vuint64m4_t test_vwaddu_vv_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
2336   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2337 }
2338
2339 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vx_u64m4_mu
2340 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2341 // CHECK-RV64-NEXT:  entry:
2342 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2343 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
2344 //
2345 vuint64m4_t test_vwaddu_vx_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
2346   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2347 }
2348
2349 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wv_u64m4_mu
2350 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2351 // CHECK-RV64-NEXT:  entry:
2352 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2353 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
2354 //
2355 vuint64m4_t test_vwaddu_wv_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint32m2_t op2, size_t vl) {
2356   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2357 }
2358
2359 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wx_u64m4_mu
2360 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2361 // CHECK-RV64-NEXT:  entry:
2362 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
2363 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
2364 //
2365 vuint64m4_t test_vwaddu_wx_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint32_t op2, size_t vl) {
2366   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2367 }
2368
2369 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vv_u64m8_mu
2370 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2371 // CHECK-RV64-NEXT:  entry:
2372 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2373 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
2374 //
2375 vuint64m8_t test_vwaddu_vv_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
2376   return __riscv_vwaddu_vv_mu(mask, maskedoff, op1, op2, vl);
2377 }
2378
2379 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vx_u64m8_mu
2380 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2381 // CHECK-RV64-NEXT:  entry:
2382 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2383 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
2384 //
2385 vuint64m8_t test_vwaddu_vx_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
2386   return __riscv_vwaddu_vx_mu(mask, maskedoff, op1, op2, vl);
2387 }
2388
2389 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wv_u64m8_mu
2390 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2391 // CHECK-RV64-NEXT:  entry:
2392 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2393 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
2394 //
2395 vuint64m8_t test_vwaddu_wv_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint32m4_t op2, size_t vl) {
2396   return __riscv_vwaddu_wv_mu(mask, maskedoff, op1, op2, vl);
2397 }
2398
2399 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wx_u64m8_mu
2400 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2401 // CHECK-RV64-NEXT:  entry:
2402 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
2403 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
2404 //
2405 vuint64m8_t test_vwaddu_wx_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint32_t op2, size_t vl) {
2406   return __riscv_vwaddu_wx_mu(mask, maskedoff, op1, op2, vl);
2407 }
2408