clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
   4 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   5 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   6
   7 #include <riscv_vector.h>
   8
   9 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu
  10 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  11 // CHECK-RV64-NEXT:  entry:
  12 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  13 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  14 //
  15 vint16m1_t test_vwredsum_vs_i8mf8_i16m1_tu(vint16m1_t maskedoff, vint8mf8_t vector, vint16m1_t scalar, size_t vl) {
  16   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  17 }
  18
  19 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu
  20 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  21 // CHECK-RV64-NEXT:  entry:
  22 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  23 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  24 //
  25 vint16m1_t test_vwredsum_vs_i8mf4_i16m1_tu(vint16m1_t maskedoff, vint8mf4_t vector, vint16m1_t scalar, size_t vl) {
  26   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  27 }
  28
  29 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu
  30 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  31 // CHECK-RV64-NEXT:  entry:
  32 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  33 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  34 //
  35 vint16m1_t test_vwredsum_vs_i8mf2_i16m1_tu(vint16m1_t maskedoff, vint8mf2_t vector, vint16m1_t scalar, size_t vl) {
  36   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  37 }
  38
  39 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu
  40 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  41 // CHECK-RV64-NEXT:  entry:
  42 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  43 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  44 //
  45 vint16m1_t test_vwredsum_vs_i8m1_i16m1_tu(vint16m1_t maskedoff, vint8m1_t vector, vint16m1_t scalar, size_t vl) {
  46   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  47 }
  48
  49 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu
  50 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  51 // CHECK-RV64-NEXT:  entry:
  52 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  53 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  54 //
  55 vint16m1_t test_vwredsum_vs_i8m2_i16m1_tu(vint16m1_t maskedoff, vint8m2_t vector, vint16m1_t scalar, size_t vl) {
  56   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  57 }
  58
  59 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu
  60 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  61 // CHECK-RV64-NEXT:  entry:
  62 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  63 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  64 //
  65 vint16m1_t test_vwredsum_vs_i8m4_i16m1_tu(vint16m1_t maskedoff, vint8m4_t vector, vint16m1_t scalar, size_t vl) {
  66   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  67 }
  68
  69 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu
  70 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  71 // CHECK-RV64-NEXT:  entry:
  72 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 64 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])
  73 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  74 //
  75 vint16m1_t test_vwredsum_vs_i8m8_i16m1_tu(vint16m1_t maskedoff, vint8m8_t vector, vint16m1_t scalar, size_t vl) {
  76   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  77 }
  78
  79 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu
  80 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  81 // CHECK-RV64-NEXT:  entry:
  82 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])
  83 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  84 //
  85 vint32m1_t test_vwredsum_vs_i16mf4_i32m1_tu(vint32m1_t maskedoff, vint16mf4_t vector, vint32m1_t scalar, size_t vl) {
  86   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  87 }
  88
  89 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1_tu
  90 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  91 // CHECK-RV64-NEXT:  entry:
  92 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])
  93 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  94 //
  95 vint32m1_t test_vwredsum_vs_i16mf2_i32m1_tu(vint32m1_t maskedoff, vint16mf2_t vector, vint32m1_t scalar, size_t vl) {
  96   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
  97 }
  98
  99 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1_tu
 100 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 101 // CHECK-RV64-NEXT:  entry:
 102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])
 103 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 104 //
 105 vint32m1_t test_vwredsum_vs_i16m1_i32m1_tu(vint32m1_t maskedoff, vint16m1_t vector, vint32m1_t scalar, size_t vl) {
 106   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 107 }
 108
 109 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m2_i32m1_tu
 110 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 111 // CHECK-RV64-NEXT:  entry:
 112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])
 113 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 114 //
 115 vint32m1_t test_vwredsum_vs_i16m2_i32m1_tu(vint32m1_t maskedoff, vint16m2_t vector, vint32m1_t scalar, size_t vl) {
 116   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 117 }
 118
 119 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m4_i32m1_tu
 120 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 121 // CHECK-RV64-NEXT:  entry:
 122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])
 123 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 124 //
 125 vint32m1_t test_vwredsum_vs_i16m4_i32m1_tu(vint32m1_t maskedoff, vint16m4_t vector, vint32m1_t scalar, size_t vl) {
 126   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 127 }
 128
 129 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m8_i32m1_tu
 130 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 131 // CHECK-RV64-NEXT:  entry:
 132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 32 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])
 133 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 134 //
 135 vint32m1_t test_vwredsum_vs_i16m8_i32m1_tu(vint32m1_t maskedoff, vint16m8_t vector, vint32m1_t scalar, size_t vl) {
 136   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 137 }
 138
 139 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32mf2_i64m1_tu
 140 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 141 // CHECK-RV64-NEXT:  entry:
 142 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])
 143 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 144 //
 145 vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tu(vint64m1_t maskedoff, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
 146   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 147 }
 148
 149 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m1_i64m1_tu
 150 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 151 // CHECK-RV64-NEXT:  entry:
 152 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])
 153 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 154 //
 155 vint64m1_t test_vwredsum_vs_i32m1_i64m1_tu(vint64m1_t maskedoff, vint32m1_t vector, vint64m1_t scalar, size_t vl) {
 156   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 157 }
 158
 159 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m2_i64m1_tu
 160 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 161 // CHECK-RV64-NEXT:  entry:
 162 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])
 163 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 164 //
 165 vint64m1_t test_vwredsum_vs_i32m2_i64m1_tu(vint64m1_t maskedoff, vint32m2_t vector, vint64m1_t scalar, size_t vl) {
 166   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 167 }
 168
 169 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m4_i64m1_tu
 170 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 171 // CHECK-RV64-NEXT:  entry:
 172 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])
 173 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 174 //
 175 vint64m1_t test_vwredsum_vs_i32m4_i64m1_tu(vint64m1_t maskedoff, vint32m4_t vector, vint64m1_t scalar, size_t vl) {
 176   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 177 }
 178
 179 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m8_i64m1_tu
 180 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 181 // CHECK-RV64-NEXT:  entry:
 182 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 16 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])
 183 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 184 //
 185 vint64m1_t test_vwredsum_vs_i32m8_i64m1_tu(vint64m1_t maskedoff, vint32m8_t vector, vint64m1_t scalar, size_t vl) {
 186   return __riscv_vwredsum_tu(maskedoff, vector, scalar, vl);
 187 }
 188
 189 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tum
 190 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 191 // CHECK-RV64-NEXT:  entry:
 192 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 193 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 194 //
 195 vint16m1_t test_vwredsum_vs_i8mf8_i16m1_tum(vbool64_t mask, vint16m1_t maskedoff, vint8mf8_t vector, vint16m1_t scalar, size_t vl) {
 196   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 197 }
 198
 199 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tum
 200 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 201 // CHECK-RV64-NEXT:  entry:
 202 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 203 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 204 //
 205 vint16m1_t test_vwredsum_vs_i8mf4_i16m1_tum(vbool32_t mask, vint16m1_t maskedoff, vint8mf4_t vector, vint16m1_t scalar, size_t vl) {
 206   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 207 }
 208
 209 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tum
 210 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 211 // CHECK-RV64-NEXT:  entry:
 212 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 213 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 214 //
 215 vint16m1_t test_vwredsum_vs_i8mf2_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t vector, vint16m1_t scalar, size_t vl) {
 216   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 217 }
 218
 219 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tum
 220 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 221 // CHECK-RV64-NEXT:  entry:
 222 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 223 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 224 //
 225 vint16m1_t test_vwredsum_vs_i8m1_i16m1_tum(vbool8_t mask, vint16m1_t maskedoff, vint8m1_t vector, vint16m1_t scalar, size_t vl) {
 226   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 227 }
 228
 229 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tum
 230 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 231 // CHECK-RV64-NEXT:  entry:
 232 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
 233 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 234 //
 235 vint16m1_t test_vwredsum_vs_i8m2_i16m1_tum(vbool4_t mask, vint16m1_t maskedoff, vint8m2_t vector, vint16m1_t scalar, size_t vl) {
 236   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 237 }
 238
 239 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tum
 240 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 241 // CHECK-RV64-NEXT:  entry:
 242 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
 243 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 244 //
 245 vint16m1_t test_vwredsum_vs_i8m4_i16m1_tum(vbool2_t mask, vint16m1_t maskedoff, vint8m4_t vector, vint16m1_t scalar, size_t vl) {
 246   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 247 }
 248
 249 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tum
 250 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 251 // CHECK-RV64-NEXT:  entry:
 252 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 64 x i8> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
 253 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 254 //
 255 vint16m1_t test_vwredsum_vs_i8m8_i16m1_tum(vbool1_t mask, vint16m1_t maskedoff, vint8m8_t vector, vint16m1_t scalar, size_t vl) {
 256   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 257 }
 258
 259 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tum
 260 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 261 // CHECK-RV64-NEXT:  entry:
 262 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 263 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 264 //
 265 vint32m1_t test_vwredsum_vs_i16mf4_i32m1_tum(vbool64_t mask, vint32m1_t maskedoff, vint16mf4_t vector, vint32m1_t scalar, size_t vl) {
 266   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 267 }
 268
 269 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1_tum
 270 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 271 // CHECK-RV64-NEXT:  entry:
 272 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 273 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 274 //
 275 vint32m1_t test_vwredsum_vs_i16mf2_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t vector, vint32m1_t scalar, size_t vl) {
 276   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 277 }
 278
 279 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1_tum
 280 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 281 // CHECK-RV64-NEXT:  entry:
 282 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 283 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 284 //
 285 vint32m1_t test_vwredsum_vs_i16m1_i32m1_tum(vbool16_t mask, vint32m1_t maskedoff, vint16m1_t vector, vint32m1_t scalar, size_t vl) {
 286   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 287 }
 288
 289 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m2_i32m1_tum
 290 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 291 // CHECK-RV64-NEXT:  entry:
 292 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 293 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 294 //
 295 vint32m1_t test_vwredsum_vs_i16m2_i32m1_tum(vbool8_t mask, vint32m1_t maskedoff, vint16m2_t vector, vint32m1_t scalar, size_t vl) {
 296   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 297 }
 298
 299 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m4_i32m1_tum
 300 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 301 // CHECK-RV64-NEXT:  entry:
 302 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
 303 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 304 //
 305 vint32m1_t test_vwredsum_vs_i16m4_i32m1_tum(vbool4_t mask, vint32m1_t maskedoff, vint16m4_t vector, vint32m1_t scalar, size_t vl) {
 306   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 307 }
 308
 309 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m8_i32m1_tum
 310 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 311 // CHECK-RV64-NEXT:  entry:
 312 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 32 x i16> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
 313 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 314 //
 315 vint32m1_t test_vwredsum_vs_i16m8_i32m1_tum(vbool2_t mask, vint32m1_t maskedoff, vint16m8_t vector, vint32m1_t scalar, size_t vl) {
 316   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 317 }
 318
 319 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32mf2_i64m1_tum
 320 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 321 // CHECK-RV64-NEXT:  entry:
 322 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
 323 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 324 //
 325 vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
 326   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 327 }
 328
 329 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m1_i64m1_tum
 330 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 331 // CHECK-RV64-NEXT:  entry:
 332 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
 333 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 334 //
 335 vint64m1_t test_vwredsum_vs_i32m1_i64m1_tum(vbool32_t mask, vint64m1_t maskedoff, vint32m1_t vector, vint64m1_t scalar, size_t vl) {
 336   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 337 }
 338
 339 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m2_i64m1_tum
 340 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 341 // CHECK-RV64-NEXT:  entry:
 342 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
 343 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 344 //
 345 vint64m1_t test_vwredsum_vs_i32m2_i64m1_tum(vbool16_t mask, vint64m1_t maskedoff, vint32m2_t vector, vint64m1_t scalar, size_t vl) {
 346   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 347 }
 348
 349 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m4_i64m1_tum
 350 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 351 // CHECK-RV64-NEXT:  entry:
 352 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
 353 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 354 //
 355 vint64m1_t test_vwredsum_vs_i32m4_i64m1_tum(vbool8_t mask, vint64m1_t maskedoff, vint32m4_t vector, vint64m1_t scalar, size_t vl) {
 356   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 357 }
 358
 359 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwredsum_vs_i32m8_i64m1_tum
 360 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 361 // CHECK-RV64-NEXT:  entry:
 362 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 16 x i32> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
 363 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 364 //
 365 vint64m1_t test_vwredsum_vs_i32m8_i64m1_tum(vbool4_t mask, vint64m1_t maskedoff, vint32m8_t vector, vint64m1_t scalar, size_t vl) {
 366   return __riscv_vwredsum_tum(mask, maskedoff, vector, scalar, vl);
 367 }
 368