clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
   4 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   5 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   6
   7 #include <riscv_vector.h>
   8
   9 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu
  10 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  11 // CHECK-RV64-NEXT:  entry:
  12 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[VL]])
  13 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
  14 //
  15 vuint16mf4_t test_vzext_vf2_u16mf4_tu(vuint16mf4_t maskedoff, vuint8mf8_t op1, size_t vl) {
  16   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  17 }
  18
  19 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu
  20 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  21 // CHECK-RV64-NEXT:  entry:
  22 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[VL]])
  23 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
  24 //
  25 vuint16mf2_t test_vzext_vf2_u16mf2_tu(vuint16mf2_t maskedoff, vuint8mf4_t op1, size_t vl) {
  26   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  27 }
  28
  29 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu
  30 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  31 // CHECK-RV64-NEXT:  entry:
  32 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[VL]])
  33 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
  34 //
  35 vuint16m1_t test_vzext_vf2_u16m1_tu(vuint16m1_t maskedoff, vuint8mf2_t op1, size_t vl) {
  36   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  37 }
  38
  39 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu
  40 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  41 // CHECK-RV64-NEXT:  entry:
  42 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[VL]])
  43 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  44 //
  45 vuint16m2_t test_vzext_vf2_u16m2_tu(vuint16m2_t maskedoff, vuint8m1_t op1, size_t vl) {
  46   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  47 }
  48
  49 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu
  50 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  51 // CHECK-RV64-NEXT:  entry:
  52 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[VL]])
  53 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
  54 //
  55 vuint16m4_t test_vzext_vf2_u16m4_tu(vuint16m4_t maskedoff, vuint8m2_t op1, size_t vl) {
  56   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  57 }
  58
  59 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu
  60 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  61 // CHECK-RV64-NEXT:  entry:
  62 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[VL]])
  63 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
  64 //
  65 vuint16m8_t test_vzext_vf2_u16m8_tu(vuint16m8_t maskedoff, vuint8m4_t op1, size_t vl) {
  66   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  67 }
  68
  69 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu
  70 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  71 // CHECK-RV64-NEXT:  entry:
  72 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[VL]])
  73 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
  74 //
  75 vuint32mf2_t test_vzext_vf2_u32mf2_tu(vuint32mf2_t maskedoff, vuint16mf4_t op1, size_t vl) {
  76   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  77 }
  78
  79 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu
  80 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  81 // CHECK-RV64-NEXT:  entry:
  82 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[VL]])
  83 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  84 //
  85 vuint32m1_t test_vzext_vf2_u32m1_tu(vuint32m1_t maskedoff, vuint16mf2_t op1, size_t vl) {
  86   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  87 }
  88
  89 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu
  90 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  91 // CHECK-RV64-NEXT:  entry:
  92 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[VL]])
  93 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  94 //
  95 vuint32m2_t test_vzext_vf2_u32m2_tu(vuint32m2_t maskedoff, vuint16m1_t op1, size_t vl) {
  96   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
  97 }
  98
  99 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu
 100 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 101 // CHECK-RV64-NEXT:  entry:
 102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[VL]])
 103 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 104 //
 105 vuint32m4_t test_vzext_vf2_u32m4_tu(vuint32m4_t maskedoff, vuint16m2_t op1, size_t vl) {
 106   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
 107 }
 108
 109 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8_tu
 110 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 111 // CHECK-RV64-NEXT:  entry:
 112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[VL]])
 113 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 114 //
 115 vuint32m8_t test_vzext_vf2_u32m8_tu(vuint32m8_t maskedoff, vuint16m4_t op1, size_t vl) {
 116   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
 117 }
 118
 119 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1_tu
 120 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 121 // CHECK-RV64-NEXT:  entry:
 122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[VL]])
 123 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 124 //
 125 vuint64m1_t test_vzext_vf2_u64m1_tu(vuint64m1_t maskedoff, vuint32mf2_t op1, size_t vl) {
 126   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
 127 }
 128
 129 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2_tu
 130 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 131 // CHECK-RV64-NEXT:  entry:
 132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[VL]])
 133 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 134 //
 135 vuint64m2_t test_vzext_vf2_u64m2_tu(vuint64m2_t maskedoff, vuint32m1_t op1, size_t vl) {
 136   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
 137 }
 138
 139 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf2_u64m4_tu
 140 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 141 // CHECK-RV64-NEXT:  entry:
 142 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[VL]])
 143 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 144 //
 145 vuint64m4_t test_vzext_vf2_u64m4_tu(vuint64m4_t maskedoff, vuint32m2_t op1, size_t vl) {
 146   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
 147 }
 148
 149 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf2_u64m8_tu
 150 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 151 // CHECK-RV64-NEXT:  entry:
 152 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[VL]])
 153 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 154 //
 155 vuint64m8_t test_vzext_vf2_u64m8_tu(vuint64m8_t maskedoff, vuint32m4_t op1, size_t vl) {
 156   return __riscv_vzext_vf2_tu(maskedoff, op1, vl);
 157 }
 158
 159 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tum
 160 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 161 // CHECK-RV64-NEXT:  entry:
 162 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 163 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 164 //
 165 vuint16mf4_t test_vzext_vf2_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, size_t vl) {
 166   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 167 }
 168
 169 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tum
 170 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 171 // CHECK-RV64-NEXT:  entry:
 172 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 173 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 174 //
 175 vuint16mf2_t test_vzext_vf2_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, size_t vl) {
 176   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 177 }
 178
 179 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tum
 180 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 181 // CHECK-RV64-NEXT:  entry:
 182 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 183 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 184 //
 185 vuint16m1_t test_vzext_vf2_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, size_t vl) {
 186   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 187 }
 188
 189 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tum
 190 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 191 // CHECK-RV64-NEXT:  entry:
 192 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 193 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 194 //
 195 vuint16m2_t test_vzext_vf2_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, size_t vl) {
 196   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 197 }
 198
 199 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tum
 200 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 201 // CHECK-RV64-NEXT:  entry:
 202 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
 203 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 204 //
 205 vuint16m4_t test_vzext_vf2_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, size_t vl) {
 206   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 207 }
 208
 209 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tum
 210 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 211 // CHECK-RV64-NEXT:  entry:
 212 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
 213 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 214 //
 215 vuint16m8_t test_vzext_vf2_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, size_t vl) {
 216   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 217 }
 218
 219 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tum
 220 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 221 // CHECK-RV64-NEXT:  entry:
 222 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 223 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 224 //
 225 vuint32mf2_t test_vzext_vf2_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, size_t vl) {
 226   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 227 }
 228
 229 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tum
 230 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 231 // CHECK-RV64-NEXT:  entry:
 232 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 233 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 234 //
 235 vuint32m1_t test_vzext_vf2_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, size_t vl) {
 236   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 237 }
 238
 239 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tum
 240 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 241 // CHECK-RV64-NEXT:  entry:
 242 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 243 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 244 //
 245 vuint32m2_t test_vzext_vf2_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, size_t vl) {
 246   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 247 }
 248
 249 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tum
 250 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 251 // CHECK-RV64-NEXT:  entry:
 252 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 253 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 254 //
 255 vuint32m4_t test_vzext_vf2_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, size_t vl) {
 256   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 257 }
 258
 259 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8_tum
 260 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 261 // CHECK-RV64-NEXT:  entry:
 262 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
 263 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 264 //
 265 vuint32m8_t test_vzext_vf2_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, size_t vl) {
 266   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 267 }
 268
 269 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1_tum
 270 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 271 // CHECK-RV64-NEXT:  entry:
 272 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
 273 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 274 //
 275 vuint64m1_t test_vzext_vf2_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, size_t vl) {
 276   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 277 }
 278
 279 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2_tum
 280 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 281 // CHECK-RV64-NEXT:  entry:
 282 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
 283 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 284 //
 285 vuint64m2_t test_vzext_vf2_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, size_t vl) {
 286   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 287 }
 288
 289 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf2_u64m4_tum
 290 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 291 // CHECK-RV64-NEXT:  entry:
 292 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
 293 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 294 //
 295 vuint64m4_t test_vzext_vf2_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, size_t vl) {
 296   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 297 }
 298
 299 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf2_u64m8_tum
 300 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 301 // CHECK-RV64-NEXT:  entry:
 302 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
 303 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 304 //
 305 vuint64m8_t test_vzext_vf2_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, size_t vl) {
 306   return __riscv_vzext_vf2_tum(mask, maskedoff, op1, vl);
 307 }
 308
 309 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tumu
 310 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 311 // CHECK-RV64-NEXT:  entry:
 312 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
 313 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 314 //
 315 vuint16mf4_t test_vzext_vf2_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, size_t vl) {
 316   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 317 }
 318
 319 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tumu
 320 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 321 // CHECK-RV64-NEXT:  entry:
 322 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
 323 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 324 //
 325 vuint16mf2_t test_vzext_vf2_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, size_t vl) {
 326   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 327 }
 328
 329 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tumu
 330 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 331 // CHECK-RV64-NEXT:  entry:
 332 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
 333 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 334 //
 335 vuint16m1_t test_vzext_vf2_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, size_t vl) {
 336   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 337 }
 338
 339 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tumu
 340 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 341 // CHECK-RV64-NEXT:  entry:
 342 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
 343 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 344 //
 345 vuint16m2_t test_vzext_vf2_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, size_t vl) {
 346   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 347 }
 348
 349 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tumu
 350 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 351 // CHECK-RV64-NEXT:  entry:
 352 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
 353 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 354 //
 355 vuint16m4_t test_vzext_vf2_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, size_t vl) {
 356   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 357 }
 358
 359 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tumu
 360 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 361 // CHECK-RV64-NEXT:  entry:
 362 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
 363 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 364 //
 365 vuint16m8_t test_vzext_vf2_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, size_t vl) {
 366   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 367 }
 368
 369 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tumu
 370 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 371 // CHECK-RV64-NEXT:  entry:
 372 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
 373 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 374 //
 375 vuint32mf2_t test_vzext_vf2_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, size_t vl) {
 376   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 377 }
 378
 379 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tumu
 380 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 381 // CHECK-RV64-NEXT:  entry:
 382 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
 383 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 384 //
 385 vuint32m1_t test_vzext_vf2_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, size_t vl) {
 386   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 387 }
 388
 389 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tumu
 390 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 391 // CHECK-RV64-NEXT:  entry:
 392 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
 393 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 394 //
 395 vuint32m2_t test_vzext_vf2_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, size_t vl) {
 396   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 397 }
 398
 399 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tumu
 400 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 401 // CHECK-RV64-NEXT:  entry:
 402 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
 403 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 404 //
 405 vuint32m4_t test_vzext_vf2_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, size_t vl) {
 406   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 407 }
 408
 409 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8_tumu
 410 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 411 // CHECK-RV64-NEXT:  entry:
 412 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
 413 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 414 //
 415 vuint32m8_t test_vzext_vf2_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, size_t vl) {
 416   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 417 }
 418
 419 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1_tumu
 420 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 421 // CHECK-RV64-NEXT:  entry:
 422 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
 423 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 424 //
 425 vuint64m1_t test_vzext_vf2_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, size_t vl) {
 426   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 427 }
 428
 429 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2_tumu
 430 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 431 // CHECK-RV64-NEXT:  entry:
 432 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
 433 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 434 //
 435 vuint64m2_t test_vzext_vf2_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, size_t vl) {
 436   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 437 }
 438
 439 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf2_u64m4_tumu
 440 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 441 // CHECK-RV64-NEXT:  entry:
 442 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
 443 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 444 //
 445 vuint64m4_t test_vzext_vf2_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, size_t vl) {
 446   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 447 }
 448
 449 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf2_u64m8_tumu
 450 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 451 // CHECK-RV64-NEXT:  entry:
 452 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
 453 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 454 //
 455 vuint64m8_t test_vzext_vf2_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, size_t vl) {
 456   return __riscv_vzext_vf2_tumu(mask, maskedoff, op1, vl);
 457 }
 458
 459 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_mu
 460 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 461 // CHECK-RV64-NEXT:  entry:
 462 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
 463 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 464 //
 465 vuint16mf4_t test_vzext_vf2_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, size_t vl) {
 466   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 467 }
 468
 469 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_mu
 470 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 471 // CHECK-RV64-NEXT:  entry:
 472 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
 473 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 474 //
 475 vuint16mf2_t test_vzext_vf2_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, size_t vl) {
 476   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 477 }
 478
 479 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_mu
 480 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 481 // CHECK-RV64-NEXT:  entry:
 482 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
 483 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 484 //
 485 vuint16m1_t test_vzext_vf2_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, size_t vl) {
 486   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 487 }
 488
 489 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_mu
 490 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 491 // CHECK-RV64-NEXT:  entry:
 492 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
 493 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 494 //
 495 vuint16m2_t test_vzext_vf2_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, size_t vl) {
 496   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 497 }
 498
 499 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_mu
 500 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 501 // CHECK-RV64-NEXT:  entry:
 502 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
 503 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 504 //
 505 vuint16m4_t test_vzext_vf2_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, size_t vl) {
 506   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 507 }
 508
 509 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_mu
 510 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 511 // CHECK-RV64-NEXT:  entry:
 512 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
 513 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 514 //
 515 vuint16m8_t test_vzext_vf2_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, size_t vl) {
 516   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 517 }
 518
 519 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_mu
 520 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 521 // CHECK-RV64-NEXT:  entry:
 522 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
 523 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 524 //
 525 vuint32mf2_t test_vzext_vf2_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, size_t vl) {
 526   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 527 }
 528
 529 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_mu
 530 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 531 // CHECK-RV64-NEXT:  entry:
 532 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
 533 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 534 //
 535 vuint32m1_t test_vzext_vf2_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, size_t vl) {
 536   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 537 }
 538
 539 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_mu
 540 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 541 // CHECK-RV64-NEXT:  entry:
 542 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
 543 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 544 //
 545 vuint32m2_t test_vzext_vf2_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, size_t vl) {
 546   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 547 }
 548
 549 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_mu
 550 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 551 // CHECK-RV64-NEXT:  entry:
 552 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
 553 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 554 //
 555 vuint32m4_t test_vzext_vf2_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, size_t vl) {
 556   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 557 }
 558
 559 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8_mu
 560 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 561 // CHECK-RV64-NEXT:  entry:
 562 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
 563 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 564 //
 565 vuint32m8_t test_vzext_vf2_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, size_t vl) {
 566   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 567 }
 568
 569 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1_mu
 570 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 571 // CHECK-RV64-NEXT:  entry:
 572 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
 573 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 574 //
 575 vuint64m1_t test_vzext_vf2_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, size_t vl) {
 576   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 577 }
 578
 579 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2_mu
 580 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 581 // CHECK-RV64-NEXT:  entry:
 582 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
 583 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 584 //
 585 vuint64m2_t test_vzext_vf2_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, size_t vl) {
 586   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 587 }
 588
 589 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf2_u64m4_mu
 590 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 591 // CHECK-RV64-NEXT:  entry:
 592 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
 593 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 594 //
 595 vuint64m4_t test_vzext_vf2_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, size_t vl) {
 596   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 597 }
 598
 599 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf2_u64m8_mu
 600 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 601 // CHECK-RV64-NEXT:  entry:
 602 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
 603 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 604 //
 605 vuint64m8_t test_vzext_vf2_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, size_t vl) {
 606   return __riscv_vzext_vf2_mu(mask, maskedoff, op1, vl);
 607 }
 608