1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
3 // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
4 // RUN: -target-feature +experimental-zvkned -fsyntax-only -verify %s
6 #include <riscv_vector.h>
8 vuint32m1_t
test_vaeskf1_vi_u32m1(vuint32m1_t vs2
, size_t vl
) {
9 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
10 return __riscv_vaeskf1_vi_u32m1(vs2
, 33, vl
);
13 vuint32m1_t
test_vaeskf1_vi_u32m1_tu(vuint32m1_t merge
, vuint32m1_t vs2
, size_t vl
) {
14 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
15 return __riscv_vaeskf1_vi_u32m1_tu(merge
, vs2
, 33, vl
);