clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwsub-out-of-range.c

   1 // REQUIRES: riscv-registered-target
   2 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
   3 // RUN:   -target-feature +v -target-feature +zfh -target-feature +zvfh \
   4 // RUN:   -fsyntax-only -verify %s
   5
   6 #include <riscv_vector.h>
   7
   8 vfloat32m1_t test_vfwsub_vv_f32m1_rm(vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
   9   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  10   return __riscv_vfwsub_vv_f32m1_rm(op1, op2, 5, vl);
  11 }
  12
  13 vfloat32m1_t test_vfwsub_vf_f32m1_rm(vfloat16mf2_t op1, _Float16 op2, size_t vl) {
  14   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  15   return __riscv_vfwsub_vf_f32m1_rm(op1, op2, 5, vl);
  16 }
  17
  18 vfloat32m1_t test_vfwsub_wv_f32m1_rm(vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
  19   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  20   return __riscv_vfwsub_wv_f32m1_rm(op1, op2, 5, vl);
  21 }
  22
  23 vfloat32m1_t test_vfwsub_wf_f32m1_rm(vfloat32m1_t op1, _Float16 op2, size_t vl) {
  24   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  25   return __riscv_vfwsub_wf_f32m1_rm(op1, op2, 5, vl);
  26 }
  27
  28 vfloat32m1_t test_vfwsub_vv_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
  29   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  30   return __riscv_vfwsub_vv_f32m1_rm_m(mask, op1, op2, 5, vl);
  31 }
  32
  33 vfloat32m1_t test_vfwsub_vf_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
  34   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  35   return __riscv_vfwsub_vf_f32m1_rm_m(mask, op1, op2, 5, vl);
  36 }
  37
  38 vfloat32m1_t test_vfwsub_wv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
  39   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  40   return __riscv_vfwsub_wv_f32m1_rm_m(mask, op1, op2, 5, vl);
  41 }
  42
  43 vfloat32m1_t test_vfwsub_wf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t op1, _Float16 op2, size_t vl) {
  44   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  45   return __riscv_vfwsub_wf_f32m1_rm_m(mask, op1, op2, 5, vl);
  46 }
  47
  48 vfloat32m1_t test_vfwsub_vv_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
  49   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  50   return __riscv_vfwsub_vv_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
  51 }
  52
  53 vfloat32m1_t test_vfwsub_vf_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
  54   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  55   return __riscv_vfwsub_vf_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
  56 }
  57
  58 vfloat32m1_t test_vfwsub_wv_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
  59   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  60   return __riscv_vfwsub_wv_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
  61 }
  62
  63 vfloat32m1_t test_vfwsub_wf_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
  64   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  65   return __riscv_vfwsub_wf_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
  66 }
  67
  68 vfloat32m1_t test_vfwsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
  69   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  70   return __riscv_vfwsub_vv_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
  71 }
  72
  73 vfloat32m1_t test_vfwsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
  74   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  75   return __riscv_vfwsub_vf_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
  76 }
  77
  78 vfloat32m1_t test_vfwsub_wv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
  79   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  80   return __riscv_vfwsub_wv_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
  81 }
  82
  83 vfloat32m1_t test_vfwsub_wf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
  84   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  85   return __riscv_vfwsub_wf_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
  86 }
  87
  88 vfloat32m1_t test_vfwsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
  89   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  90   return __riscv_vfwsub_vv_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
  91 }
  92
  93 vfloat32m1_t test_vfwsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
  94   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
  95   return __riscv_vfwsub_vf_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
  96 }
  97
  98 vfloat32m1_t test_vfwsub_wv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
  99   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
 100   return __riscv_vfwsub_wv_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
 101 }
 102
 103 vfloat32m1_t test_vfwsub_wf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
 104   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
 105   return __riscv_vfwsub_wf_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
 106 }
 107
 108 vfloat32m1_t test_vfwsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
 109   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
 110   return __riscv_vfwsub_vv_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
 111 }
 112
 113 vfloat32m1_t test_vfwsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
 114   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
 115   return __riscv_vfwsub_vf_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
 116 }
 117
 118 vfloat32m1_t test_vfwsub_wv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
 119   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
 120   return __riscv_vfwsub_wv_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
 121 }
 122
 123 vfloat32m1_t test_vfwsub_wf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
 124   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
 125   return __riscv_vfwsub_wf_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
 126 }