1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
3 // RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
4 // RUN: -fsyntax-only -verify %s
6 #include <riscv_vector.h>
8 vint32m1_t
test_vnclip_wv_i32m1(vint64m2_t op1
, vuint32m1_t shift
, size_t vl
) {
9 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
10 return __riscv_vnclip_wv_i32m1(op1
, shift
, 5, vl
);
13 vint32m1_t
test_vnclip_wx_i32m1(vint64m2_t op1
, size_t shift
, size_t vl
) {
14 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
15 return __riscv_vnclip_wx_i32m1(op1
, shift
, 5, vl
);
18 vint32m1_t
test_vnclip_wv_i32m1_m(vbool32_t mask
, vint64m2_t op1
, vuint32m1_t shift
, size_t vl
) {
19 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
20 return __riscv_vnclip_wv_i32m1_m(mask
, op1
, shift
, 5, vl
);
23 vint32m1_t
test_vnclip_wx_i32m1_m(vbool32_t mask
, vint64m2_t op1
, size_t shift
, size_t vl
) {
24 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
25 return __riscv_vnclip_wx_i32m1_m(mask
, op1
, shift
, 5, vl
);
28 vint32m1_t
test_vnclip_wv_i32m1_tu(vint32m1_t maskedoff
, vint64m2_t op1
, vuint32m1_t shift
, size_t vl
) {
29 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
30 return __riscv_vnclip_wv_i32m1_tu(maskedoff
, op1
, shift
, 5, vl
);
33 vint32m1_t
test_vnclip_wx_i32m1_tu(vint32m1_t maskedoff
, vint64m2_t op1
, size_t shift
, size_t vl
) {
34 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
35 return __riscv_vnclip_wx_i32m1_tu(maskedoff
, op1
, shift
, 5, vl
);
38 vint32m1_t
test_vnclip_wv_i32m1_tum(vbool32_t mask
, vint32m1_t maskedoff
, vint64m2_t op1
, vuint32m1_t shift
, size_t vl
) {
39 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
40 return __riscv_vnclip_wv_i32m1_tum(mask
, maskedoff
, op1
, shift
, 5, vl
);
43 vint32m1_t
test_vnclip_wx_i32m1_tum(vbool32_t mask
, vint32m1_t maskedoff
, vint64m2_t op1
, size_t shift
, size_t vl
) {
44 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
45 return __riscv_vnclip_wx_i32m1_tum(mask
, maskedoff
, op1
, shift
, 5, vl
);
48 vint32m1_t
test_vnclip_wv_i32m1_tumu(vbool32_t mask
, vint32m1_t maskedoff
, vint64m2_t op1
, vuint32m1_t shift
, size_t vl
) {
49 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
50 return __riscv_vnclip_wv_i32m1_tumu(mask
, maskedoff
, op1
, shift
, 5, vl
);
53 vint32m1_t
test_vnclip_wx_i32m1_tumu(vbool32_t mask
, vint32m1_t maskedoff
, vint64m2_t op1
, size_t shift
, size_t vl
) {
54 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
55 return __riscv_vnclip_wx_i32m1_tumu(mask
, maskedoff
, op1
, shift
, 5, vl
);
58 vint32m1_t
test_vnclip_wv_i32m1_mu(vbool32_t mask
, vint32m1_t maskedoff
, vint64m2_t op1
, vuint32m1_t shift
, size_t vl
) {
59 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
60 return __riscv_vnclip_wv_i32m1_mu(mask
, maskedoff
, op1
, shift
, 5, vl
);
63 vint32m1_t
test_vnclip_wx_i32m1_mu(vbool32_t mask
, vint32m1_t maskedoff
, vint64m2_t op1
, size_t shift
, size_t vl
) {
64 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}
65 return __riscv_vnclip_wx_i32m1_mu(mask
, maskedoff
, op1
, shift
, 5, vl
);