1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: aarch64-registered-target
3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
6 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
10 #ifdef SVE_OVERLOADED_FORMS
11 // A simple used,unused... macro, long enough to represent any SVE builtin.
12 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
14 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
17 // CHECK-LABEL: @test_svcmla_f16_z(
19 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
20 // CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
21 // CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 0)
22 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
24 // CPP-CHECK-LABEL: @_Z17test_svcmla_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_(
25 // CPP-CHECK-NEXT: entry:
26 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
27 // CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
28 // CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 0)
29 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
31 svfloat16_t
test_svcmla_f16_z(svbool_t pg
, svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
33 return SVE_ACLE_FUNC(svcmla
,_f16
,_z
,)(pg
, op1
, op2
, op3
, 0);
36 // CHECK-LABEL: @test_svcmla_f16_z_1(
38 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
39 // CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
40 // CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 90)
41 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
43 // CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_1u10__SVBool_tu13__SVFloat16_tS0_S0_(
44 // CPP-CHECK-NEXT: entry:
45 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
46 // CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
47 // CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 90)
48 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
50 svfloat16_t
test_svcmla_f16_z_1(svbool_t pg
, svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
52 return SVE_ACLE_FUNC(svcmla
,_f16
,_z
,)(pg
, op1
, op2
, op3
, 90);
55 // CHECK-LABEL: @test_svcmla_f16_z_2(
57 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
58 // CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
59 // CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 180)
60 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
62 // CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_2u10__SVBool_tu13__SVFloat16_tS0_S0_(
63 // CPP-CHECK-NEXT: entry:
64 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
65 // CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
66 // CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 180)
67 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
69 svfloat16_t
test_svcmla_f16_z_2(svbool_t pg
, svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
71 return SVE_ACLE_FUNC(svcmla
,_f16
,_z
,)(pg
, op1
, op2
, op3
, 180);
74 // CHECK-LABEL: @test_svcmla_f16_z_3(
76 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
77 // CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
78 // CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 270)
79 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
81 // CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_3u10__SVBool_tu13__SVFloat16_tS0_S0_(
82 // CPP-CHECK-NEXT: entry:
83 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
84 // CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> zeroinitializer
85 // CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 270)
86 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
88 svfloat16_t
test_svcmla_f16_z_3(svbool_t pg
, svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
90 return SVE_ACLE_FUNC(svcmla
,_f16
,_z
,)(pg
, op1
, op2
, op3
, 270);
93 // CHECK-LABEL: @test_svcmla_f32_z(
95 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
96 // CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> zeroinitializer
97 // CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[TMP1]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 0)
98 // CHECK-NEXT: ret <vscale x 4 x float> [[TMP2]]
100 // CPP-CHECK-LABEL: @_Z17test_svcmla_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_(
101 // CPP-CHECK-NEXT: entry:
102 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
103 // CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> zeroinitializer
104 // CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[TMP1]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 0)
105 // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP2]]
107 svfloat32_t
test_svcmla_f32_z(svbool_t pg
, svfloat32_t op1
, svfloat32_t op2
, svfloat32_t op3
)
109 return SVE_ACLE_FUNC(svcmla
,_f32
,_z
,)(pg
, op1
, op2
, op3
, 0);
112 // CHECK-LABEL: @test_svcmla_f64_z(
113 // CHECK-NEXT: entry:
114 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
115 // CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> zeroinitializer
116 // CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[TMP1]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 90)
117 // CHECK-NEXT: ret <vscale x 2 x double> [[TMP2]]
119 // CPP-CHECK-LABEL: @_Z17test_svcmla_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_(
120 // CPP-CHECK-NEXT: entry:
121 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
122 // CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> zeroinitializer
123 // CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[TMP1]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 90)
124 // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP2]]
126 svfloat64_t
test_svcmla_f64_z(svbool_t pg
, svfloat64_t op1
, svfloat64_t op2
, svfloat64_t op3
)
128 return SVE_ACLE_FUNC(svcmla
,_f64
,_z
,)(pg
, op1
, op2
, op3
, 90);
131 // CHECK-LABEL: @test_svcmla_f16_m(
132 // CHECK-NEXT: entry:
133 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
134 // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 180)
135 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
137 // CPP-CHECK-LABEL: @_Z17test_svcmla_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_(
138 // CPP-CHECK-NEXT: entry:
139 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
140 // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 180)
141 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
143 svfloat16_t
test_svcmla_f16_m(svbool_t pg
, svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
145 return SVE_ACLE_FUNC(svcmla
,_f16
,_m
,)(pg
, op1
, op2
, op3
, 180);
148 // CHECK-LABEL: @test_svcmla_f32_m(
149 // CHECK-NEXT: entry:
150 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
151 // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 270)
152 // CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
154 // CPP-CHECK-LABEL: @_Z17test_svcmla_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_(
155 // CPP-CHECK-NEXT: entry:
156 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
157 // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 270)
158 // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
160 svfloat32_t
test_svcmla_f32_m(svbool_t pg
, svfloat32_t op1
, svfloat32_t op2
, svfloat32_t op3
)
162 return SVE_ACLE_FUNC(svcmla
,_f32
,_m
,)(pg
, op1
, op2
, op3
, 270);
165 // CHECK-LABEL: @test_svcmla_f64_m(
166 // CHECK-NEXT: entry:
167 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
168 // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 0)
169 // CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
171 // CPP-CHECK-LABEL: @_Z17test_svcmla_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_(
172 // CPP-CHECK-NEXT: entry:
173 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
174 // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 0)
175 // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
177 svfloat64_t
test_svcmla_f64_m(svbool_t pg
, svfloat64_t op1
, svfloat64_t op2
, svfloat64_t op3
)
179 return SVE_ACLE_FUNC(svcmla
,_f64
,_m
,)(pg
, op1
, op2
, op3
, 0);
182 // CHECK-LABEL: @test_svcmla_f16_x(
183 // CHECK-NEXT: entry:
184 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
185 // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 90)
186 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
188 // CPP-CHECK-LABEL: @_Z17test_svcmla_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_(
189 // CPP-CHECK-NEXT: entry:
190 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
191 // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 90)
192 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
194 svfloat16_t
test_svcmla_f16_x(svbool_t pg
, svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
196 return SVE_ACLE_FUNC(svcmla
,_f16
,_x
,)(pg
, op1
, op2
, op3
, 90);
199 // CHECK-LABEL: @test_svcmla_f32_x(
200 // CHECK-NEXT: entry:
201 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
202 // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 180)
203 // CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
205 // CPP-CHECK-LABEL: @_Z17test_svcmla_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_(
206 // CPP-CHECK-NEXT: entry:
207 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
208 // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 180)
209 // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
211 svfloat32_t
test_svcmla_f32_x(svbool_t pg
, svfloat32_t op1
, svfloat32_t op2
, svfloat32_t op3
)
213 return SVE_ACLE_FUNC(svcmla
,_f32
,_x
,)(pg
, op1
, op2
, op3
, 180);
216 // CHECK-LABEL: @test_svcmla_f64_x(
217 // CHECK-NEXT: entry:
218 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
219 // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 270)
220 // CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
222 // CPP-CHECK-LABEL: @_Z17test_svcmla_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_(
223 // CPP-CHECK-NEXT: entry:
224 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
225 // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 270)
226 // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
228 svfloat64_t
test_svcmla_f64_x(svbool_t pg
, svfloat64_t op1
, svfloat64_t op2
, svfloat64_t op3
)
230 return SVE_ACLE_FUNC(svcmla
,_f64
,_x
,)(pg
, op1
, op2
, op3
, 270);
233 // CHECK-LABEL: @test_svcmla_lane_f16(
234 // CHECK-NEXT: entry:
235 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.lane.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 0, i32 0)
236 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
238 // CPP-CHECK-LABEL: @_Z20test_svcmla_lane_f16u13__SVFloat16_tS_S_(
239 // CPP-CHECK-NEXT: entry:
240 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.lane.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 0, i32 0)
241 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
243 svfloat16_t
test_svcmla_lane_f16(svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
245 return SVE_ACLE_FUNC(svcmla_lane
,_f16
,,)(op1
, op2
, op3
, 0, 0);
248 // CHECK-LABEL: @test_svcmla_lane_f16_1(
249 // CHECK-NEXT: entry:
250 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.lane.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3, i32 90)
251 // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
253 // CPP-CHECK-LABEL: @_Z22test_svcmla_lane_f16_1u13__SVFloat16_tS_S_(
254 // CPP-CHECK-NEXT: entry:
255 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.lane.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3, i32 90)
256 // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
258 svfloat16_t
test_svcmla_lane_f16_1(svfloat16_t op1
, svfloat16_t op2
, svfloat16_t op3
)
260 return SVE_ACLE_FUNC(svcmla_lane
,_f16
,,)(op1
, op2
, op3
, 3, 90);
263 // CHECK-LABEL: @test_svcmla_lane_f32(
264 // CHECK-NEXT: entry:
265 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.lane.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 0, i32 180)
266 // CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
268 // CPP-CHECK-LABEL: @_Z20test_svcmla_lane_f32u13__SVFloat32_tS_S_(
269 // CPP-CHECK-NEXT: entry:
270 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.lane.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 0, i32 180)
271 // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
273 svfloat32_t
test_svcmla_lane_f32(svfloat32_t op1
, svfloat32_t op2
, svfloat32_t op3
)
275 return SVE_ACLE_FUNC(svcmla_lane
,_f32
,,)(op1
, op2
, op3
, 0, 180);
278 // CHECK-LABEL: @test_svcmla_lane_f32_1(
279 // CHECK-NEXT: entry:
280 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.lane.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 1, i32 270)
281 // CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
283 // CPP-CHECK-LABEL: @_Z22test_svcmla_lane_f32_1u13__SVFloat32_tS_S_(
284 // CPP-CHECK-NEXT: entry:
285 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.lane.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 1, i32 270)
286 // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
288 svfloat32_t
test_svcmla_lane_f32_1(svfloat32_t op1
, svfloat32_t op2
, svfloat32_t op3
)
290 return SVE_ACLE_FUNC(svcmla_lane
,_f32
,,)(op1
, op2
, op3
, 1, 270);