clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   6 #include <arm_sve.h>
   7
   8 // CHECK-LABEL: @test_svcnth(
   9 // CHECK-NEXT:  entry:
  10 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
  11 // CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3
  12 // CHECK-NEXT:    ret i64 [[TMP1]]
  13 //
  14 // CPP-CHECK-LABEL: @_Z11test_svcnthv(
  15 // CPP-CHECK-NEXT:  entry:
  16 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
  17 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3
  18 // CPP-CHECK-NEXT:    ret i64 [[TMP1]]
  19 //
  20 uint64_t test_svcnth()
  21 {
  22   return svcnth();
  23 }
  24
  25 // CHECK-LABEL: @test_svcnth_pat(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 0)
  28 // CHECK-NEXT:    ret i64 [[TMP0]]
  29 //
  30 // CPP-CHECK-LABEL: @_Z15test_svcnth_patv(
  31 // CPP-CHECK-NEXT:  entry:
  32 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 0)
  33 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
  34 //
  35 uint64_t test_svcnth_pat()
  36 {
  37   return svcnth_pat(SV_POW2);
  38 }
  39
  40 // CHECK-LABEL: @test_svcnth_pat_1(
  41 // CHECK-NEXT:  entry:
  42 // CHECK-NEXT:    ret i64 1
  43 //
  44 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_1v(
  45 // CPP-CHECK-NEXT:  entry:
  46 // CPP-CHECK-NEXT:    ret i64 1
  47 //
  48 uint64_t test_svcnth_pat_1()
  49 {
  50   return svcnth_pat(SV_VL1);
  51 }
  52
  53 // CHECK-LABEL: @test_svcnth_pat_2(
  54 // CHECK-NEXT:  entry:
  55 // CHECK-NEXT:    ret i64 2
  56 //
  57 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_2v(
  58 // CPP-CHECK-NEXT:  entry:
  59 // CPP-CHECK-NEXT:    ret i64 2
  60 //
  61 uint64_t test_svcnth_pat_2()
  62 {
  63   return svcnth_pat(SV_VL2);
  64 }
  65
  66 // CHECK-LABEL: @test_svcnth_pat_3(
  67 // CHECK-NEXT:  entry:
  68 // CHECK-NEXT:    ret i64 3
  69 //
  70 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_3v(
  71 // CPP-CHECK-NEXT:  entry:
  72 // CPP-CHECK-NEXT:    ret i64 3
  73 //
  74 uint64_t test_svcnth_pat_3()
  75 {
  76   return svcnth_pat(SV_VL3);
  77 }
  78
  79 // CHECK-LABEL: @test_svcnth_pat_4(
  80 // CHECK-NEXT:  entry:
  81 // CHECK-NEXT:    ret i64 4
  82 //
  83 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_4v(
  84 // CPP-CHECK-NEXT:  entry:
  85 // CPP-CHECK-NEXT:    ret i64 4
  86 //
  87 uint64_t test_svcnth_pat_4()
  88 {
  89   return svcnth_pat(SV_VL4);
  90 }
  91
  92 // CHECK-LABEL: @test_svcnth_pat_5(
  93 // CHECK-NEXT:  entry:
  94 // CHECK-NEXT:    ret i64 5
  95 //
  96 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_5v(
  97 // CPP-CHECK-NEXT:  entry:
  98 // CPP-CHECK-NEXT:    ret i64 5
  99 //
 100 uint64_t test_svcnth_pat_5()
 101 {
 102   return svcnth_pat(SV_VL5);
 103 }
 104
 105 // CHECK-LABEL: @test_svcnth_pat_6(
 106 // CHECK-NEXT:  entry:
 107 // CHECK-NEXT:    ret i64 6
 108 //
 109 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_6v(
 110 // CPP-CHECK-NEXT:  entry:
 111 // CPP-CHECK-NEXT:    ret i64 6
 112 //
 113 uint64_t test_svcnth_pat_6()
 114 {
 115   return svcnth_pat(SV_VL6);
 116 }
 117
 118 // CHECK-LABEL: @test_svcnth_pat_7(
 119 // CHECK-NEXT:  entry:
 120 // CHECK-NEXT:    ret i64 7
 121 //
 122 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_7v(
 123 // CPP-CHECK-NEXT:  entry:
 124 // CPP-CHECK-NEXT:    ret i64 7
 125 //
 126 uint64_t test_svcnth_pat_7()
 127 {
 128   return svcnth_pat(SV_VL7);
 129 }
 130
 131 // CHECK-LABEL: @test_svcnth_pat_8(
 132 // CHECK-NEXT:  entry:
 133 // CHECK-NEXT:    ret i64 8
 134 //
 135 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_8v(
 136 // CPP-CHECK-NEXT:  entry:
 137 // CPP-CHECK-NEXT:    ret i64 8
 138 //
 139 uint64_t test_svcnth_pat_8()
 140 {
 141   return svcnth_pat(SV_VL8);
 142 }
 143
 144 // CHECK-LABEL: @test_svcnth_pat_9(
 145 // CHECK-NEXT:  entry:
 146 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 9)
 147 // CHECK-NEXT:    ret i64 [[TMP0]]
 148 //
 149 // CPP-CHECK-LABEL: @_Z17test_svcnth_pat_9v(
 150 // CPP-CHECK-NEXT:  entry:
 151 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 9)
 152 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 153 //
 154 uint64_t test_svcnth_pat_9()
 155 {
 156   return svcnth_pat(SV_VL16);
 157 }
 158
 159 // CHECK-LABEL: @test_svcnth_pat_10(
 160 // CHECK-NEXT:  entry:
 161 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 10)
 162 // CHECK-NEXT:    ret i64 [[TMP0]]
 163 //
 164 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_10v(
 165 // CPP-CHECK-NEXT:  entry:
 166 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 10)
 167 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 168 //
 169 uint64_t test_svcnth_pat_10()
 170 {
 171   return svcnth_pat(SV_VL32);
 172 }
 173
 174 // CHECK-LABEL: @test_svcnth_pat_11(
 175 // CHECK-NEXT:  entry:
 176 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 11)
 177 // CHECK-NEXT:    ret i64 [[TMP0]]
 178 //
 179 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_11v(
 180 // CPP-CHECK-NEXT:  entry:
 181 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 11)
 182 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 183 //
 184 uint64_t test_svcnth_pat_11()
 185 {
 186   return svcnth_pat(SV_VL64);
 187 }
 188
 189 // CHECK-LABEL: @test_svcnth_pat_12(
 190 // CHECK-NEXT:  entry:
 191 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 12)
 192 // CHECK-NEXT:    ret i64 [[TMP0]]
 193 //
 194 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_12v(
 195 // CPP-CHECK-NEXT:  entry:
 196 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 12)
 197 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 198 //
 199 uint64_t test_svcnth_pat_12()
 200 {
 201   return svcnth_pat(SV_VL128);
 202 }
 203
 204 // CHECK-LABEL: @test_svcnth_pat_13(
 205 // CHECK-NEXT:  entry:
 206 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 13)
 207 // CHECK-NEXT:    ret i64 [[TMP0]]
 208 //
 209 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_13v(
 210 // CPP-CHECK-NEXT:  entry:
 211 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 13)
 212 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 213 //
 214 uint64_t test_svcnth_pat_13()
 215 {
 216   return svcnth_pat(SV_VL256);
 217 }
 218
 219 // CHECK-LABEL: @test_svcnth_pat_14(
 220 // CHECK-NEXT:  entry:
 221 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 29)
 222 // CHECK-NEXT:    ret i64 [[TMP0]]
 223 //
 224 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_14v(
 225 // CPP-CHECK-NEXT:  entry:
 226 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 29)
 227 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 228 //
 229 uint64_t test_svcnth_pat_14()
 230 {
 231   return svcnth_pat(SV_MUL4);
 232 }
 233
 234 // CHECK-LABEL: @test_svcnth_pat_15(
 235 // CHECK-NEXT:  entry:
 236 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 30)
 237 // CHECK-NEXT:    ret i64 [[TMP0]]
 238 //
 239 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_15v(
 240 // CPP-CHECK-NEXT:  entry:
 241 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 30)
 242 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 243 //
 244 uint64_t test_svcnth_pat_15()
 245 {
 246   return svcnth_pat(SV_MUL3);
 247 }
 248
 249 // CHECK-LABEL: @test_svcnth_pat_16(
 250 // CHECK-NEXT:  entry:
 251 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
 252 // CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3
 253 // CHECK-NEXT:    ret i64 [[TMP1]]
 254 //
 255 // CPP-CHECK-LABEL: @_Z18test_svcnth_pat_16v(
 256 // CPP-CHECK-NEXT:  entry:
 257 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
 258 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3
 259 // CPP-CHECK-NEXT:    ret i64 [[TMP1]]
 260 //
 261 uint64_t test_svcnth_pat_16()
 262 {
 263   return svcnth_pat(SV_ALL);
 264 }