clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   6 #include <arm_sve.h>
   7
   8 // CHECK-LABEL: @test_svcntw(
   9 // CHECK-NEXT:  entry:
  10 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
  11 // CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
  12 // CHECK-NEXT:    ret i64 [[TMP1]]
  13 //
  14 // CPP-CHECK-LABEL: @_Z11test_svcntwv(
  15 // CPP-CHECK-NEXT:  entry:
  16 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
  17 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
  18 // CPP-CHECK-NEXT:    ret i64 [[TMP1]]
  19 //
  20 uint64_t test_svcntw()
  21 {
  22   return svcntw();
  23 }
  24
  25 // CHECK-LABEL: @test_svcntw_pat(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 0)
  28 // CHECK-NEXT:    ret i64 [[TMP0]]
  29 //
  30 // CPP-CHECK-LABEL: @_Z15test_svcntw_patv(
  31 // CPP-CHECK-NEXT:  entry:
  32 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 0)
  33 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
  34 //
  35 uint64_t test_svcntw_pat()
  36 {
  37   return svcntw_pat(SV_POW2);
  38 }
  39
  40 // CHECK-LABEL: @test_svcntw_pat_1(
  41 // CHECK-NEXT:  entry:
  42 // CHECK-NEXT:    ret i64 1
  43 //
  44 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_1v(
  45 // CPP-CHECK-NEXT:  entry:
  46 // CPP-CHECK-NEXT:    ret i64 1
  47 //
  48 uint64_t test_svcntw_pat_1()
  49 {
  50   return svcntw_pat(SV_VL1);
  51 }
  52
  53 // CHECK-LABEL: @test_svcntw_pat_2(
  54 // CHECK-NEXT:  entry:
  55 // CHECK-NEXT:    ret i64 2
  56 //
  57 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_2v(
  58 // CPP-CHECK-NEXT:  entry:
  59 // CPP-CHECK-NEXT:    ret i64 2
  60 //
  61 uint64_t test_svcntw_pat_2()
  62 {
  63   return svcntw_pat(SV_VL2);
  64 }
  65
  66 // CHECK-LABEL: @test_svcntw_pat_3(
  67 // CHECK-NEXT:  entry:
  68 // CHECK-NEXT:    ret i64 3
  69 //
  70 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_3v(
  71 // CPP-CHECK-NEXT:  entry:
  72 // CPP-CHECK-NEXT:    ret i64 3
  73 //
  74 uint64_t test_svcntw_pat_3()
  75 {
  76   return svcntw_pat(SV_VL3);
  77 }
  78
  79 // CHECK-LABEL: @test_svcntw_pat_4(
  80 // CHECK-NEXT:  entry:
  81 // CHECK-NEXT:    ret i64 4
  82 //
  83 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_4v(
  84 // CPP-CHECK-NEXT:  entry:
  85 // CPP-CHECK-NEXT:    ret i64 4
  86 //
  87 uint64_t test_svcntw_pat_4()
  88 {
  89   return svcntw_pat(SV_VL4);
  90 }
  91
  92 // CHECK-LABEL: @test_svcntw_pat_5(
  93 // CHECK-NEXT:  entry:
  94 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 5)
  95 // CHECK-NEXT:    ret i64 [[TMP0]]
  96 //
  97 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_5v(
  98 // CPP-CHECK-NEXT:  entry:
  99 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 5)
 100 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 101 //
 102 uint64_t test_svcntw_pat_5()
 103 {
 104   return svcntw_pat(SV_VL5);
 105 }
 106
 107 // CHECK-LABEL: @test_svcntw_pat_6(
 108 // CHECK-NEXT:  entry:
 109 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 6)
 110 // CHECK-NEXT:    ret i64 [[TMP0]]
 111 //
 112 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_6v(
 113 // CPP-CHECK-NEXT:  entry:
 114 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 6)
 115 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 116 //
 117 uint64_t test_svcntw_pat_6()
 118 {
 119   return svcntw_pat(SV_VL6);
 120 }
 121
 122 // CHECK-LABEL: @test_svcntw_pat_7(
 123 // CHECK-NEXT:  entry:
 124 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 7)
 125 // CHECK-NEXT:    ret i64 [[TMP0]]
 126 //
 127 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_7v(
 128 // CPP-CHECK-NEXT:  entry:
 129 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 7)
 130 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 131 //
 132 uint64_t test_svcntw_pat_7()
 133 {
 134   return svcntw_pat(SV_VL7);
 135 }
 136
 137 // CHECK-LABEL: @test_svcntw_pat_8(
 138 // CHECK-NEXT:  entry:
 139 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 8)
 140 // CHECK-NEXT:    ret i64 [[TMP0]]
 141 //
 142 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_8v(
 143 // CPP-CHECK-NEXT:  entry:
 144 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 8)
 145 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 146 //
 147 uint64_t test_svcntw_pat_8()
 148 {
 149   return svcntw_pat(SV_VL8);
 150 }
 151
 152 // CHECK-LABEL: @test_svcntw_pat_9(
 153 // CHECK-NEXT:  entry:
 154 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 9)
 155 // CHECK-NEXT:    ret i64 [[TMP0]]
 156 //
 157 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_9v(
 158 // CPP-CHECK-NEXT:  entry:
 159 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 9)
 160 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 161 //
 162 uint64_t test_svcntw_pat_9()
 163 {
 164   return svcntw_pat(SV_VL16);
 165 }
 166
 167 // CHECK-LABEL: @test_svcntw_pat_10(
 168 // CHECK-NEXT:  entry:
 169 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 10)
 170 // CHECK-NEXT:    ret i64 [[TMP0]]
 171 //
 172 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_10v(
 173 // CPP-CHECK-NEXT:  entry:
 174 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 10)
 175 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 176 //
 177 uint64_t test_svcntw_pat_10()
 178 {
 179   return svcntw_pat(SV_VL32);
 180 }
 181
 182 // CHECK-LABEL: @test_svcntw_pat_11(
 183 // CHECK-NEXT:  entry:
 184 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 11)
 185 // CHECK-NEXT:    ret i64 [[TMP0]]
 186 //
 187 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_11v(
 188 // CPP-CHECK-NEXT:  entry:
 189 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 11)
 190 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 191 //
 192 uint64_t test_svcntw_pat_11()
 193 {
 194   return svcntw_pat(SV_VL64);
 195 }
 196
 197 // CHECK-LABEL: @test_svcntw_pat_12(
 198 // CHECK-NEXT:  entry:
 199 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 12)
 200 // CHECK-NEXT:    ret i64 [[TMP0]]
 201 //
 202 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_12v(
 203 // CPP-CHECK-NEXT:  entry:
 204 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 12)
 205 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 206 //
 207 uint64_t test_svcntw_pat_12()
 208 {
 209   return svcntw_pat(SV_VL128);
 210 }
 211
 212 // CHECK-LABEL: @test_svcntw_pat_13(
 213 // CHECK-NEXT:  entry:
 214 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 13)
 215 // CHECK-NEXT:    ret i64 [[TMP0]]
 216 //
 217 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_13v(
 218 // CPP-CHECK-NEXT:  entry:
 219 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 13)
 220 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 221 //
 222 uint64_t test_svcntw_pat_13()
 223 {
 224   return svcntw_pat(SV_VL256);
 225 }
 226
 227 // CHECK-LABEL: @test_svcntw_pat_14(
 228 // CHECK-NEXT:  entry:
 229 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 29)
 230 // CHECK-NEXT:    ret i64 [[TMP0]]
 231 //
 232 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_14v(
 233 // CPP-CHECK-NEXT:  entry:
 234 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 29)
 235 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 236 //
 237 uint64_t test_svcntw_pat_14()
 238 {
 239   return svcntw_pat(SV_MUL4);
 240 }
 241
 242 // CHECK-LABEL: @test_svcntw_pat_15(
 243 // CHECK-NEXT:  entry:
 244 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 30)
 245 // CHECK-NEXT:    ret i64 [[TMP0]]
 246 //
 247 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_15v(
 248 // CPP-CHECK-NEXT:  entry:
 249 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 30)
 250 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 251 //
 252 uint64_t test_svcntw_pat_15()
 253 {
 254   return svcntw_pat(SV_MUL3);
 255 }
 256
 257 // CHECK-LABEL: @test_svcntw_pat_16(
 258 // CHECK-NEXT:  entry:
 259 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
 260 // CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
 261 // CHECK-NEXT:    ret i64 [[TMP1]]
 262 //
 263 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_16v(
 264 // CPP-CHECK-NEXT:  entry:
 265 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
 266 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
 267 // CPP-CHECK-NEXT:    ret i64 [[TMP1]]
 268 //
 269 uint64_t test_svcntw_pat_16()
 270 {
 271   return svcntw_pat(SV_ALL);
 272 }