clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_index.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
   6 #include <arm_sve.h>
   7
   8 // CHECK-LABEL: @test_svindex_s8(
   9 // CHECK-NEXT:  entry:
  10 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
  11 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  12 //
  13 // CPP-CHECK-LABEL: @_Z15test_svindex_s8aa(
  14 // CPP-CHECK-NEXT:  entry:
  15 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
  16 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  17 //
  18 svint8_t test_svindex_s8(int8_t base, int8_t step)
  19 {
  20   return svindex_s8(base, step);
  21 }
  22
  23 // CHECK-LABEL: @test_svindex_s16(
  24 // CHECK-NEXT:  entry:
  25 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
  26 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  27 //
  28 // CPP-CHECK-LABEL: @_Z16test_svindex_s16ss(
  29 // CPP-CHECK-NEXT:  entry:
  30 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
  31 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  32 //
  33 svint16_t test_svindex_s16(int16_t base, int16_t step)
  34 {
  35   return svindex_s16(base, step);
  36 }
  37
  38 // CHECK-LABEL: @test_svindex_s32(
  39 // CHECK-NEXT:  entry:
  40 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
  41 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  42 //
  43 // CPP-CHECK-LABEL: @_Z16test_svindex_s32ii(
  44 // CPP-CHECK-NEXT:  entry:
  45 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
  46 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  47 //
  48 svint32_t test_svindex_s32(int32_t base, int32_t step)
  49 {
  50   return svindex_s32(base, step);
  51 }
  52
  53 // CHECK-LABEL: @test_svindex_s64(
  54 // CHECK-NEXT:  entry:
  55 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
  56 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  57 //
  58 // CPP-CHECK-LABEL: @_Z16test_svindex_s64ll(
  59 // CPP-CHECK-NEXT:  entry:
  60 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
  61 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  62 //
  63 svint64_t test_svindex_s64(int64_t base, int64_t step)
  64 {
  65   return svindex_s64(base, step);
  66 }
  67
  68 // CHECK-LABEL: @test_svindex_u8(
  69 // CHECK-NEXT:  entry:
  70 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
  71 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  72 //
  73 // CPP-CHECK-LABEL: @_Z15test_svindex_u8hh(
  74 // CPP-CHECK-NEXT:  entry:
  75 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
  76 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  77 //
  78 svuint8_t test_svindex_u8(uint8_t base, uint8_t step)
  79 {
  80   return svindex_u8(base, step);
  81 }
  82
  83 // CHECK-LABEL: @test_svindex_u16(
  84 // CHECK-NEXT:  entry:
  85 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
  86 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  87 //
  88 // CPP-CHECK-LABEL: @_Z16test_svindex_u16tt(
  89 // CPP-CHECK-NEXT:  entry:
  90 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
  91 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  92 //
  93 svuint16_t test_svindex_u16(uint16_t base, uint16_t step)
  94 {
  95   return svindex_u16(base, step);
  96 }
  97
  98 // CHECK-LABEL: @test_svindex_u32(
  99 // CHECK-NEXT:  entry:
 100 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
 101 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 102 //
 103 // CPP-CHECK-LABEL: @_Z16test_svindex_u32jj(
 104 // CPP-CHECK-NEXT:  entry:
 105 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
 106 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 107 //
 108 svuint32_t test_svindex_u32(uint32_t base, uint32_t step)
 109 {
 110   return svindex_u32(base, step);
 111 }
 112
 113 // CHECK-LABEL: @test_svindex_u64(
 114 // CHECK-NEXT:  entry:
 115 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
 116 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 117 //
 118 // CPP-CHECK-LABEL: @_Z16test_svindex_u64mm(
 119 // CPP-CHECK-NEXT:  entry:
 120 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
 121 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 122 //
 123 svuint64_t test_svindex_u64(uint64_t base, uint64_t step)
 124 {
 125   return svindex_u64(base, step);
 126 }