clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qcadd.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
   4 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
   5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
   6
   7 // REQUIRES: aarch64-registered-target
   8
   9 #include <arm_sve.h>
  10
  11 #ifdef SVE_OVERLOADED_FORMS
  12 // A simple used,unused... macro, long enough to represent any SVE builtin.
  13 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  14 #else
  15 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  16 #endif
  17
  18 // CHECK-LABEL: @test_svqcadd_s8(
  19 // CHECK-NEXT:  entry:
  20 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcadd.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 90)
  21 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  22 //
  23 // CPP-CHECK-LABEL: @_Z15test_svqcadd_s8u10__SVInt8_tS_(
  24 // CPP-CHECK-NEXT:  entry:
  25 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcadd.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 90)
  26 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  27 //
  28 svint8_t test_svqcadd_s8(svint8_t op1, svint8_t op2)
  29 {
  30   return SVE_ACLE_FUNC(svqcadd,_s8,,)(op1, op2, 90);
  31 }
  32
  33 // CHECK-LABEL: @test_svqcadd_s8_1(
  34 // CHECK-NEXT:  entry:
  35 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcadd.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 270)
  36 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  37 //
  38 // CPP-CHECK-LABEL: @_Z17test_svqcadd_s8_1u10__SVInt8_tS_(
  39 // CPP-CHECK-NEXT:  entry:
  40 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcadd.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 270)
  41 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  42 //
  43 svint8_t test_svqcadd_s8_1(svint8_t op1, svint8_t op2)
  44 {
  45   return SVE_ACLE_FUNC(svqcadd,_s8,,)(op1, op2, 270);
  46 }
  47
  48 // CHECK-LABEL: @test_svqcadd_s16(
  49 // CHECK-NEXT:  entry:
  50 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcadd.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 90)
  51 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  52 //
  53 // CPP-CHECK-LABEL: @_Z16test_svqcadd_s16u11__SVInt16_tS_(
  54 // CPP-CHECK-NEXT:  entry:
  55 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcadd.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 90)
  56 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  57 //
  58 svint16_t test_svqcadd_s16(svint16_t op1, svint16_t op2)
  59 {
  60   return SVE_ACLE_FUNC(svqcadd,_s16,,)(op1, op2, 90);
  61 }
  62
  63 // CHECK-LABEL: @test_svqcadd_s16_1(
  64 // CHECK-NEXT:  entry:
  65 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcadd.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 270)
  66 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  67 //
  68 // CPP-CHECK-LABEL: @_Z18test_svqcadd_s16_1u11__SVInt16_tS_(
  69 // CPP-CHECK-NEXT:  entry:
  70 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcadd.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 270)
  71 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  72 //
  73 svint16_t test_svqcadd_s16_1(svint16_t op1, svint16_t op2)
  74 {
  75   return SVE_ACLE_FUNC(svqcadd,_s16,,)(op1, op2, 270);
  76 }
  77
  78 // CHECK-LABEL: @test_svqcadd_s32(
  79 // CHECK-NEXT:  entry:
  80 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqcadd.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 90)
  81 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  82 //
  83 // CPP-CHECK-LABEL: @_Z16test_svqcadd_s32u11__SVInt32_tS_(
  84 // CPP-CHECK-NEXT:  entry:
  85 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqcadd.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 90)
  86 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  87 //
  88 svint32_t test_svqcadd_s32(svint32_t op1, svint32_t op2)
  89 {
  90   return SVE_ACLE_FUNC(svqcadd,_s32,,)(op1, op2, 90);
  91 }
  92
  93 // CHECK-LABEL: @test_svqcadd_s32_1(
  94 // CHECK-NEXT:  entry:
  95 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqcadd.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 270)
  96 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  97 //
  98 // CPP-CHECK-LABEL: @_Z18test_svqcadd_s32_1u11__SVInt32_tS_(
  99 // CPP-CHECK-NEXT:  entry:
 100 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqcadd.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 270)
 101 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 102 //
 103 svint32_t test_svqcadd_s32_1(svint32_t op1, svint32_t op2)
 104 {
 105   return SVE_ACLE_FUNC(svqcadd,_s32,,)(op1, op2, 270);
 106 }
 107
 108 // CHECK-LABEL: @test_svqcadd_s64(
 109 // CHECK-NEXT:  entry:
 110 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqcadd.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 90)
 111 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 112 //
 113 // CPP-CHECK-LABEL: @_Z16test_svqcadd_s64u11__SVInt64_tS_(
 114 // CPP-CHECK-NEXT:  entry:
 115 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqcadd.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 90)
 116 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 117 //
 118 svint64_t test_svqcadd_s64(svint64_t op1, svint64_t op2)
 119 {
 120   return SVE_ACLE_FUNC(svqcadd,_s64,,)(op1, op2, 90);
 121 }
 122
 123 // CHECK-LABEL: @test_svqcadd_s64_1(
 124 // CHECK-NEXT:  entry:
 125 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqcadd.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 270)
 126 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 127 //
 128 // CPP-CHECK-LABEL: @_Z18test_svqcadd_s64_1u11__SVInt64_tS_(
 129 // CPP-CHECK-NEXT:  entry:
 130 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqcadd.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 270)
 131 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 132 //
 133 svint64_t test_svqcadd_s64_1(svint64_t op1, svint64_t op2)
 134 {
 135   return SVE_ACLE_FUNC(svqcadd,_s64,,)(op1, op2, 270);
 136 }