clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdcmlah.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
   4 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
   5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
   6
   7 // REQUIRES: aarch64-registered-target
   8
   9 #include <arm_sve.h>
  10
  11 #ifdef SVE_OVERLOADED_FORMS
  12 // A simple used,unused... macro, long enough to represent any SVE builtin.
  13 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  14 #else
  15 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  16 #endif
  17
  18 // CHECK-LABEL: @test_svqrdcmlah_s8(
  19 // CHECK-NEXT:  entry:
  20 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)
  21 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  22 //
  23 // CPP-CHECK-LABEL: @_Z18test_svqrdcmlah_s8u10__SVInt8_tS_S_(
  24 // CPP-CHECK-NEXT:  entry:
  25 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)
  26 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  27 //
  28 svint8_t test_svqrdcmlah_s8(svint8_t op1, svint8_t op2, svint8_t op3)
  29 {
  30   return SVE_ACLE_FUNC(svqrdcmlah,_s8,,)(op1, op2, op3, 0);
  31 }
  32
  33 // CHECK-LABEL: @test_svqrdcmlah_s8_1(
  34 // CHECK-NEXT:  entry:
  35 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 90)
  36 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  37 //
  38 // CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_1u10__SVInt8_tS_S_(
  39 // CPP-CHECK-NEXT:  entry:
  40 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 90)
  41 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  42 //
  43 svint8_t test_svqrdcmlah_s8_1(svint8_t op1, svint8_t op2, svint8_t op3)
  44 {
  45   return SVE_ACLE_FUNC(svqrdcmlah,_s8,,)(op1, op2, op3, 90);
  46 }
  47
  48 // CHECK-LABEL: @test_svqrdcmlah_s8_2(
  49 // CHECK-NEXT:  entry:
  50 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 180)
  51 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  52 //
  53 // CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_2u10__SVInt8_tS_S_(
  54 // CPP-CHECK-NEXT:  entry:
  55 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 180)
  56 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  57 //
  58 svint8_t test_svqrdcmlah_s8_2(svint8_t op1, svint8_t op2, svint8_t op3)
  59 {
  60   return SVE_ACLE_FUNC(svqrdcmlah,_s8,,)(op1, op2, op3, 180);
  61 }
  62
  63 // CHECK-LABEL: @test_svqrdcmlah_s8_3(
  64 // CHECK-NEXT:  entry:
  65 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 270)
  66 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  67 //
  68 // CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_3u10__SVInt8_tS_S_(
  69 // CPP-CHECK-NEXT:  entry:
  70 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 270)
  71 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  72 //
  73 svint8_t test_svqrdcmlah_s8_3(svint8_t op1, svint8_t op2, svint8_t op3)
  74 {
  75   return SVE_ACLE_FUNC(svqrdcmlah,_s8,,)(op1, op2, op3, 270);
  76 }
  77
  78 // CHECK-LABEL: @test_svqrdcmlah_s16(
  79 // CHECK-NEXT:  entry:
  80 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)
  81 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  82 //
  83 // CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s16u11__SVInt16_tS_S_(
  84 // CPP-CHECK-NEXT:  entry:
  85 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)
  86 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  87 //
  88 svint16_t test_svqrdcmlah_s16(svint16_t op1, svint16_t op2, svint16_t op3)
  89 {
  90   return SVE_ACLE_FUNC(svqrdcmlah,_s16,,)(op1, op2, op3, 0);
  91 }
  92
  93 // CHECK-LABEL: @test_svqrdcmlah_s16_1(
  94 // CHECK-NEXT:  entry:
  95 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 90)
  96 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  97 //
  98 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_1u11__SVInt16_tS_S_(
  99 // CPP-CHECK-NEXT:  entry:
 100 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 90)
 101 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 102 //
 103 svint16_t test_svqrdcmlah_s16_1(svint16_t op1, svint16_t op2, svint16_t op3)
 104 {
 105   return SVE_ACLE_FUNC(svqrdcmlah,_s16,,)(op1, op2, op3, 90);
 106 }
 107
 108 // CHECK-LABEL: @test_svqrdcmlah_s16_2(
 109 // CHECK-NEXT:  entry:
 110 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 180)
 111 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 112 //
 113 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_2u11__SVInt16_tS_S_(
 114 // CPP-CHECK-NEXT:  entry:
 115 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 180)
 116 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 117 //
 118 svint16_t test_svqrdcmlah_s16_2(svint16_t op1, svint16_t op2, svint16_t op3)
 119 {
 120   return SVE_ACLE_FUNC(svqrdcmlah,_s16,,)(op1, op2, op3, 180);
 121 }
 122
 123 // CHECK-LABEL: @test_svqrdcmlah_s16_3(
 124 // CHECK-NEXT:  entry:
 125 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 270)
 126 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 127 //
 128 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_3u11__SVInt16_tS_S_(
 129 // CPP-CHECK-NEXT:  entry:
 130 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 270)
 131 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 132 //
 133 svint16_t test_svqrdcmlah_s16_3(svint16_t op1, svint16_t op2, svint16_t op3)
 134 {
 135   return SVE_ACLE_FUNC(svqrdcmlah,_s16,,)(op1, op2, op3, 270);
 136 }
 137
 138 // CHECK-LABEL: @test_svqrdcmlah_s32(
 139 // CHECK-NEXT:  entry:
 140 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)
 141 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 142 //
 143 // CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s32u11__SVInt32_tS_S_(
 144 // CPP-CHECK-NEXT:  entry:
 145 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)
 146 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 147 //
 148 svint32_t test_svqrdcmlah_s32(svint32_t op1, svint32_t op2, svint32_t op3)
 149 {
 150   return SVE_ACLE_FUNC(svqrdcmlah,_s32,,)(op1, op2, op3, 0);
 151 }
 152
 153 // CHECK-LABEL: @test_svqrdcmlah_s32_1(
 154 // CHECK-NEXT:  entry:
 155 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 90)
 156 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 157 //
 158 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_1u11__SVInt32_tS_S_(
 159 // CPP-CHECK-NEXT:  entry:
 160 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 90)
 161 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 162 //
 163 svint32_t test_svqrdcmlah_s32_1(svint32_t op1, svint32_t op2, svint32_t op3)
 164 {
 165   return SVE_ACLE_FUNC(svqrdcmlah,_s32,,)(op1, op2, op3, 90);
 166 }
 167
 168 // CHECK-LABEL: @test_svqrdcmlah_s32_2(
 169 // CHECK-NEXT:  entry:
 170 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 180)
 171 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 172 //
 173 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_2u11__SVInt32_tS_S_(
 174 // CPP-CHECK-NEXT:  entry:
 175 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 180)
 176 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 177 //
 178 svint32_t test_svqrdcmlah_s32_2(svint32_t op1, svint32_t op2, svint32_t op3)
 179 {
 180   return SVE_ACLE_FUNC(svqrdcmlah,_s32,,)(op1, op2, op3, 180);
 181 }
 182
 183 // CHECK-LABEL: @test_svqrdcmlah_s32_3(
 184 // CHECK-NEXT:  entry:
 185 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 270)
 186 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 187 //
 188 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_3u11__SVInt32_tS_S_(
 189 // CPP-CHECK-NEXT:  entry:
 190 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 270)
 191 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 192 //
 193 svint32_t test_svqrdcmlah_s32_3(svint32_t op1, svint32_t op2, svint32_t op3)
 194 {
 195   return SVE_ACLE_FUNC(svqrdcmlah,_s32,,)(op1, op2, op3, 270);
 196 }
 197
 198 // CHECK-LABEL: @test_svqrdcmlah_s64(
 199 // CHECK-NEXT:  entry:
 200 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)
 201 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 202 //
 203 // CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s64u11__SVInt64_tS_S_(
 204 // CPP-CHECK-NEXT:  entry:
 205 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)
 206 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 207 //
 208 svint64_t test_svqrdcmlah_s64(svint64_t op1, svint64_t op2, svint64_t op3)
 209 {
 210   return SVE_ACLE_FUNC(svqrdcmlah,_s64,,)(op1, op2, op3, 0);
 211 }
 212
 213 // CHECK-LABEL: @test_svqrdcmlah_s64_1(
 214 // CHECK-NEXT:  entry:
 215 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 90)
 216 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 217 //
 218 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_1u11__SVInt64_tS_S_(
 219 // CPP-CHECK-NEXT:  entry:
 220 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 90)
 221 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 222 //
 223 svint64_t test_svqrdcmlah_s64_1(svint64_t op1, svint64_t op2, svint64_t op3)
 224 {
 225   return SVE_ACLE_FUNC(svqrdcmlah,_s64,,)(op1, op2, op3, 90);
 226 }
 227
 228 // CHECK-LABEL: @test_svqrdcmlah_s64_2(
 229 // CHECK-NEXT:  entry:
 230 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 180)
 231 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 232 //
 233 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_2u11__SVInt64_tS_S_(
 234 // CPP-CHECK-NEXT:  entry:
 235 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 180)
 236 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 237 //
 238 svint64_t test_svqrdcmlah_s64_2(svint64_t op1, svint64_t op2, svint64_t op3)
 239 {
 240   return SVE_ACLE_FUNC(svqrdcmlah,_s64,,)(op1, op2, op3, 180);
 241 }
 242
 243 // CHECK-LABEL: @test_svqrdcmlah_s64_3(
 244 // CHECK-NEXT:  entry:
 245 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 270)
 246 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 247 //
 248 // CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_3u11__SVInt64_tS_S_(
 249 // CPP-CHECK-NEXT:  entry:
 250 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 270)
 251 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 252 //
 253 svint64_t test_svqrdcmlah_s64_3(svint64_t op1, svint64_t op2, svint64_t op3)
 254 {
 255   return SVE_ACLE_FUNC(svqrdcmlah,_s64,,)(op1, op2, op3, 270);
 256 }
 257
 258 // CHECK-LABEL: @test_svqrdcmlah_lane_s16(
 259 // CHECK-NEXT:  entry:
 260 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0, i32 0)
 261 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 262 //
 263 // CPP-CHECK-LABEL: @_Z24test_svqrdcmlah_lane_s16u11__SVInt16_tS_S_(
 264 // CPP-CHECK-NEXT:  entry:
 265 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0, i32 0)
 266 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 267 //
 268 svint16_t test_svqrdcmlah_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3)
 269 {
 270   return SVE_ACLE_FUNC(svqrdcmlah_lane,_s16,,)(op1, op2, op3, 0, 0);
 271 }
 272
 273 // CHECK-LABEL: @test_svqrdcmlah_lane_s16_1(
 274 // CHECK-NEXT:  entry:
 275 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3, i32 90)
 276 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 277 //
 278 // CPP-CHECK-LABEL: @_Z26test_svqrdcmlah_lane_s16_1u11__SVInt16_tS_S_(
 279 // CPP-CHECK-NEXT:  entry:
 280 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3, i32 90)
 281 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 282 //
 283 svint16_t test_svqrdcmlah_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3)
 284 {
 285   return SVE_ACLE_FUNC(svqrdcmlah_lane,_s16,,)(op1, op2, op3, 3, 90);
 286 }
 287
 288 // CHECK-LABEL: @test_svqrdcmlah_lane_s32(
 289 // CHECK-NEXT:  entry:
 290 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0, i32 180)
 291 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 292 //
 293 // CPP-CHECK-LABEL: @_Z24test_svqrdcmlah_lane_s32u11__SVInt32_tS_S_(
 294 // CPP-CHECK-NEXT:  entry:
 295 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0, i32 180)
 296 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 297 //
 298 svint32_t test_svqrdcmlah_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3)
 299 {
 300   return SVE_ACLE_FUNC(svqrdcmlah_lane,_s32,,)(op1, op2, op3, 0, 180);
 301 }
 302
 303 // CHECK-LABEL: @test_svqrdcmlah_lane_s32_1(
 304 // CHECK-NEXT:  entry:
 305 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 1, i32 270)
 306 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 307 //
 308 // CPP-CHECK-LABEL: @_Z26test_svqrdcmlah_lane_s32_1u11__SVInt32_tS_S_(
 309 // CPP-CHECK-NEXT:  entry:
 310 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 1, i32 270)
 311 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 312 //
 313 svint32_t test_svqrdcmlah_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3)
 314 {
 315   return SVE_ACLE_FUNC(svqrdcmlah_lane,_s32,,)(op1, op2, op3, 1, 270);
 316 }