clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_sclamp.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
   4 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
   6 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   7 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
   8 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   9 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
  10 // RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
  11 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
  12 // RUN:   -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
  13
  14 #include <arm_sve.h>
  15
  16 #ifdef SVE_OVERLOADED_FORMS
  17 // A simple used,unused... macro, long enough to represent any SVE builtin.
  18 #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
  19 #else
  20 #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
  21 #endif
  22
  23 // CHECK-LABEL: @test_svclamp_s8(
  24 // CHECK-NEXT:  entry:
  25 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])
  26 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  27 //
  28 // CPP-CHECK-LABEL: @_Z15test_svclamp_s8u10__SVInt8_tS_S_(
  29 // CPP-CHECK-NEXT:  entry:
  30 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])
  31 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  32 //
  33 svint8_t test_svclamp_s8(svint8_t op1, svint8_t op2, svint8_t op3) {
  34   return SVE_ACLE_FUNC(svclamp, _s8, , )(op1, op2, op3);
  35 }
  36
  37 // CHECK-LABEL: @test_svclamp_s16(
  38 // CHECK-NEXT:  entry:
  39 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])
  40 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  41 //
  42 // CPP-CHECK-LABEL: @_Z16test_svclamp_s16u11__SVInt16_tS_S_(
  43 // CPP-CHECK-NEXT:  entry:
  44 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])
  45 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  46 //
  47 svint16_t test_svclamp_s16(svint16_t op1, svint16_t op2, svint16_t op3) {
  48   return SVE_ACLE_FUNC(svclamp, _s16, , )(op1, op2, op3);
  49 }
  50
  51 // CHECK-LABEL: @test_svclamp_s32(
  52 // CHECK-NEXT:  entry:
  53 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]])
  54 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  55 //
  56 // CPP-CHECK-LABEL: @_Z16test_svclamp_s32u11__SVInt32_tS_S_(
  57 // CPP-CHECK-NEXT:  entry:
  58 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]])
  59 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  60 //
  61 svint32_t test_svclamp_s32(svint32_t op1, svint32_t op2, svint32_t op3) {
  62   return SVE_ACLE_FUNC(svclamp, _s32, , )(op1, op2, op3);
  63 }
  64
  65 // CHECK-LABEL: @test_svclamp_s64(
  66 // CHECK-NEXT:  entry:
  67 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]])
  68 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  69 //
  70 // CPP-CHECK-LABEL: @_Z16test_svclamp_s64u11__SVInt64_tS_S_(
  71 // CPP-CHECK-NEXT:  entry:
  72 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]])
  73 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  74 //
  75 svint64_t test_svclamp_s64(svint64_t op1, svint64_t op2, svint64_t op3) {
  76   return SVE_ACLE_FUNC(svclamp, _s64, , )(op1, op2, op3);
  77 }
  78