clang/test/CodeGen/attr-arm-sve-vector-bits-call.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=4 -mvscale-max=4 -S -O1 -emit-llvm -o - %s | FileCheck %s
   3
   4 // REQUIRES: aarch64-registered-target
   5
   6 #include <arm_sve.h>
   7
   8 #define N __ARM_FEATURE_SVE_BITS
   9
  10 typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
  11 typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
  12 typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
  13
  14 //===----------------------------------------------------------------------===//
  15 // Test caller/callee with VLST <-> VLAT
  16 //===----------------------------------------------------------------------===//
  17
  18 // CHECK-LABEL: @sizeless_callee(
  19 // CHECK-NEXT:  entry:
  20 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X:%.*]]
  21 //
  22 svint32_t sizeless_callee(svint32_t x) {
  23   return x;
  24 }
  25
  26 // CHECK-LABEL: @fixed_caller(
  27 // CHECK-NEXT:  entry:
  28 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X_COERCE:%.*]]
  29 //
  30 fixed_int32_t fixed_caller(fixed_int32_t x) {
  31   return sizeless_callee(x);
  32 }
  33
  34 // CHECK-LABEL: @fixed_callee(
  35 // CHECK-NEXT:  entry:
  36 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X_COERCE:%.*]]
  37 //
  38 fixed_int32_t fixed_callee(fixed_int32_t x) {
  39   return x;
  40 }
  41
  42 // CHECK-LABEL: @sizeless_caller(
  43 // CHECK-NEXT:  entry:
  44 // CHECK-NEXT:    ret <vscale x 4 x i32> [[X:%.*]]
  45 //
  46 svint32_t sizeless_caller(svint32_t x) {
  47   return fixed_callee(x);
  48 }
  49
  50 //===----------------------------------------------------------------------===//
  51 // fixed, fixed
  52 //===----------------------------------------------------------------------===//
  53
  54 // CHECK-LABEL: @call_int32_ff(
  55 // CHECK-NEXT:  entry:
  56 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
  57 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1_COERCE:%.*]], <vscale x 4 x i32> [[OP2_COERCE:%.*]]
  58 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  59 //
  60 fixed_int32_t call_int32_ff(svbool_t pg, fixed_int32_t op1, fixed_int32_t op2) {
  61   return svsel(pg, op1, op2);
  62 }
  63
  64 // CHECK-LABEL: @call_float64_ff(
  65 // CHECK-NEXT:  entry:
  66 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
  67 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1_COERCE:%.*]], <vscale x 2 x double> [[OP2_COERCE:%.*]]
  68 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
  69 //
  70 fixed_float64_t call_float64_ff(svbool_t pg, fixed_float64_t op1, fixed_float64_t op2) {
  71   return svsel(pg, op1, op2);
  72 }
  73
  74 // CHECK-LABEL: @call_bool_ff(
  75 // CHECK-NEXT:  entry:
  76 // CHECK-NEXT:    [[TMP2:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[TMP1:%.*]]
  77 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP2]]
  78 //
  79 fixed_bool_t call_bool_ff(svbool_t pg, fixed_bool_t op1, fixed_bool_t op2) {
  80   return svsel(pg, op1, op2);
  81 }
  82
  83 //===----------------------------------------------------------------------===//
  84 // fixed, scalable
  85 //===----------------------------------------------------------------------===//
  86
  87 // CHECK-LABEL: @call_int32_fs(
  88 // CHECK-NEXT:  entry:
  89 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
  90 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1_COERCE:%.*]], <vscale x 4 x i32> [[OP2:%.*]]
  91 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  92 //
  93 fixed_int32_t call_int32_fs(svbool_t pg, fixed_int32_t op1, svint32_t op2) {
  94   return svsel(pg, op1, op2);
  95 }
  96
  97 // CHECK-LABEL: @call_float64_fs(
  98 // CHECK-NEXT:  entry:
  99 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 100 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1_COERCE:%.*]], <vscale x 2 x double> [[OP2:%.*]]
 101 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 102 //
 103 fixed_float64_t call_float64_fs(svbool_t pg, fixed_float64_t op1, svfloat64_t op2) {
 104   return svsel(pg, op1, op2);
 105 }
 106
 107 // CHECK-LABEL: @call_bool_fs(
 108 // CHECK-NEXT:  entry:
 109 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[OP2:%.*]]
 110 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 111 //
 112 fixed_bool_t call_bool_fs(svbool_t pg, fixed_bool_t op1, svbool_t op2) {
 113   return svsel(pg, op1, op2);
 114 }
 115
 116 //===----------------------------------------------------------------------===//
 117 // scalable, scalable
 118 //===----------------------------------------------------------------------===//
 119
 120 // CHECK-LABEL: @call_int32_ss(
 121 // CHECK-NEXT:  entry:
 122 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 123 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]
 124 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 125 //
 126 fixed_int32_t call_int32_ss(svbool_t pg, svint32_t op1, svint32_t op2) {
 127   return svsel(pg, op1, op2);
 128 }
 129
 130 // CHECK-LABEL: @call_float64_ss(
 131 // CHECK-NEXT:  entry:
 132 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 133 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]
 134 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 135 //
 136 fixed_float64_t call_float64_ss(svbool_t pg, svfloat64_t op1, svfloat64_t op2) {
 137   return svsel(pg, op1, op2);
 138 }
 139
 140 // CHECK-LABEL: @call_bool_ss(
 141 // CHECK-NEXT:  entry:
 142 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]
 143 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 144 //
 145 fixed_bool_t call_bool_ss(svbool_t pg, svbool_t op1, svbool_t op2) {
 146   return svsel(pg, op1, op2);
 147 }