clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -S -O1 -emit-llvm -o - %s | FileCheck %s
   3
   4 // REQUIRES: riscv-registered-target
   5
   6 #include <riscv_vector.h>
   7
   8 typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
   9 typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  10
  11 //===----------------------------------------------------------------------===//
  12 // Test caller/callee with VLST <-> VLAT
  13 //===----------------------------------------------------------------------===//
  14
  15 // CHECK-LABEL: @sizeless_callee(
  16 // CHECK-NEXT:  entry:
  17 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X:%.*]]
  18 //
  19 vint32m1_t sizeless_callee(vint32m1_t x) {
  20   return x;
  21 }
  22
  23 // CHECK-LABEL: @fixed_caller(
  24 // CHECK-NEXT:  entry:
  25 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X_COERCE:%.*]]
  26 //
  27 fixed_int32m1_t fixed_caller(fixed_int32m1_t x) {
  28   return sizeless_callee(x);
  29 }
  30
  31 // CHECK-LABEL: @fixed_callee(
  32 // CHECK-NEXT:  entry:
  33 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X_COERCE:%.*]]
  34 //
  35 fixed_int32m1_t fixed_callee(fixed_int32m1_t x) {
  36   return x;
  37 }
  38
  39 // CHECK-LABEL: @sizeless_caller(
  40 // CHECK-NEXT:  entry:
  41 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X:%.*]]
  42 //
  43 vint32m1_t sizeless_caller(vint32m1_t x) {
  44   return fixed_callee(x);
  45 }
  46
  47 //===----------------------------------------------------------------------===//
  48 // fixed, fixed
  49 //===----------------------------------------------------------------------===//
  50
  51 // CHECK-LABEL: @call_int32_ff(
  52 // CHECK-NEXT:  entry:
  53 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1_COERCE:%.*]], <vscale x 2 x i32> [[OP2_COERCE:%.*]], i64 8)
  54 // CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  55 //
  56 fixed_int32m1_t call_int32_ff(fixed_int32m1_t op1, fixed_int32m1_t op2) {
  57   return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
  58 }
  59
  60 // CHECK-LABEL: @call_float64_ff(
  61 // CHECK-NEXT:  entry:
  62 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1_COERCE:%.*]], <vscale x 1 x double> [[OP2_COERCE:%.*]], i64 7, i64 4)
  63 // CHECK-NEXT:    ret <vscale x 1 x double> [[TMP0]]
  64 //
  65 fixed_float64m1_t call_float64_ff(fixed_float64m1_t op1, fixed_float64m1_t op2) {
  66   return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
  67 }
  68
  69 //===----------------------------------------------------------------------===//
  70 // fixed, scalable
  71 //===----------------------------------------------------------------------===//
  72
  73 // CHECK-LABEL: @call_int32_fs(
  74 // CHECK-NEXT:  entry:
  75 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1_COERCE:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 8)
  76 // CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  77 //
  78 fixed_int32m1_t call_int32_fs(fixed_int32m1_t op1, vint32m1_t op2) {
  79   return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
  80 }
  81
  82 // CHECK-LABEL: @call_float64_fs(
  83 // CHECK-NEXT:  entry:
  84 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1_COERCE:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 7, i64 4)
  85 // CHECK-NEXT:    ret <vscale x 1 x double> [[TMP0]]
  86 //
  87 fixed_float64m1_t call_float64_fs(fixed_float64m1_t op1, vfloat64m1_t op2) {
  88   return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
  89 }
  90
  91 //===----------------------------------------------------------------------===//
  92 // scalable, scalable
  93 //===----------------------------------------------------------------------===//
  94
  95 // CHECK-LABEL: @call_int32_ss(
  96 // CHECK-NEXT:  entry:
  97 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 8)
  98 // CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  99 //
 100 fixed_int32m1_t call_int32_ss(vint32m1_t op1, vint32m1_t op2) {
 101   return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
 102 }
 103
 104 // CHECK-LABEL: @call_float64_ss(
 105 // CHECK-NEXT:  entry:
 106 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 7, i64 4)
 107 // CHECK-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 108 //
 109 fixed_float64m1_t call_float64_ss(vfloat64m1_t op1, vfloat64m1_t op2) {
 110   return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
 111 }