clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -S -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
   3
   4 // REQUIRES: riscv-registered-target
   5
   6 #include <riscv_vector.h>
   7
   8 typedef __rvv_int8m1_t vint8m1_t;
   9 typedef __rvv_uint8m1_t vuint8m1_t;
  10 typedef __rvv_int16m1_t vint16m1_t;
  11 typedef __rvv_uint16m1_t vuint16m1_t;
  12 typedef __rvv_int32m1_t vint32m1_t;
  13 typedef __rvv_uint32m1_t vuint32m1_t;
  14 typedef __rvv_int64m1_t vint64m1_t;
  15 typedef __rvv_uint64m1_t vuint64m1_t;
  16 typedef __rvv_float32m1_t vfloat32m1_t;
  17 typedef __rvv_float64m1_t vfloat64m1_t;
  18
  19 typedef __rvv_int8m2_t vint8m2_t;
  20 typedef __rvv_uint8m2_t vuint8m2_t;
  21 typedef __rvv_int16m2_t vint16m2_t;
  22 typedef __rvv_uint16m2_t vuint16m2_t;
  23 typedef __rvv_int32m2_t vint32m2_t;
  24 typedef __rvv_uint32m2_t vuint32m2_t;
  25 typedef __rvv_int64m2_t vint64m2_t;
  26 typedef __rvv_uint64m2_t vuint64m2_t;
  27 typedef __rvv_float32m2_t vfloat32m2_t;
  28 typedef __rvv_float64m2_t vfloat64m2_t;
  29
  30 typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  31 typedef vint32m2_t fixed_int32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * 2)));
  32
  33 fixed_int32m1_t global_vec;
  34 fixed_int32m2_t global_vec_m2;
  35
  36 // CHECK-LABEL: @test_ptr_to_global(
  37 // CHECK-NEXT:  entry:
  38 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <8 x i32>, align 8
  39 // CHECK-NEXT:    [[GLOBAL_VEC_PTR:%.*]] = alloca ptr, align 8
  40 // CHECK-NEXT:    store ptr @global_vec, ptr [[GLOBAL_VEC_PTR]], align 8
  41 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[GLOBAL_VEC_PTR]], align 8
  42 // CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i32>, ptr [[TMP0]], align 8
  43 // CHECK-NEXT:    store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
  44 // CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
  45 // CHECK-NEXT:    [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP2]], i64 0)
  46 // CHECK-NEXT:    ret <vscale x 2 x i32> [[CAST_SCALABLE]]
  47 //
  48 fixed_int32m1_t test_ptr_to_global() {
  49   fixed_int32m1_t *global_vec_ptr;
  50   global_vec_ptr = &global_vec;
  51   return *global_vec_ptr;
  52 }
  53
  54 //
  55 // Test casting pointer from fixed-length array to scalable vector.
  56 // CHECK-LABEL: @array_arg(
  57 // CHECK-NEXT:  entry:
  58 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <8 x i32>, align 8
  59 // CHECK-NEXT:    [[ARR_ADDR:%.*]] = alloca ptr, align 8
  60 // CHECK-NEXT:    store ptr [[ARR:%.*]], ptr [[ARR_ADDR]], align 8
  61 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
  62 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds <8 x i32>, ptr [[TMP0]], i64 0
  63 // CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 8
  64 // CHECK-NEXT:    store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
  65 // CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
  66 // CHECK-NEXT:    [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP2]], i64 0)
  67 // CHECK-NEXT:    ret <vscale x 2 x i32> [[CAST_SCALABLE]]
  68 //
  69 fixed_int32m1_t array_arg(fixed_int32m1_t arr[]) {
  70   return arr[0];
  71 }
  72
  73 // CHECK-LABEL: @test_cast(
  74 // CHECK-NEXT:  entry:
  75 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <8 x i32>, align 8
  76 // CHECK-NEXT:    [[VEC_ADDR:%.*]] = alloca <vscale x 2 x i32>, align 4
  77 // CHECK-NEXT:    store <vscale x 2 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4
  78 // CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i32>, ptr @global_vec, align 8
  79 // CHECK-NEXT:    [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP0]], i64 0)
  80 // CHECK-NEXT:    [[TMP1:%.*]] = load <vscale x 2 x i32>, ptr [[VEC_ADDR]], align 4
  81 // CHECK-NEXT:    [[TMP2:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[CAST_SCALABLE]], <vscale x 2 x i32> [[TMP1]], i64 8)
  82 // CHECK-NEXT:    [[CAST_FIXED:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TMP2]], i64 0)
  83 // CHECK-NEXT:    store <8 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8
  84 // CHECK-NEXT:    [[TMP3:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
  85 // CHECK-NEXT:    [[CAST_SCALABLE1:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TMP3]], i64 0)
  86 // CHECK-NEXT:    ret <vscale x 2 x i32> [[CAST_SCALABLE1]]
  87 //
  88 fixed_int32m1_t test_cast(vint32m1_t vec) {
  89   return __riscv_vadd(global_vec, vec, __riscv_v_fixed_vlen/32);
  90 }
  91
  92 // CHECK-LABEL: @test_ptr_to_global_m2(
  93 // CHECK-NEXT:  entry:
  94 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <16 x i32>, align 8
  95 // CHECK-NEXT:    [[GLOBAL_VEC_PTR:%.*]] = alloca ptr, align 8
  96 // CHECK-NEXT:    store ptr @global_vec_m2, ptr [[GLOBAL_VEC_PTR]], align 8
  97 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[GLOBAL_VEC_PTR]], align 8
  98 // CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i32>, ptr [[TMP0]], align 8
  99 // CHECK-NEXT:    store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 100 // CHECK-NEXT:    [[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
 101 // CHECK-NEXT:    [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP2]], i64 0)
 102 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CAST_SCALABLE]]
 103 //
 104 fixed_int32m2_t test_ptr_to_global_m2() {
 105   fixed_int32m2_t *global_vec_ptr;
 106   global_vec_ptr = &global_vec_m2;
 107   return *global_vec_ptr;
 108 }
 109
 110 //
 111 // Test casting pointer from fixed-length array to scalable vector.
 112 // CHECK-LABEL: @array_arg_m2(
 113 // CHECK-NEXT:  entry:
 114 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <16 x i32>, align 8
 115 // CHECK-NEXT:    [[ARR_ADDR:%.*]] = alloca ptr, align 8
 116 // CHECK-NEXT:    store ptr [[ARR:%.*]], ptr [[ARR_ADDR]], align 8
 117 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
 118 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, ptr [[TMP0]], i64 0
 119 // CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i32>, ptr [[ARRAYIDX]], align 8
 120 // CHECK-NEXT:    store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 121 // CHECK-NEXT:    [[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
 122 // CHECK-NEXT:    [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP2]], i64 0)
 123 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CAST_SCALABLE]]
 124 //
 125 fixed_int32m2_t array_arg_m2(fixed_int32m2_t arr[]) {
 126   return arr[0];
 127 }
 128
 129 // CHECK-LABEL: @test_cast_m2(
 130 // CHECK-NEXT:  entry:
 131 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <16 x i32>, align 8
 132 // CHECK-NEXT:    [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 4
 133 // CHECK-NEXT:    store <vscale x 4 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4
 134 // CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i32>, ptr @global_vec_m2, align 8
 135 // CHECK-NEXT:    [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP0]], i64 0)
 136 // CHECK-NEXT:    [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[VEC_ADDR]], align 4
 137 // CHECK-NEXT:    [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[CAST_SCALABLE]], <vscale x 4 x i32> [[TMP1]], i64 16)
 138 // CHECK-NEXT:    [[CAST_FIXED:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP2]], i64 0)
 139 // CHECK-NEXT:    store <16 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8
 140 // CHECK-NEXT:    [[TMP3:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
 141 // CHECK-NEXT:    [[CAST_SCALABLE1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP3]], i64 0)
 142 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CAST_SCALABLE1]]
 143 //
 144 fixed_int32m2_t test_cast_m2(vint32m2_t vec) {
 145   return __riscv_vadd(global_vec_m2, vec, __riscv_v_fixed_vlen/16);
 146 }