clang/test/CodeGen/ppc-vec_ct-truncate.c

   1 // REQUIRES: powerpc-registered-target
   2 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
   3 // RUN:   -flax-vector-conversions=all -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
   4 // RUN:   -target-cpu pwr7 | FileCheck %s
   5 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
   6 // RUN:   -flax-vector-conversions=all -triple powerpc64-unknown-linux-gnu -emit-llvm %s -o - \
   7 // RUN:   -target-cpu pwr8 | FileCheck %s
   8 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
   9 // RUN:   -flax-vector-conversions=all -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
  10 // RUN:   -target-cpu pwr8 | FileCheck %s
  11 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
  12 // RUN:   -flax-vector-conversions=all -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
  13 // RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr7 | FileCheck %s
  14 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
  15 // RUN:   -flax-vector-conversions=all -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
  16 // RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s
  17
  18 #include <altivec.h>
  19 vector double a1 = {-1.234e-5, 1.2345};
  20 vector signed int res_vsi;
  21 vector float vf1 = {0.234, 1.234, 2.345, 3.456};
  22 vector signed int vsi1 = {1, 2, 3, 4};
  23 vector double res_vd;
  24 vector float res_vf;
  25 vector signed long long res_vsll;
  26 vector unsigned long long res_vull;
  27 void test(void) {
  28   // CHECK-LABEL: @test(
  29   // CHECK-NEXT:  entry:
  30
  31   res_vsi = vec_cts(a1, 31);
  32   //  CHECK:       [[TMP0:%.*]] = load <2 x double>, ptr @a1, align 16
  33   //  CHECK-NEXT:  fmul <2 x double> [[TMP0]], <double 0x41E0000000000000, double 0x41E0000000000000>
  34
  35   res_vsi = vec_cts(a1, 500);
  36   // CHECK:        [[TMP4:%.*]] = load <2 x double>, ptr @a1, align 16
  37   // CHECK-NEXT:   fmul <2 x double> [[TMP4]], <double 0x4130000000000000, double 0x4130000000000000>
  38
  39   res_vsi = vec_ctu(vf1, 31);
  40   // CHECK:        [[TMP8:%.*]] = load <4 x float>, ptr @vf1, align 16
  41   // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP8]], i32 31)
  42
  43   res_vsi = vec_ctu(vf1, 500);
  44   // CHECK:        [[TMP10:%.*]] = load <4 x float>, ptr @vf1, align 16
  45   // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP10]], i32 20)
  46
  47   res_vull = vec_ctul(vf1, 31);
  48   // CHECK:        [[TMP12:%.*]] = load <4 x float>, ptr @vf1, align 16
  49   // CHECK-NEXT:   fmul <4 x float> [[TMP12]], <float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000>
  50
  51   res_vull = vec_ctul(vf1, 500);
  52   // CHECK:        [[TMP21:%.*]] = load <4 x float>, ptr @vf1, align 16
  53   // CHECK-NEXT:   fmul <4 x float> [[TMP21]], <float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000>
  54
  55   res_vsll = vec_ctsl(vf1, 31);
  56   // CHECK:        [[TMP30:%.*]] = load <4 x float>, ptr @vf1, align 16
  57   // CHECK-NEXT:   fmul <4 x float> [[TMP30]], <float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000>
  58
  59   res_vsll = vec_ctsl(vf1, 500);
  60   // CHECK:        [[TMP39:%.*]] = load <4 x float>, ptr @vf1, align 16
  61   // CHECK-NEXT:   fmul <4 x float> [[TMP39]], <float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000>
  62
  63   res_vf = vec_ctf(vsi1, 31);
  64   // CHECK:        [[TMP48:%.*]] = load <4 x i32>, ptr @vsi1, align 16
  65   // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP48]], i32 31)
  66
  67   res_vf = vec_ctf(vsi1, 500);
  68   // CHECK:        [[TMP50:%.*]] = load <4 x i32>, ptr @vsi1, align 16
  69   // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP50]], i32 20)
  70
  71   res_vd = vec_ctd(vsi1, 31);
  72   // CHECK:        [[TMP53:%.*]] = load <4 x i32>, ptr @vsi1, align 16
  73   // CHECK:        [[TMP83:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP82:%.*]])
  74   // CHECK-NEXT:   fmul <2 x double> [[TMP83]], <double 0x3E00000000000000, double 0x3E00000000000000>
  75
  76   res_vd = vec_ctd(vsi1, 500);
  77   // CHECK:        [[TMP84:%.*]] = load <4 x i32>, ptr @vsi1, align 16
  78   // CHECK:        [[TMP115:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP114:%.*]])
  79   // CHECK-NEXT:   fmul <2 x double> [[TMP115]], <double 0x3EB0000000000000, double 0x3EB0000000000000>
  80 }