clang/test/CodeGen/riscv-rvv-vls-subscript-ops.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
   3 // RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
   4 // RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \
   5 // RUN: opt -S -passes=sroa | FileCheck %s
   6
   7 // REQUIRES: riscv-registered-target
   8
   9 #include <stddef.h>
  10 #include <stdint.h>
  11
  12 typedef __rvv_int8m1_t vint8m1_t;
  13 typedef __rvv_uint8m1_t vuint8m1_t;
  14 typedef __rvv_int16m1_t vint16m1_t;
  15 typedef __rvv_uint16m1_t vuint16m1_t;
  16 typedef __rvv_int32m1_t vint32m1_t;
  17 typedef __rvv_uint32m1_t vuint32m1_t;
  18 typedef __rvv_int64m1_t vint64m1_t;
  19 typedef __rvv_uint64m1_t vuint64m1_t;
  20 typedef __rvv_float32m1_t vfloat32m1_t;
  21 typedef __rvv_float64m1_t vfloat64m1_t;
  22
  23 typedef vint8m1_t fixed_int8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  24 typedef vint16m1_t fixed_int16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  25 typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  26 typedef vint64m1_t fixed_int64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  27
  28 typedef vuint8m1_t fixed_uint8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  29 typedef vuint16m1_t fixed_uint16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  30 typedef vuint32m1_t fixed_uint32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  31 typedef vuint64m1_t fixed_uint64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  32
  33 typedef vfloat32m1_t fixed_float32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  34 typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  35
  36 // CHECK-LABEL: @subscript_int8(
  37 // CHECK-NEXT:  entry:
  38 // CHECK-NEXT:    [[A:%.*]] = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> [[A_COERCE:%.*]], i64 0)
  39 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <32 x i8> [[A]], i64 [[B:%.*]]
  40 // CHECK-NEXT:    ret i8 [[VECEXT]]
  41 //
  42 int8_t subscript_int8(fixed_int8m1_t a, size_t b) {
  43   return a[b];
  44 }
  45
  46 // CHECK-LABEL: @subscript_uint8(
  47 // CHECK-NEXT:  entry:
  48 // CHECK-NEXT:    [[A:%.*]] = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> [[A_COERCE:%.*]], i64 0)
  49 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <32 x i8> [[A]], i64 [[B:%.*]]
  50 // CHECK-NEXT:    ret i8 [[VECEXT]]
  51 //
  52 uint8_t subscript_uint8(fixed_uint8m1_t a, size_t b) {
  53   return a[b];
  54 }
  55
  56 // CHECK-LABEL: @subscript_int16(
  57 // CHECK-NEXT:  entry:
  58 // CHECK-NEXT:    [[A:%.*]] = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> [[A_COERCE:%.*]], i64 0)
  59 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <16 x i16> [[A]], i64 [[B:%.*]]
  60 // CHECK-NEXT:    ret i16 [[VECEXT]]
  61 //
  62 int16_t subscript_int16(fixed_int16m1_t a, size_t b) {
  63   return a[b];
  64 }
  65
  66 // CHECK-LABEL: @subscript_uint16(
  67 // CHECK-NEXT:  entry:
  68 // CHECK-NEXT:    [[A:%.*]] = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> [[A_COERCE:%.*]], i64 0)
  69 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <16 x i16> [[A]], i64 [[B:%.*]]
  70 // CHECK-NEXT:    ret i16 [[VECEXT]]
  71 //
  72 uint16_t subscript_uint16(fixed_uint16m1_t a, size_t b) {
  73   return a[b];
  74 }
  75
  76 // CHECK-LABEL: @subscript_int32(
  77 // CHECK-NEXT:  entry:
  78 // CHECK-NEXT:    [[A:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[A_COERCE:%.*]], i64 0)
  79 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x i32> [[A]], i64 [[B:%.*]]
  80 // CHECK-NEXT:    ret i32 [[VECEXT]]
  81 //
  82 int32_t subscript_int32(fixed_int32m1_t a, size_t b) {
  83   return a[b];
  84 }
  85
  86 // CHECK-LABEL: @subscript_uint32(
  87 // CHECK-NEXT:  entry:
  88 // CHECK-NEXT:    [[A:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[A_COERCE:%.*]], i64 0)
  89 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x i32> [[A]], i64 [[B:%.*]]
  90 // CHECK-NEXT:    ret i32 [[VECEXT]]
  91 //
  92 uint32_t subscript_uint32(fixed_uint32m1_t a, size_t b) {
  93   return a[b];
  94 }
  95
  96 // CHECK-LABEL: @subscript_int64(
  97 // CHECK-NEXT:  entry:
  98 // CHECK-NEXT:    [[A:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> [[A_COERCE:%.*]], i64 0)
  99 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <4 x i64> [[A]], i64 [[B:%.*]]
 100 // CHECK-NEXT:    ret i64 [[VECEXT]]
 101 //
 102 int64_t subscript_int64(fixed_int64m1_t a, size_t b) {
 103   return a[b];
 104 }
 105
 106 // CHECK-LABEL: @subscript_uint64(
 107 // CHECK-NEXT:  entry:
 108 // CHECK-NEXT:    [[A:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> [[A_COERCE:%.*]], i64 0)
 109 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <4 x i64> [[A]], i64 [[B:%.*]]
 110 // CHECK-NEXT:    ret i64 [[VECEXT]]
 111 //
 112 uint64_t subscript_uint64(fixed_uint64m1_t a, size_t b) {
 113   return a[b];
 114 }
 115
 116 // CHECK-LABEL: @subscript_float32(
 117 // CHECK-NEXT:  entry:
 118 // CHECK-NEXT:    [[A:%.*]] = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> [[A_COERCE:%.*]], i64 0)
 119 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x float> [[A]], i64 [[B:%.*]]
 120 // CHECK-NEXT:    ret float [[VECEXT]]
 121 //
 122 float subscript_float32(fixed_float32m1_t a, size_t b) {
 123   return a[b];
 124 }
 125
 126 // CHECK-LABEL: @subscript_float64(
 127 // CHECK-NEXT:  entry:
 128 // CHECK-NEXT:    [[A:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> [[A_COERCE:%.*]], i64 0)
 129 // CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <4 x double> [[A]], i64 [[B:%.*]]
 130 // CHECK-NEXT:    ret double [[VECEXT]]
 131 //
 132 double subscript_float64(fixed_float64m1_t a, size_t b) {
 133   return a[b];
 134 }