clang/test/CodeGenCXX/pragma-loop-safety.cpp

   1 // RUN: %clang_cc1 -triple x86_64-apple-darwin -std=c++11 -emit-llvm -o - %s | FileCheck %s
   2
   3 // Verify assume_safety vectorization is recognized.
   4 void vectorize_test(int *List, int Length) {
   5 // CHECK: define {{.*}} @_Z14vectorize_test
   6 // CHECK: [[LOAD1_IV:.+]] = load i32, ptr [[IV1:[^,]+]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_2:[0-9]+]]
   7 // CHECK-NEXT: [[LOAD1_LEN:.+]] = load i32, ptr [[LEN1:.+]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_2]]
   8 // CHECK-NEXT: [[CMP1:.+]] = icmp slt i32[[LOAD1_IV]],[[LOAD1_LEN]]
   9 // CHECK-NEXT: br i1[[CMP1]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]]
  10 #pragma clang loop vectorize(assume_safety) interleave(disable) unroll(disable)
  11   for (int i = 0; i < Length; i++) {
  12     // CHECK: [[RHIV1:.+]] = load i32, ptr [[IV1]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_2]]
  13     // CHECK-DAG: [[CALC1:.+]] = mul nsw i32[[RHIV1]], 2
  14     // CHECK-DAG: [[SIV1:.+]] = load i32, ptr [[IV1]]{{.*}}!llvm.access.group ![[ACCESS_GROUP_2]]
  15     // CHECK-DAG: [[INDEX1:.+]] = sext i32[[SIV1]] to i64
  16     // CHECK-DAG: [[ARRAY1:.+]] = load ptr, ptr [[LIST1:.*]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_2]]
  17     // CHECK-DAG: [[PTR1:.+]] = getelementptr inbounds i32, ptr[[ARRAY1]], i64[[INDEX1]]
  18     // CHECK: store i32[[CALC1]], ptr[[PTR1]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_2]]
  19     // CHECK-NEXT: br label [[LOOP1_INC:[^,]+]]
  20     List[i] = i * 2;
  21
  22     // CHECK: br label [[LOOP1_COND:[^,]+]], !llvm.loop ![[LOOP1_HINTS:[0-9]+]]
  23   }
  24 }
  25
  26 // Verify assume_safety interleaving is recognized.
  27 void interleave_test(int *List, int Length) {
  28 // CHECK: define {{.*}} @_Z15interleave_test
  29 // CHECK: [[LOAD2_IV:.+]] = load i32, ptr [[IV2:[^,]+]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_8:[0-9]+]]
  30 // CHECK-NEXT: [[LOAD2_LEN:.+]] = load i32, ptr [[LEN2:.+]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_8]]
  31 // CHECK-NEXT: [[CMP2:.+]] = icmp slt i32[[LOAD2_IV]],[[LOAD2_LEN]]
  32 // CHECK-NEXT: br i1[[CMP2]], label %[[LOOP2_BODY:[^,]+]], label %[[LOOP2_END:[^,]+]]
  33 #pragma clang loop interleave(assume_safety) vectorize(disable) unroll(disable)
  34   for (int i = 0; i < Length; i++) {
  35     // CHECK: [[RHIV2:.+]] = load i32, ptr [[IV2]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_8]]
  36     // CHECK-DAG: [[CALC2:.+]] = mul nsw i32[[RHIV2]], 2
  37     // CHECK-DAG: [[SIV2:.+]] = load i32, ptr [[IV2]]{{.*}}!llvm.access.group ![[ACCESS_GROUP_8]]
  38     // CHECK-DAG: [[INDEX2:.+]] = sext i32[[SIV2]] to i64
  39     // CHECK-DAG: [[ARRAY2:.+]] = load ptr, ptr [[LIST2:.*]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_8]]
  40     // CHECK-DAG: [[PTR2:.+]] = getelementptr inbounds i32, ptr[[ARRAY2]], i64[[INDEX2]]
  41     // CHECK: store i32[[CALC2]], ptr[[PTR2]], {{.*}}!llvm.access.group ![[ACCESS_GROUP_8]]
  42     // CHECK-NEXT: br label [[LOOP2_INC:[^,]+]]
  43     List[i] = i * 2;
  44
  45     // CHECK: br label [[LOOP2_COND:[^,]+]], !llvm.loop ![[LOOP2_HINTS:[0-9]+]]
  46   }
  47 }
  48
  49 // CHECK: ![[ACCESS_GROUP_2]] = distinct !{}
  50 // CHECK: ![[LOOP1_HINTS]] = distinct !{![[LOOP1_HINTS]], [[MP:![0-9]+]], ![[PARALLEL_ACCESSES_7:[0-9]+]], ![[UNROLL_DISABLE:[0-9]+]], ![[INTERLEAVE_1:[0-9]+]], ![[INTENABLE_1:[0-9]+]]}
  51 // CHECK: ![[PARALLEL_ACCESSES_7]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_2]]}
  52 // CHECK: ![[UNROLL_DISABLE]] = !{!"llvm.loop.unroll.disable"}
  53 // CHECK: ![[INTERLEAVE_1]] = !{!"llvm.loop.interleave.count", i32 1}
  54 // CHECK: ![[INTENABLE_1]] = !{!"llvm.loop.vectorize.enable", i1 true}
  55 // CHECK: ![[ACCESS_GROUP_8]] = distinct !{}
  56 // CHECK: ![[LOOP2_HINTS]] = distinct !{![[LOOP2_HINTS]], [[MP]], ![[PARALLEL_ACCESSES_11:[0-9]+]], ![[UNROLL_DISABLE]], ![[WIDTH_1:[0-9]+]], ![[INTENABLE_1]]}
  57 // CHECK: ![[PARALLEL_ACCESSES_11]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_8]]}
  58 // CHECK: ![[WIDTH_1]] = !{!"llvm.loop.vectorize.width", i32 1}