clang/test/Driver/riscv-cpus.c

   1 // Check target CPUs are correctly passed.
   2
   3 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s
   4 // MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32"
   5 // MCPU-ROCKET32: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
   6
   7 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKET64 %s
   8 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
   9 // MCPU-ROCKET64: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
  10
  11 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
  12 // MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
  13 // MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
  14 // MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
  15 // MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
  16
  17 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
  18 // MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
  19 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
  20 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
  21 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
  22
  23 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
  24 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
  25 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
  26 // MCPU-NATIVE-NOT: "-target-cpu" "native"
  27
  28 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
  29 // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"
  30
  31 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s
  32 // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
  33
  34 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s
  35 // MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base"
  36
  37 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
  38 // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
  39
  40 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
  41 // MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
  42 // MCPU-VEYRON-V1: "-target-feature" "+m"
  43 // MCPU-VEYRON-V1: "-target-feature" "+a"
  44 // MCPU-VEYRON-V1: "-target-feature" "+f"
  45 // MCPU-VEYRON-V1: "-target-feature" "+d"
  46 // MCPU-VEYRON-V1: "-target-feature" "+c"
  47 // MCPU-VEYRON-V1: "-target-feature" "+zicbom"
  48 // MCPU-VEYRON-V1: "-target-feature" "+zicbop"
  49 // MCPU-VEYRON-V1: "-target-feature" "+zicboz"
  50 // MCPU-VEYRON-V1: "-target-feature" "+zicntr"
  51 // MCPU-VEYRON-V1: "-target-feature" "+zicsr"
  52 // MCPU-VEYRON-V1: "-target-feature" "+zifencei"
  53 // MCPU-VEYRON-V1: "-target-feature" "+zihintpause"
  54 // MCPU-VEYRON-V1: "-target-feature" "+zihpm"
  55 // MCPU-VEYRON-V1: "-target-feature" "+zba"
  56 // MCPU-VEYRON-V1: "-target-feature" "+zbb"
  57 // MCPU-VEYRON-V1: "-target-feature" "+zbc"
  58 // MCPU-VEYRON-V1: "-target-feature" "+zbs"
  59 // MCPU-VEYRON-V1: "-target-feature" "+xventanacondops"
  60 // MCPU-VEYRON-V1: "-target-abi" "lp64d"
  61
  62 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s
  63 // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
  64
  65 // Check mtune alias CPU has resolved to the right CPU according XLEN.
  66 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
  67 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
  68
  69 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-64 %s
  70 // MTUNE-GENERIC-64: "-tune-cpu" "generic"
  71
  72 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-32 %s
  73 // MTUNE-ROCKET-32: "-tune-cpu" "rocket"
  74
  75 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s
  76 // MTUNE-ROCKET-64: "-tune-cpu" "rocket"
  77
  78 // We cannot check much for -mtune=native, but it should be replaced by a valid CPU string.
  79 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=native | FileCheck -check-prefix=MTUNE-NATIVE %s
  80 // MTUNE-NATIVE-NOT: "-tune-cpu" "native"
  81
  82 // mcpu with default march
  83 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s
  84 // MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20"
  85 // MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c"
  86 // MCPU-SIFIVE-E20: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
  87 // MCPU-SIFIVE-E20: "-target-abi" "ilp32"
  88
  89 // mcpu with default march
  90 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck -check-prefix=MCPU-SIFIVE-E21 %s
  91 // MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21"
  92 // MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c"
  93 // MCPU-SIFIVE-E21: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
  94 // MCPU-SIFIVE-E21: "-target-abi" "ilp32"
  95
  96 // mcpu with default march
  97 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck -check-prefix=MCPU-SIFIVE-E24 %s
  98 // MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24"
  99 // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
 100 // MCPU-SIFIVE-E24: "-target-feature" "+c"
 101 // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 102 // MCPU-SIFIVE-E24: "-target-abi" "ilp32"
 103
 104 // mcpu with default march
 105 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s
 106 // MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34"
 107 // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
 108 // MCPU-SIFIVE-E34: "-target-feature" "+c"
 109 // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 110 // MCPU-SIFIVE-E34: "-target-abi" "ilp32"
 111
 112 // mcpu with mabi option
 113 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
 114 // MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21"
 115 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
 116 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+c"
 117 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 118 // MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"
 119
 120 // mcpu with mabi option
 121 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
 122 // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
 123 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
 124 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+c"
 125 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 126 // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
 127
 128 // mcpu with default march
 129 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s
 130 // MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54"
 131 // MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 132 // MCPU-SIFIVE-S54: "-target-feature" "+c"
 133 // MCPU-SIFIVE-S54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 134 // MCPU-SIFIVE-S54: "-target-abi" "lp64d"
 135
 136 // mcpu with mabi option
 137 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s
 138 // MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76"
 139 // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 140 // MCPU-SIFIVE-S76: "-target-feature" "+c"
 141 // MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause"
 142 // MCPU-SIFIVE-S76: "-target-feature" "+xsfcie"
 143 // MCPU-SIFIVE-S76: "-target-abi" "lp64d"
 144
 145 // mcpu with default march
 146 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
 147 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
 148 // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 149 // MCPU-SIFIVE-U54: "-target-feature" "+c"
 150 // MCPU-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 151 // MCPU-SIFIVE-U54: "-target-abi" "lp64d"
 152
 153 // mcpu with mabi option
 154 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s
 155 // MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
 156 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 157 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c"
 158 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 159 // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
 160
 161 // mcpu with default march
 162 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s
 163 // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
 164 // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
 165 // MCPU-SIFIVE-E76: "-target-feature" "+c"
 166 // MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 167 // MCPU-SIFIVE-E76: "-target-abi" "ilp32"
 168
 169 // mcpu with mabi option
 170 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
 171 // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
 172 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 173 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+c"
 174 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 175 // MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
 176
 177 // march overwrite mcpu's default march
 178 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s
 179 // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
 180 // MCPU-MARCH: "-target-abi" "ilp32"
 181
 182 // Check interaction between mcpu and mtune, mtune won't affect arch related
 183 // target feature, but mcpu will.
 184 //
 185 // In this case, sifive-e31 is rv32imac, sifive-e76 is rv32imafc, so F-extension
 186 // should not enabled.
 187 //
 188 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s
 189 // MTUNE-E31-MCPU-E76: "-target-cpu" "sifive-e31"
 190 // MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f"
 191 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m"
 192 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a"
 193 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c"
 194 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 195 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 196
 197 // mcpu with default march include experimental extensions
 198 // RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s
 199 // MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
 200 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 201 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
 202 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 203 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
 204 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
 205 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvfh"
 206 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
 207 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
 208 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
 209 // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
 210
 211 // Check failed cases
 212
 213 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
 214 // FAIL-MCPU-NAME: error: unsupported argument 'generic-rv321' to option '-mcpu='
 215
 216 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 217 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64