clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  10 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5
  11 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6
  12 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  13 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6
  14
  15 // RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8
  16 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  17 // RUN: %clang_cc1  -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8
  18 // RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10
  19 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  20 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10
  21
  22 // RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12
  23 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  24 // RUN: %clang_cc1  -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12
  25 // RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14
  26 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  27 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14
  28 // expected-no-diagnostics
  29 #ifndef HEADER
  30 #define HEADER
  31
  32 template <class T>
  33 struct S {
  34   T f;
  35   S(T a) : f(a) {}
  36   S() : f() {}
  37   operator T() { return T(); }
  38   ~S() {}
  39 };
  40
  41 template <typename T>
  42 T tmain() {
  43   S<T> test;
  44   T t_var = T();
  45   T vec[] = {1, 2};
  46   S<T> s_arr[] = {1, 2};
  47   S<T> &var = test;
  48   #pragma omp target
  49   #pragma omp teams
  50   #pragma omp distribute parallel for simd firstprivate(t_var, vec, s_arr, s_arr, var, var)
  51   for (int i = 0; i < 2; ++i) {
  52     vec[i] = t_var;
  53     s_arr[i] = var;
  54   }
  55   return T();
  56 }
  57
  58 int main() {
  59   static int svar;
  60   volatile double g;
  61   volatile double &g1 = g;
  62
  63   #ifdef LAMBDA
  64   [&]() {
  65     static float sfvar;
  66
  67     #pragma omp target
  68     #pragma omp teams
  69     #pragma omp distribute parallel for simd firstprivate(g, g1, svar, sfvar)
  70     for (int i = 0; i < 2; ++i) {
  71
  72       // addr alloca's
  73
  74       // private alloca's
  75
  76       // transfer input parameters into addr alloca's
  77
  78       // init private alloca's with addr alloca's
  79       // g
  80
  81       // g1
  82
  83       // svar
  84
  85       // sfvar
  86
  87       // pass firstprivate parameters to parallel outlined function
  88       // g
  89
  90       // g1
  91
  92       // svar
  93
  94       // sfvar
  95
  96
  97
  98       // skip initial params
  99
 100       // addr alloca's
 101
 102       // private alloca's (only for 32-bit)
 103
 104       // transfer input parameters into addr alloca's
 105
 106       // prepare parameters for lambda
 107       // g
 108
 109       // g1
 110
 111       // svar
 112
 113       // sfvar
 114
 115       g = 1;
 116       g1 = 1;
 117       svar = 3;
 118       sfvar = 4.0;
 119
 120       // pass params to inner lambda
 121       [&]() {
 122         g = 2;
 123         g1 = 2;
 124         svar = 4;
 125         sfvar = 8.0;
 126
 127       }();
 128     }
 129   }();
 130   return 0;
 131   #else
 132   S<float> test;
 133   int t_var = 0;
 134   int vec[] = {1, 2};
 135   S<float> s_arr[] = {1, 2};
 136   S<float> &var = test;
 137
 138   #pragma omp target
 139   #pragma omp teams
 140   #pragma omp distribute parallel for simd firstprivate(t_var, vec, s_arr, s_arr, var, var, svar)
 141   for (int i = 0; i < 2; ++i) {
 142     vec[i] = t_var;
 143     s_arr[i] = var;
 144   }
 145   return tmain<int>();
 146   #endif
 147 }
 148
 149
 150
 151
 152 // addr alloca's
 153
 154 // skip loop alloca's
 155
 156 // private alloca's
 157
 158
 159 // init addr alloca's with input values
 160
 161 // init private alloca's with addr alloca's
 162 // t-var
 163
 164 // vec
 165
 166 // s_arr
 167
 168 // var
 169
 170 // svar
 171
 172 // pass private alloca's to fork
 173 // not dag to distinguish with S_VAR_CAST
 174
 175 // call destructors: var..
 176
 177 // ..and s_arr
 178
 179
 180 // By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for.
 181 // However, the support for 'firstprivate' of 'parallel' is only used when 'parallel'
 182 // is found alone. Therefore we only have one 'firstprivate' support for 'parallel for'
 183 // in combination
 184
 185 // addr alloca's
 186
 187 // skip loop alloca's
 188
 189 // private alloca's
 190
 191
 192 // init addr alloca's with input values
 193
 194 // init private alloca's with addr alloca's
 195 // vec
 196
 197 // s_arr
 198
 199 // var
 200
 201
 202 // call destructors: var..
 203
 204 // ..and s_arr
 205
 206
 207 // template tmain with S_INT_TY
 208
 209
 210
 211 // addr alloca's
 212
 213 // skip loop alloca's
 214
 215 // private alloca's
 216
 217
 218 // init addr alloca's with input values
 219
 220 // init private alloca's with addr alloca's
 221 // t-var
 222
 223 // vec
 224
 225 // s_arr
 226
 227 // var
 228
 229 // pass private alloca's to fork
 230 // not dag to distinguish with S_VAR_CAST
 231
 232 // call destructors: var..
 233
 234 // ..and s_arr
 235
 236
 237 // By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for.
 238 // However, the support for 'firstprivate' of 'parallel' is only used when 'parallel'
 239 // is found alone. Therefore we only have one 'firstprivate' support for 'parallel for'
 240 // in combination
 241
 242 // addr alloca's
 243
 244 // skip loop alloca's
 245
 246 // private alloca's
 247
 248
 249 // init addr alloca's with input values
 250
 251 // init private alloca's with addr alloca's
 252 // vec
 253
 254 // s_arr
 255
 256 // var
 257
 258
 259 // call destructors: var..
 260
 261 // ..and s_arr
 262
 263
 264 #endif
 265 // CHECK1-LABEL: define {{[^@]+}}@main
 266 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 267 // CHECK1-NEXT:  entry:
 268 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 269 // CHECK1-NEXT:    [[G:%.*]] = alloca double, align 8
 270 // CHECK1-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 271 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
 272 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 273 // CHECK1-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 274 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 275 // CHECK1-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8
 276 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 277 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8
 278 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8
 279 // CHECK1-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
 280 // CHECK1-NEXT:    ret i32 0
 281 //
 282 //
 283 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
 284 // CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {
 285 // CHECK1-NEXT:  entry:
 286 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
 287 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
 288 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 289 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8
 290 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 291 // CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
 292 // CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
 293 // CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 294 // CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 295 // CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
 296 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
 297 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])
 298 // CHECK1-NEXT:    ret void
 299 //
 300 //
 301 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined
 302 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {
 303 // CHECK1-NEXT:  entry:
 304 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 305 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 306 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 8
 307 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 8
 308 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 8
 309 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca ptr, align 8
 310 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 311 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 312 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 313 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 314 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 315 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 316 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 317 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 318 // CHECK1-NEXT:    [[G3:%.*]] = alloca double, align 8
 319 // CHECK1-NEXT:    [[G14:%.*]] = alloca double, align 8
 320 // CHECK1-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 8
 321 // CHECK1-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4
 322 // CHECK1-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4
 323 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 324 // CHECK1-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
 325 // CHECK1-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
 326 // CHECK1-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 327 // CHECK1-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i64, align 8
 328 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 329 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 330 // CHECK1-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 8
 331 // CHECK1-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 8
 332 // CHECK1-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8
 333 // CHECK1-NEXT:    store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 334 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
 335 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8
 336 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8
 337 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8
 338 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 8
 339 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
 340 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 8
 341 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 342 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 343 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 344 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 345 // CHECK1-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8
 346 // CHECK1-NEXT:    store double [[TMP5]], ptr [[G3]], align 8
 347 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8
 348 // CHECK1-NEXT:    [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
 349 // CHECK1-NEXT:    store double [[TMP7]], ptr [[G14]], align 8
 350 // CHECK1-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 8
 351 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4
 352 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[SVAR6]], align 4
 353 // CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4
 354 // CHECK1-NEXT:    store float [[TMP9]], ptr [[SFVAR7]], align 4
 355 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 356 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 357 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 358 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 359 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
 360 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 361 // CHECK1:       cond.true:
 362 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 363 // CHECK1:       cond.false:
 364 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 365 // CHECK1-NEXT:    br label [[COND_END]]
 366 // CHECK1:       cond.end:
 367 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
 368 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 369 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 370 // CHECK1-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
 371 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 372 // CHECK1:       omp.inner.for.cond:
 373 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
 374 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
 375 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
 376 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 377 // CHECK1:       omp.inner.for.body:
 378 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]]
 379 // CHECK1-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
 380 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
 381 // CHECK1-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
 382 // CHECK1-NEXT:    [[TMP21:%.*]] = load double, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP4]]
 383 // CHECK1-NEXT:    store double [[TMP21]], ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
 384 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
 385 // CHECK1-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP4]]
 386 // CHECK1-NEXT:    [[TMP24:%.*]] = load volatile double, ptr [[TMP23]], align 8, !llvm.access.group [[ACC_GRP4]]
 387 // CHECK1-NEXT:    store double [[TMP24]], ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
 388 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
 389 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP4]]
 390 // CHECK1-NEXT:    store i32 [[TMP26]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]]
 391 // CHECK1-NEXT:    [[TMP27:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
 392 // CHECK1-NEXT:    [[TMP28:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP4]]
 393 // CHECK1-NEXT:    store float [[TMP28]], ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]]
 394 // CHECK1-NEXT:    [[TMP29:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
 395 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]), !llvm.access.group [[ACC_GRP4]]
 396 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 397 // CHECK1:       omp.inner.for.inc:
 398 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 399 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]]
 400 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
 401 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 402 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
 403 // CHECK1:       omp.inner.for.end:
 404 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 405 // CHECK1:       omp.loop.exit:
 406 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])
 407 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 408 // CHECK1-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
 409 // CHECK1-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 410 // CHECK1:       .omp.final.then:
 411 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 412 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 413 // CHECK1:       .omp.final.done:
 414 // CHECK1-NEXT:    ret void
 415 //
 416 //
 417 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined
 418 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] {
 419 // CHECK1-NEXT:  entry:
 420 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 421 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 422 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 423 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 424 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
 425 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
 426 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 427 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8
 428 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 429 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 430 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 431 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 432 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 433 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 434 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 435 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 436 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
 437 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 438 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 439 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 440 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 441 // CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
 442 // CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
 443 // CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 444 // CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 445 // CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
 446 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 447 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 448 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 449 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 450 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 451 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
 452 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 453 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
 454 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 455 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 456 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 457 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 458 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 459 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 460 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
 461 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 462 // CHECK1:       cond.true:
 463 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 464 // CHECK1:       cond.false:
 465 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 466 // CHECK1-NEXT:    br label [[COND_END]]
 467 // CHECK1:       cond.end:
 468 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 469 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 470 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 471 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 472 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 473 // CHECK1:       omp.inner.for.cond:
 474 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
 475 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
 476 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 477 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 478 // CHECK1:       omp.inner.for.body:
 479 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
 480 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
 481 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 482 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
 483 // CHECK1-NEXT:    store double 1.000000e+00, ptr [[G_ADDR]], align 8, !llvm.access.group [[ACC_GRP8]]
 484 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP8]]
 485 // CHECK1-NEXT:    store volatile double 1.000000e+00, ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP8]]
 486 // CHECK1-NEXT:    store i32 3, ptr [[SVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP8]]
 487 // CHECK1-NEXT:    store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP8]]
 488 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 489 // CHECK1-NEXT:    store ptr [[G_ADDR]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]]
 490 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
 491 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP8]]
 492 // CHECK1-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]]
 493 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
 494 // CHECK1-NEXT:    store ptr [[SVAR_ADDR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP8]]
 495 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
 496 // CHECK1-NEXT:    store ptr [[SFVAR_ADDR]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP8]]
 497 // CHECK1-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]]
 498 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 499 // CHECK1:       omp.body.continue:
 500 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 501 // CHECK1:       omp.inner.for.inc:
 502 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
 503 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1
 504 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
 505 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
 506 // CHECK1:       omp.inner.for.end:
 507 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 508 // CHECK1:       omp.loop.exit:
 509 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
 510 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 511 // CHECK1-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
 512 // CHECK1-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 513 // CHECK1:       .omp.final.then:
 514 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 515 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 516 // CHECK1:       .omp.final.done:
 517 // CHECK1-NEXT:    ret void
 518 //
 519 //
 520 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 521 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
 522 // CHECK1-NEXT:  entry:
 523 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
 524 // CHECK1-NEXT:    ret void
 525 //
 526 //
 527 // CHECK3-LABEL: define {{[^@]+}}@main
 528 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 529 // CHECK3-NEXT:  entry:
 530 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 531 // CHECK3-NEXT:    [[G:%.*]] = alloca double, align 8
 532 // CHECK3-NEXT:    [[G1:%.*]] = alloca ptr, align 4
 533 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
 534 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 535 // CHECK3-NEXT:    store ptr [[G]], ptr [[G1]], align 4
 536 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 537 // CHECK3-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4
 538 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 539 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4
 540 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4
 541 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
 542 // CHECK3-NEXT:    ret i32 0
 543 //
 544 //
 545 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
 546 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {
 547 // CHECK3-NEXT:  entry:
 548 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 549 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 550 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
 551 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4
 552 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 553 // CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8
 554 // CHECK3-NEXT:    [[G13:%.*]] = alloca double, align 8
 555 // CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
 556 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 557 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 558 // CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
 559 // CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 560 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 561 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 562 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 4
 563 // CHECK3-NEXT:    [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8
 564 // CHECK3-NEXT:    store double [[TMP2]], ptr [[G2]], align 8
 565 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
 566 // CHECK3-NEXT:    [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4
 567 // CHECK3-NEXT:    store double [[TMP4]], ptr [[G13]], align 8
 568 // CHECK3-NEXT:    store ptr [[G13]], ptr [[_TMP4]], align 4
 569 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4
 570 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])
 571 // CHECK3-NEXT:    ret void
 572 //
 573 //
 574 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined
 575 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {
 576 // CHECK3-NEXT:  entry:
 577 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 578 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 579 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 580 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 581 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 4
 582 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca ptr, align 4
 583 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 584 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
 585 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 586 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 587 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 588 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 589 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 590 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 591 // CHECK3-NEXT:    [[G3:%.*]] = alloca double, align 8
 592 // CHECK3-NEXT:    [[G14:%.*]] = alloca double, align 8
 593 // CHECK3-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 4
 594 // CHECK3-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4
 595 // CHECK3-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4
 596 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 597 // CHECK3-NEXT:    [[G1_CASTED:%.*]] = alloca i32, align 4
 598 // CHECK3-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
 599 // CHECK3-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i32, align 4
 600 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 601 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 602 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 603 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 604 // CHECK3-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4
 605 // CHECK3-NEXT:    store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 606 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 607 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 608 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4
 609 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4
 610 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 4
 611 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
 612 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 4
 613 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 614 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 615 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 616 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 617 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8
 618 // CHECK3-NEXT:    store double [[TMP5]], ptr [[G3]], align 8
 619 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4
 620 // CHECK3-NEXT:    [[TMP7:%.*]] = load double, ptr [[TMP6]], align 4
 621 // CHECK3-NEXT:    store double [[TMP7]], ptr [[G14]], align 8
 622 // CHECK3-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 4
 623 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4
 624 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[SVAR6]], align 4
 625 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4
 626 // CHECK3-NEXT:    store float [[TMP9]], ptr [[SFVAR7]], align 4
 627 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 628 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 629 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 630 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 631 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
 632 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 633 // CHECK3:       cond.true:
 634 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 635 // CHECK3:       cond.false:
 636 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 637 // CHECK3-NEXT:    br label [[COND_END]]
 638 // CHECK3:       cond.end:
 639 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
 640 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 641 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 642 // CHECK3-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
 643 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 644 // CHECK3:       omp.inner.for.cond:
 645 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 646 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 647 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
 648 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 649 // CHECK3:       omp.inner.for.body:
 650 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]]
 651 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 652 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4, !llvm.access.group [[ACC_GRP5]]
 653 // CHECK3-NEXT:    [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP5]]
 654 // CHECK3-NEXT:    store double [[TMP20]], ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 655 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 656 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP5]]
 657 // CHECK3-NEXT:    store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 658 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 659 // CHECK3-NEXT:    [[TMP24:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP5]]
 660 // CHECK3-NEXT:    store float [[TMP24]], ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 661 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 662 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]), !llvm.access.group [[ACC_GRP5]]
 663 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 664 // CHECK3:       omp.inner.for.inc:
 665 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 666 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]]
 667 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]
 668 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 669 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 670 // CHECK3:       omp.inner.for.end:
 671 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 672 // CHECK3:       omp.loop.exit:
 673 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])
 674 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 675 // CHECK3-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
 676 // CHECK3-NEXT:    br i1 [[TMP29]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 677 // CHECK3:       .omp.final.then:
 678 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 679 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 680 // CHECK3:       .omp.final.done:
 681 // CHECK3-NEXT:    ret void
 682 //
 683 //
 684 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined
 685 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] {
 686 // CHECK3-NEXT:  entry:
 687 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 688 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 689 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
 690 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
 691 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 692 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca i32, align 4
 693 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
 694 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4
 695 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 696 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 697 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 698 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 699 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 700 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 701 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 702 // CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8
 703 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 704 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
 705 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 706 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 707 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
 708 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
 709 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 710 // CHECK3-NEXT:    store i32 [[G1]], ptr [[G1_ADDR]], align 4
 711 // CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
 712 // CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 713 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 714 // CHECK3-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 4
 715 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 716 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 717 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
 718 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
 719 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
 720 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
 721 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 722 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 723 // CHECK3-NEXT:    [[TMP3:%.*]] = load double, ptr [[TMP0]], align 8
 724 // CHECK3-NEXT:    store double [[TMP3]], ptr [[G2]], align 8
 725 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 726 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 727 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 728 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 729 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
 730 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 731 // CHECK3:       cond.true:
 732 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 733 // CHECK3:       cond.false:
 734 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 735 // CHECK3-NEXT:    br label [[COND_END]]
 736 // CHECK3:       cond.end:
 737 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 738 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 739 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 740 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 741 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 742 // CHECK3:       omp.inner.for.cond:
 743 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
 744 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
 745 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 746 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 747 // CHECK3:       omp.inner.for.body:
 748 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 749 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
 750 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 751 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 752 // CHECK3-NEXT:    store double 1.000000e+00, ptr [[G2]], align 8, !llvm.access.group [[ACC_GRP9]]
 753 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 4, !llvm.access.group [[ACC_GRP9]]
 754 // CHECK3-NEXT:    store volatile double 1.000000e+00, ptr [[TMP12]], align 4, !llvm.access.group [[ACC_GRP9]]
 755 // CHECK3-NEXT:    store i32 3, ptr [[SVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]
 756 // CHECK3-NEXT:    store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]
 757 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 758 // CHECK3-NEXT:    store ptr [[G2]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP9]]
 759 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
 760 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP]], align 4, !llvm.access.group [[ACC_GRP9]]
 761 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP14]], align 4, !llvm.access.group [[ACC_GRP9]]
 762 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
 763 // CHECK3-NEXT:    store ptr [[SVAR_ADDR]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP9]]
 764 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
 765 // CHECK3-NEXT:    store ptr [[SFVAR_ADDR]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP9]]
 766 // CHECK3-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group [[ACC_GRP9]]
 767 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 768 // CHECK3:       omp.body.continue:
 769 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 770 // CHECK3:       omp.inner.for.inc:
 771 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 772 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP18]], 1
 773 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 774 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
 775 // CHECK3:       omp.inner.for.end:
 776 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 777 // CHECK3:       omp.loop.exit:
 778 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
 779 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 780 // CHECK3-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
 781 // CHECK3-NEXT:    br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 782 // CHECK3:       .omp.final.then:
 783 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 784 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 785 // CHECK3:       .omp.final.done:
 786 // CHECK3-NEXT:    ret void
 787 //
 788 //
 789 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 790 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
 791 // CHECK3-NEXT:  entry:
 792 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
 793 // CHECK3-NEXT:    ret void
 794 //
 795 //
 796 // CHECK5-LABEL: define {{[^@]+}}@main
 797 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
 798 // CHECK5-NEXT:  entry:
 799 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 800 // CHECK5-NEXT:    [[G:%.*]] = alloca double, align 8
 801 // CHECK5-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 802 // CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
 803 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 804 // CHECK5-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 805 // CHECK5-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 806 // CHECK5-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8
 807 // CHECK5-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 808 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8
 809 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8
 810 // CHECK5-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
 811 // CHECK5-NEXT:    ret i32 0
 812 //
 813 //
 814 // CHECK6-LABEL: define {{[^@]+}}@main
 815 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
 816 // CHECK6-NEXT:  entry:
 817 // CHECK6-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 818 // CHECK6-NEXT:    [[G:%.*]] = alloca double, align 8
 819 // CHECK6-NEXT:    [[G1:%.*]] = alloca ptr, align 4
 820 // CHECK6-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
 821 // CHECK6-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 822 // CHECK6-NEXT:    store ptr [[G]], ptr [[G1]], align 4
 823 // CHECK6-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 824 // CHECK6-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4
 825 // CHECK6-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 826 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4
 827 // CHECK6-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4
 828 // CHECK6-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
 829 // CHECK6-NEXT:    ret i32 0
 830 //
 831 //
 832 // CHECK8-LABEL: define {{[^@]+}}@main
 833 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
 834 // CHECK8-NEXT:  entry:
 835 // CHECK8-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 836 // CHECK8-NEXT:    [[G:%.*]] = alloca double, align 8
 837 // CHECK8-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 838 // CHECK8-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 839 // CHECK8-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 840 // CHECK8-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 841 // CHECK8-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 842 // CHECK8-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 843 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 844 // CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 845 // CHECK8-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 846 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
 847 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
 848 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
 849 // CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 850 // CHECK8-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 851 // CHECK8-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 852 // CHECK8-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 853 // CHECK8-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 854 // CHECK8-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 855 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
 856 // CHECK8-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
 857 // CHECK8-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
 858 // CHECK8-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1
 859 // CHECK8-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
 860 // CHECK8-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 861 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
 862 // CHECK8-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
 863 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
 864 // CHECK8-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
 865 // CHECK8-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 866 // CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 867 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
 868 // CHECK8-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
 869 // CHECK8-NEXT:    [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 870 // CHECK8-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
 871 // CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
 872 // CHECK8-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 873 // CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP8]], align 8
 874 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 875 // CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP9]], align 8
 876 // CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 877 // CHECK8-NEXT:    store ptr null, ptr [[TMP10]], align 8
 878 // CHECK8-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 879 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP11]], align 8
 880 // CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 881 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP12]], align 8
 882 // CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 883 // CHECK8-NEXT:    store ptr null, ptr [[TMP13]], align 8
 884 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 885 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP14]], align 8
 886 // CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 887 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP15]], align 8
 888 // CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 889 // CHECK8-NEXT:    store ptr null, ptr [[TMP16]], align 8
 890 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 891 // CHECK8-NEXT:    store ptr [[TMP6]], ptr [[TMP17]], align 8
 892 // CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 893 // CHECK8-NEXT:    store ptr [[TMP7]], ptr [[TMP18]], align 8
 894 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 895 // CHECK8-NEXT:    store ptr null, ptr [[TMP19]], align 8
 896 // CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 897 // CHECK8-NEXT:    store i64 [[TMP5]], ptr [[TMP20]], align 8
 898 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 899 // CHECK8-NEXT:    store i64 [[TMP5]], ptr [[TMP21]], align 8
 900 // CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 901 // CHECK8-NEXT:    store ptr null, ptr [[TMP22]], align 8
 902 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 903 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 904 // CHECK8-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 905 // CHECK8-NEXT:    store i32 2, ptr [[TMP25]], align 4
 906 // CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 907 // CHECK8-NEXT:    store i32 5, ptr [[TMP26]], align 4
 908 // CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 909 // CHECK8-NEXT:    store ptr [[TMP23]], ptr [[TMP27]], align 8
 910 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 911 // CHECK8-NEXT:    store ptr [[TMP24]], ptr [[TMP28]], align 8
 912 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 913 // CHECK8-NEXT:    store ptr @.offload_sizes, ptr [[TMP29]], align 8
 914 // CHECK8-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 915 // CHECK8-NEXT:    store ptr @.offload_maptypes, ptr [[TMP30]], align 8
 916 // CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 917 // CHECK8-NEXT:    store ptr null, ptr [[TMP31]], align 8
 918 // CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 919 // CHECK8-NEXT:    store ptr null, ptr [[TMP32]], align 8
 920 // CHECK8-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 921 // CHECK8-NEXT:    store i64 2, ptr [[TMP33]], align 8
 922 // CHECK8-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 923 // CHECK8-NEXT:    store i64 0, ptr [[TMP34]], align 8
 924 // CHECK8-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 925 // CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
 926 // CHECK8-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 927 // CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
 928 // CHECK8-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 929 // CHECK8-NEXT:    store i32 0, ptr [[TMP37]], align 4
 930 // CHECK8-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.region_id, ptr [[KERNEL_ARGS]])
 931 // CHECK8-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
 932 // CHECK8-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 933 // CHECK8:       omp_offload.failed:
 934 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]
 935 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 936 // CHECK8:       omp_offload.cont:
 937 // CHECK8-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 938 // CHECK8-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 939 // CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 940 // CHECK8-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 941 // CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 942 // CHECK8:       arraydestroy.body:
 943 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 944 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 945 // CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 946 // CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 947 // CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 948 // CHECK8:       arraydestroy.done2:
 949 // CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 950 // CHECK8-NEXT:    [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
 951 // CHECK8-NEXT:    ret i32 [[TMP41]]
 952 //
 953 //
 954 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 955 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 956 // CHECK8-NEXT:  entry:
 957 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 958 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 959 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 960 // CHECK8-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 961 // CHECK8-NEXT:    ret void
 962 //
 963 //
 964 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 965 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 966 // CHECK8-NEXT:  entry:
 967 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 968 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 969 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 970 // CHECK8-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 971 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 972 // CHECK8-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 973 // CHECK8-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 974 // CHECK8-NEXT:    ret void
 975 //
 976 //
 977 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138
 978 // CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
 979 // CHECK8-NEXT:  entry:
 980 // CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 981 // CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 982 // CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 983 // CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 984 // CHECK8-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 985 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 986 // CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 987 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 988 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 989 // CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 990 // CHECK8-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 991 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 992 // CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 993 // CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 994 // CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
 995 // CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 996 // CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])
 997 // CHECK8-NEXT:    ret void
 998 //
 999 //
1000 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined
1001 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {
1002 // CHECK8-NEXT:  entry:
1003 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1004 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1005 // CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1006 // CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1007 // CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1008 // CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1009 // CHECK8-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 8
1010 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1011 // CHECK8-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1012 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1013 // CHECK8-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
1014 // CHECK8-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1015 // CHECK8-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1016 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1017 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1018 // CHECK8-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1019 // CHECK8-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1020 // CHECK8-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1021 // CHECK8-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1022 // CHECK8-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 8
1023 // CHECK8-NEXT:    [[SVAR9:%.*]] = alloca i32, align 4
1024 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
1025 // CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1026 // CHECK8-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
1027 // CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1028 // CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1029 // CHECK8-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1030 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1031 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1032 // CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1033 // CHECK8-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8
1034 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1035 // CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1036 // CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1037 // CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1038 // CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8
1039 // CHECK8-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 8
1040 // CHECK8-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1041 // CHECK8-NEXT:    store ptr [[TMP5]], ptr [[_TMP1]], align 8
1042 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1043 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1044 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1045 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1046 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
1047 // CHECK8-NEXT:    store i32 [[TMP6]], ptr [[T_VAR3]], align 4
1048 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)
1049 // CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1050 // CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1051 // CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]
1052 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1053 // CHECK8:       omp.arraycpy.body:
1054 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1055 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1056 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1057 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1058 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1059 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
1060 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1061 // CHECK8:       omp.arraycpy.done6:
1062 // CHECK8-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
1063 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false)
1064 // CHECK8-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 8
1065 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4
1066 // CHECK8-NEXT:    store i32 [[TMP9]], ptr [[SVAR9]], align 4
1067 // CHECK8-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1068 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
1069 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1070 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1071 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
1072 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1073 // CHECK8:       cond.true:
1074 // CHECK8-NEXT:    br label [[COND_END:%.*]]
1075 // CHECK8:       cond.false:
1076 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1077 // CHECK8-NEXT:    br label [[COND_END]]
1078 // CHECK8:       cond.end:
1079 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1080 // CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1081 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1082 // CHECK8-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
1083 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1084 // CHECK8:       omp.inner.for.cond:
1085 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
1086 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
1087 // CHECK8-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1088 // CHECK8-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1089 // CHECK8:       omp.inner.for.cond.cleanup:
1090 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1091 // CHECK8:       omp.inner.for.body:
1092 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]]
1093 // CHECK8-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
1094 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
1095 // CHECK8-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
1096 // CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP5]]
1097 // CHECK8-NEXT:    store i32 [[TMP21]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
1098 // CHECK8-NEXT:    [[TMP22:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]]
1099 // CHECK8-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP5]]
1100 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, ptr [[SVAR9]], align 4, !llvm.access.group [[ACC_GRP5]]
1101 // CHECK8-NEXT:    store i32 [[TMP24]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
1102 // CHECK8-NEXT:    [[TMP25:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]]
1103 // CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], ptr [[VEC4]], i64 [[TMP22]], ptr [[S_ARR5]], ptr [[TMP23]], i64 [[TMP25]]), !llvm.access.group [[ACC_GRP5]]
1104 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1105 // CHECK8:       omp.inner.for.inc:
1106 // CHECK8-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
1107 // CHECK8-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]]
1108 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]
1109 // CHECK8-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
1110 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1111 // CHECK8:       omp.inner.for.end:
1112 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1113 // CHECK8:       omp.loop.exit:
1114 // CHECK8-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1115 // CHECK8-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
1116 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP29]])
1117 // CHECK8-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1118 // CHECK8-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
1119 // CHECK8-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1120 // CHECK8:       .omp.final.then:
1121 // CHECK8-NEXT:    store i32 2, ptr [[I]], align 4
1122 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1123 // CHECK8:       .omp.final.done:
1124 // CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
1125 // CHECK8-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1126 // CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2
1127 // CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1128 // CHECK8:       arraydestroy.body:
1129 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1130 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1131 // CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1132 // CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
1133 // CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
1134 // CHECK8:       arraydestroy.done12:
1135 // CHECK8-NEXT:    ret void
1136 //
1137 //
1138 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined
1139 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1140 // CHECK8-NEXT:  entry:
1141 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1142 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1143 // CHECK8-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1144 // CHECK8-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1145 // CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1146 // CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1147 // CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1148 // CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1149 // CHECK8-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
1150 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1151 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1152 // CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1153 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1154 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1155 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1156 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1157 // CHECK8-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1158 // CHECK8-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
1159 // CHECK8-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1160 // CHECK8-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8
1161 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
1162 // CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1163 // CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1164 // CHECK8-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1165 // CHECK8-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1166 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1167 // CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1168 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1169 // CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1170 // CHECK8-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
1171 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1172 // CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1173 // CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1174 // CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1175 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1176 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1177 // CHECK8-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1178 // CHECK8-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1179 // CHECK8-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1180 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1181 // CHECK8-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1182 // CHECK8-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1183 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1184 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1185 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)
1186 // CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
1187 // CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1188 // CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
1189 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1190 // CHECK8:       omp.arraycpy.body:
1191 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1192 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1193 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1194 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1195 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1196 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
1197 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
1198 // CHECK8:       omp.arraycpy.done5:
1199 // CHECK8-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
1200 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false)
1201 // CHECK8-NEXT:    store ptr [[VAR6]], ptr [[_TMP7]], align 8
1202 // CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1203 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1204 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1205 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1206 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1207 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1208 // CHECK8:       cond.true:
1209 // CHECK8-NEXT:    br label [[COND_END:%.*]]
1210 // CHECK8:       cond.false:
1211 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1212 // CHECK8-NEXT:    br label [[COND_END]]
1213 // CHECK8:       cond.end:
1214 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1215 // CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1216 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1217 // CHECK8-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1218 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1219 // CHECK8:       omp.inner.for.cond:
1220 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
1221 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
1222 // CHECK8-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1223 // CHECK8-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1224 // CHECK8:       omp.inner.for.cond.cleanup:
1225 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1226 // CHECK8:       omp.inner.for.body:
1227 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
1228 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
1229 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1230 // CHECK8-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1231 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]
1232 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1233 // CHECK8-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
1234 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1235 // CHECK8-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
1236 // CHECK8-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP9]]
1237 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1238 // CHECK8-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
1239 // CHECK8-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]]
1240 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]]
1241 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1242 // CHECK8:       omp.body.continue:
1243 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1244 // CHECK8:       omp.inner.for.inc:
1245 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
1246 // CHECK8-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1
1247 // CHECK8-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
1248 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1249 // CHECK8:       omp.inner.for.end:
1250 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1251 // CHECK8:       omp.loop.exit:
1252 // CHECK8-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1253 // CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1254 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1255 // CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1256 // CHECK8-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1257 // CHECK8-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1258 // CHECK8:       .omp.final.then:
1259 // CHECK8-NEXT:    store i32 2, ptr [[I]], align 4
1260 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1261 // CHECK8:       .omp.final.done:
1262 // CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1263 // CHECK8-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
1264 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2
1265 // CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1266 // CHECK8:       arraydestroy.body:
1267 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1268 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1269 // CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1270 // CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
1271 // CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
1272 // CHECK8:       arraydestroy.done13:
1273 // CHECK8-NEXT:    ret void
1274 //
1275 //
1276 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1277 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1278 // CHECK8-NEXT:  entry:
1279 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1280 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1281 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1282 // CHECK8-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1283 // CHECK8-NEXT:    ret void
1284 //
1285 //
1286 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1287 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
1288 // CHECK8-NEXT:  entry:
1289 // CHECK8-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1290 // CHECK8-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1291 // CHECK8-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1292 // CHECK8-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1293 // CHECK8-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1294 // CHECK8-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
1295 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1296 // CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1297 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
1298 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
1299 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
1300 // CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1301 // CHECK8-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1302 // CHECK8-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1303 // CHECK8-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1304 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1305 // CHECK8-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
1306 // CHECK8-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1307 // CHECK8-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
1308 // CHECK8-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1309 // CHECK8-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
1310 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
1311 // CHECK8-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
1312 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1313 // CHECK8-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1314 // CHECK8-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1315 // CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1316 // CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
1317 // CHECK8-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1318 // CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1319 // CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP6]], align 8
1320 // CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1321 // CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8
1322 // CHECK8-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1323 // CHECK8-NEXT:    store ptr null, ptr [[TMP8]], align 8
1324 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1325 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 8
1326 // CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1327 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 8
1328 // CHECK8-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1329 // CHECK8-NEXT:    store ptr null, ptr [[TMP11]], align 8
1330 // CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1331 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 8
1332 // CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1333 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 8
1334 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1335 // CHECK8-NEXT:    store ptr null, ptr [[TMP14]], align 8
1336 // CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1337 // CHECK8-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 8
1338 // CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1339 // CHECK8-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 8
1340 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1341 // CHECK8-NEXT:    store ptr null, ptr [[TMP17]], align 8
1342 // CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1343 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1344 // CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1345 // CHECK8-NEXT:    store i32 2, ptr [[TMP20]], align 4
1346 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1347 // CHECK8-NEXT:    store i32 4, ptr [[TMP21]], align 4
1348 // CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1349 // CHECK8-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8
1350 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1351 // CHECK8-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
1352 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1353 // CHECK8-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP24]], align 8
1354 // CHECK8-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1355 // CHECK8-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP25]], align 8
1356 // CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1357 // CHECK8-NEXT:    store ptr null, ptr [[TMP26]], align 8
1358 // CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1359 // CHECK8-NEXT:    store ptr null, ptr [[TMP27]], align 8
1360 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1361 // CHECK8-NEXT:    store i64 2, ptr [[TMP28]], align 8
1362 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1363 // CHECK8-NEXT:    store i64 0, ptr [[TMP29]], align 8
1364 // CHECK8-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1365 // CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
1366 // CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1367 // CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
1368 // CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1369 // CHECK8-NEXT:    store i32 0, ptr [[TMP32]], align 4
1370 // CHECK8-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]])
1371 // CHECK8-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1372 // CHECK8-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1373 // CHECK8:       omp_offload.failed:
1374 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
1375 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1376 // CHECK8:       omp_offload.cont:
1377 // CHECK8-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1378 // CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1379 // CHECK8-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1380 // CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1381 // CHECK8:       arraydestroy.body:
1382 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1383 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1384 // CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1385 // CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1386 // CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1387 // CHECK8:       arraydestroy.done2:
1388 // CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1389 // CHECK8-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
1390 // CHECK8-NEXT:    ret i32 [[TMP36]]
1391 //
1392 //
1393 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1394 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1395 // CHECK8-NEXT:  entry:
1396 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1397 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1398 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1399 // CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1400 // CHECK8-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
1401 // CHECK8-NEXT:    ret void
1402 //
1403 //
1404 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1405 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1406 // CHECK8-NEXT:  entry:
1407 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1408 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1409 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1410 // CHECK8-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1411 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1412 // CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1413 // CHECK8-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1414 // CHECK8-NEXT:    store float [[TMP0]], ptr [[F]], align 4
1415 // CHECK8-NEXT:    ret void
1416 //
1417 //
1418 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1419 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1420 // CHECK8-NEXT:  entry:
1421 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1422 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1423 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1424 // CHECK8-NEXT:    ret void
1425 //
1426 //
1427 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1428 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1429 // CHECK8-NEXT:  entry:
1430 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1431 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1432 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1433 // CHECK8-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1434 // CHECK8-NEXT:    ret void
1435 //
1436 //
1437 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1438 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1439 // CHECK8-NEXT:  entry:
1440 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1441 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1442 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1443 // CHECK8-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1444 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1445 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1446 // CHECK8-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1447 // CHECK8-NEXT:    ret void
1448 //
1449 //
1450 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48
1451 // CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1452 // CHECK8-NEXT:  entry:
1453 // CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1454 // CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1455 // CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1456 // CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1457 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1458 // CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1459 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1460 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1461 // CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1462 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1463 // CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1464 // CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1465 // CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1466 // CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1467 // CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])
1468 // CHECK8-NEXT:    ret void
1469 //
1470 //
1471 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined
1472 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1473 // CHECK8-NEXT:  entry:
1474 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1475 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1476 // CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1477 // CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1478 // CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1479 // CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1480 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1481 // CHECK8-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1482 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1483 // CHECK8-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
1484 // CHECK8-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1485 // CHECK8-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1486 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1487 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1488 // CHECK8-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1489 // CHECK8-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1490 // CHECK8-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1491 // CHECK8-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1492 // CHECK8-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 8
1493 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
1494 // CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1495 // CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1496 // CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1497 // CHECK8-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1498 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1499 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1500 // CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1501 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1502 // CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1503 // CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1504 // CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1505 // CHECK8-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 8
1506 // CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
1507 // CHECK8-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 8
1508 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1509 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1510 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1511 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1512 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
1513 // CHECK8-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 4
1514 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)
1515 // CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1516 // CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1517 // CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]
1518 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1519 // CHECK8:       omp.arraycpy.body:
1520 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1521 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1522 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1523 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1524 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1525 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1526 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1527 // CHECK8:       omp.arraycpy.done6:
1528 // CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8
1529 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false)
1530 // CHECK8-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 8
1531 // CHECK8-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1532 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1533 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1534 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1535 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
1536 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1537 // CHECK8:       cond.true:
1538 // CHECK8-NEXT:    br label [[COND_END:%.*]]
1539 // CHECK8:       cond.false:
1540 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1541 // CHECK8-NEXT:    br label [[COND_END]]
1542 // CHECK8:       cond.end:
1543 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1544 // CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1545 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1546 // CHECK8-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
1547 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1548 // CHECK8:       omp.inner.for.cond:
1549 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
1550 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
1551 // CHECK8-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1552 // CHECK8-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1553 // CHECK8:       omp.inner.for.cond.cleanup:
1554 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1555 // CHECK8:       omp.inner.for.body:
1556 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]]
1557 // CHECK8-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
1558 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
1559 // CHECK8-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
1560 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP14]]
1561 // CHECK8-NEXT:    store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP14]]
1562 // CHECK8-NEXT:    [[TMP20:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP14]]
1563 // CHECK8-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP14]]
1564 // CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[VEC4]], i64 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]]), !llvm.access.group [[ACC_GRP14]]
1565 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1566 // CHECK8:       omp.inner.for.inc:
1567 // CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1568 // CHECK8-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]]
1569 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1570 // CHECK8-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1571 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
1572 // CHECK8:       omp.inner.for.end:
1573 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1574 // CHECK8:       omp.loop.exit:
1575 // CHECK8-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1576 // CHECK8-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
1577 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]])
1578 // CHECK8-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1579 // CHECK8-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1580 // CHECK8-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1581 // CHECK8:       .omp.final.then:
1582 // CHECK8-NEXT:    store i32 2, ptr [[I]], align 4
1583 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1584 // CHECK8:       .omp.final.done:
1585 // CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
1586 // CHECK8-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1587 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1588 // CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1589 // CHECK8:       arraydestroy.body:
1590 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1591 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1592 // CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1593 // CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1594 // CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1595 // CHECK8:       arraydestroy.done11:
1596 // CHECK8-NEXT:    ret void
1597 //
1598 //
1599 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined
1600 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1601 // CHECK8-NEXT:  entry:
1602 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1603 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1604 // CHECK8-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1605 // CHECK8-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1606 // CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1607 // CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1608 // CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1609 // CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1610 // CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1611 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1612 // CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1613 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1614 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1615 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1616 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1617 // CHECK8-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1618 // CHECK8-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1619 // CHECK8-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1620 // CHECK8-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8
1621 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
1622 // CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1623 // CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1624 // CHECK8-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1625 // CHECK8-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1626 // CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1627 // CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1628 // CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1629 // CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1630 // CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1631 // CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1632 // CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1633 // CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1634 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1635 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1636 // CHECK8-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1637 // CHECK8-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1638 // CHECK8-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1639 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1640 // CHECK8-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1641 // CHECK8-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1642 // CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1643 // CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1644 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)
1645 // CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1646 // CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1647 // CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
1648 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1649 // CHECK8:       omp.arraycpy.body:
1650 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1651 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1652 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1653 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1654 // CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1655 // CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
1656 // CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
1657 // CHECK8:       omp.arraycpy.done5:
1658 // CHECK8-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
1659 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false)
1660 // CHECK8-NEXT:    store ptr [[VAR6]], ptr [[_TMP7]], align 8
1661 // CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1662 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1663 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1664 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1665 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1666 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1667 // CHECK8:       cond.true:
1668 // CHECK8-NEXT:    br label [[COND_END:%.*]]
1669 // CHECK8:       cond.false:
1670 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1671 // CHECK8-NEXT:    br label [[COND_END]]
1672 // CHECK8:       cond.end:
1673 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1674 // CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1675 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1676 // CHECK8-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1677 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1678 // CHECK8:       omp.inner.for.cond:
1679 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
1680 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
1681 // CHECK8-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1682 // CHECK8-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1683 // CHECK8:       omp.inner.for.cond.cleanup:
1684 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1685 // CHECK8:       omp.inner.for.body:
1686 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
1687 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
1688 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1689 // CHECK8-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
1690 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
1691 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
1692 // CHECK8-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
1693 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1694 // CHECK8-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
1695 // CHECK8-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP17]]
1696 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
1697 // CHECK8-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
1698 // CHECK8-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]]
1699 // CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]]
1700 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1701 // CHECK8:       omp.body.continue:
1702 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1703 // CHECK8:       omp.inner.for.inc:
1704 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
1705 // CHECK8-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1
1706 // CHECK8-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
1707 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
1708 // CHECK8:       omp.inner.for.end:
1709 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1710 // CHECK8:       omp.loop.exit:
1711 // CHECK8-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1712 // CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1713 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1714 // CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1715 // CHECK8-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1716 // CHECK8-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1717 // CHECK8:       .omp.final.then:
1718 // CHECK8-NEXT:    store i32 2, ptr [[I]], align 4
1719 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1720 // CHECK8:       .omp.final.done:
1721 // CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1722 // CHECK8-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1723 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1724 // CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1725 // CHECK8:       arraydestroy.body:
1726 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1727 // CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1728 // CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1729 // CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
1730 // CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
1731 // CHECK8:       arraydestroy.done13:
1732 // CHECK8-NEXT:    ret void
1733 //
1734 //
1735 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1736 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1737 // CHECK8-NEXT:  entry:
1738 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1739 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1740 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1741 // CHECK8-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1742 // CHECK8-NEXT:    ret void
1743 //
1744 //
1745 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1746 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1747 // CHECK8-NEXT:  entry:
1748 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1749 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1750 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1751 // CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1752 // CHECK8-NEXT:    store i32 0, ptr [[F]], align 4
1753 // CHECK8-NEXT:    ret void
1754 //
1755 //
1756 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1757 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1758 // CHECK8-NEXT:  entry:
1759 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1760 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1761 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1762 // CHECK8-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1763 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1764 // CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1765 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1766 // CHECK8-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1767 // CHECK8-NEXT:    ret void
1768 //
1769 //
1770 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1771 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1772 // CHECK8-NEXT:  entry:
1773 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1774 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1775 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1776 // CHECK8-NEXT:    ret void
1777 //
1778 //
1779 // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1780 // CHECK8-SAME: () #[[ATTR6:[0-9]+]] {
1781 // CHECK8-NEXT:  entry:
1782 // CHECK8-NEXT:    call void @__tgt_register_requires(i64 1)
1783 // CHECK8-NEXT:    ret void
1784 //
1785 //
1786 // CHECK10-LABEL: define {{[^@]+}}@main
1787 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
1788 // CHECK10-NEXT:  entry:
1789 // CHECK10-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1790 // CHECK10-NEXT:    [[G:%.*]] = alloca double, align 8
1791 // CHECK10-NEXT:    [[G1:%.*]] = alloca ptr, align 4
1792 // CHECK10-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1793 // CHECK10-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1794 // CHECK10-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1795 // CHECK10-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1796 // CHECK10-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1797 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1798 // CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1799 // CHECK10-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
1800 // CHECK10-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1801 // CHECK10-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1802 // CHECK10-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1803 // CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1804 // CHECK10-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1805 // CHECK10-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1806 // CHECK10-NEXT:    store ptr [[G]], ptr [[G1]], align 4
1807 // CHECK10-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1808 // CHECK10-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1809 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
1810 // CHECK10-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1811 // CHECK10-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
1812 // CHECK10-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1
1813 // CHECK10-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
1814 // CHECK10-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1815 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1816 // CHECK10-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
1817 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1818 // CHECK10-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1819 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1820 // CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1821 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
1822 // CHECK10-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
1823 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1824 // CHECK10-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4
1825 // CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4
1826 // CHECK10-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1827 // CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP8]], align 4
1828 // CHECK10-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1829 // CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP9]], align 4
1830 // CHECK10-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1831 // CHECK10-NEXT:    store ptr null, ptr [[TMP10]], align 4
1832 // CHECK10-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1833 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP11]], align 4
1834 // CHECK10-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1835 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP12]], align 4
1836 // CHECK10-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1837 // CHECK10-NEXT:    store ptr null, ptr [[TMP13]], align 4
1838 // CHECK10-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1839 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP14]], align 4
1840 // CHECK10-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1841 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP15]], align 4
1842 // CHECK10-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1843 // CHECK10-NEXT:    store ptr null, ptr [[TMP16]], align 4
1844 // CHECK10-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1845 // CHECK10-NEXT:    store ptr [[TMP6]], ptr [[TMP17]], align 4
1846 // CHECK10-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1847 // CHECK10-NEXT:    store ptr [[TMP7]], ptr [[TMP18]], align 4
1848 // CHECK10-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1849 // CHECK10-NEXT:    store ptr null, ptr [[TMP19]], align 4
1850 // CHECK10-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1851 // CHECK10-NEXT:    store i32 [[TMP5]], ptr [[TMP20]], align 4
1852 // CHECK10-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1853 // CHECK10-NEXT:    store i32 [[TMP5]], ptr [[TMP21]], align 4
1854 // CHECK10-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1855 // CHECK10-NEXT:    store ptr null, ptr [[TMP22]], align 4
1856 // CHECK10-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1857 // CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1858 // CHECK10-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1859 // CHECK10-NEXT:    store i32 2, ptr [[TMP25]], align 4
1860 // CHECK10-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1861 // CHECK10-NEXT:    store i32 5, ptr [[TMP26]], align 4
1862 // CHECK10-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1863 // CHECK10-NEXT:    store ptr [[TMP23]], ptr [[TMP27]], align 4
1864 // CHECK10-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1865 // CHECK10-NEXT:    store ptr [[TMP24]], ptr [[TMP28]], align 4
1866 // CHECK10-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1867 // CHECK10-NEXT:    store ptr @.offload_sizes, ptr [[TMP29]], align 4
1868 // CHECK10-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1869 // CHECK10-NEXT:    store ptr @.offload_maptypes, ptr [[TMP30]], align 4
1870 // CHECK10-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1871 // CHECK10-NEXT:    store ptr null, ptr [[TMP31]], align 4
1872 // CHECK10-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1873 // CHECK10-NEXT:    store ptr null, ptr [[TMP32]], align 4
1874 // CHECK10-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1875 // CHECK10-NEXT:    store i64 2, ptr [[TMP33]], align 8
1876 // CHECK10-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1877 // CHECK10-NEXT:    store i64 0, ptr [[TMP34]], align 8
1878 // CHECK10-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1879 // CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
1880 // CHECK10-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1881 // CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
1882 // CHECK10-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1883 // CHECK10-NEXT:    store i32 0, ptr [[TMP37]], align 4
1884 // CHECK10-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.region_id, ptr [[KERNEL_ARGS]])
1885 // CHECK10-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
1886 // CHECK10-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1887 // CHECK10:       omp_offload.failed:
1888 // CHECK10-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]
1889 // CHECK10-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1890 // CHECK10:       omp_offload.cont:
1891 // CHECK10-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1892 // CHECK10-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1893 // CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1894 // CHECK10-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1895 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1896 // CHECK10:       arraydestroy.body:
1897 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1898 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1899 // CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1900 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1901 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1902 // CHECK10:       arraydestroy.done2:
1903 // CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1904 // CHECK10-NEXT:    [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
1905 // CHECK10-NEXT:    ret i32 [[TMP41]]
1906 //
1907 //
1908 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1909 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1910 // CHECK10-NEXT:  entry:
1911 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1912 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1913 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1914 // CHECK10-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1915 // CHECK10-NEXT:    ret void
1916 //
1917 //
1918 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1919 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1920 // CHECK10-NEXT:  entry:
1921 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1922 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1923 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1924 // CHECK10-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1925 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1926 // CHECK10-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1927 // CHECK10-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1928 // CHECK10-NEXT:    ret void
1929 //
1930 //
1931 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138
1932 // CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1933 // CHECK10-NEXT:  entry:
1934 // CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1935 // CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1936 // CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1937 // CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1938 // CHECK10-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
1939 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1940 // CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1941 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1942 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1943 // CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1944 // CHECK10-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
1945 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1946 // CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1947 // CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1948 // CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
1949 // CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1950 // CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])
1951 // CHECK10-NEXT:    ret void
1952 //
1953 //
1954 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined
1955 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {
1956 // CHECK10-NEXT:  entry:
1957 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1958 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1959 // CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
1960 // CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1961 // CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1962 // CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1963 // CHECK10-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 4
1964 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1965 // CHECK10-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1966 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1967 // CHECK10-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
1968 // CHECK10-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1969 // CHECK10-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1970 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1971 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1972 // CHECK10-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1973 // CHECK10-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1974 // CHECK10-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1975 // CHECK10-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1976 // CHECK10-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 4
1977 // CHECK10-NEXT:    [[SVAR9:%.*]] = alloca i32, align 4
1978 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
1979 // CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1980 // CHECK10-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
1981 // CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1982 // CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1983 // CHECK10-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1984 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1985 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1986 // CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1987 // CHECK10-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4
1988 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
1989 // CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1990 // CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1991 // CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1992 // CHECK10-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4
1993 // CHECK10-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 4
1994 // CHECK10-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1995 // CHECK10-NEXT:    store ptr [[TMP5]], ptr [[_TMP1]], align 4
1996 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1997 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1998 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1999 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2000 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
2001 // CHECK10-NEXT:    store i32 [[TMP6]], ptr [[T_VAR3]], align 4
2002 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)
2003 // CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
2004 // CHECK10-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2005 // CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]
2006 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2007 // CHECK10:       omp.arraycpy.body:
2008 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2009 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2010 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2011 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2012 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2013 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
2014 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
2015 // CHECK10:       omp.arraycpy.done6:
2016 // CHECK10-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4
2017 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false)
2018 // CHECK10-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 4
2019 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4
2020 // CHECK10-NEXT:    store i32 [[TMP9]], ptr [[SVAR9]], align 4
2021 // CHECK10-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2022 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
2023 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2024 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2025 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
2026 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2027 // CHECK10:       cond.true:
2028 // CHECK10-NEXT:    br label [[COND_END:%.*]]
2029 // CHECK10:       cond.false:
2030 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2031 // CHECK10-NEXT:    br label [[COND_END]]
2032 // CHECK10:       cond.end:
2033 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2034 // CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2035 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2036 // CHECK10-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
2037 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2038 // CHECK10:       omp.inner.for.cond:
2039 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
2040 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
2041 // CHECK10-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2042 // CHECK10-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2043 // CHECK10:       omp.inner.for.cond.cleanup:
2044 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2045 // CHECK10:       omp.inner.for.body:
2046 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]]
2047 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
2048 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]]
2049 // CHECK10-NEXT:    store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
2050 // CHECK10-NEXT:    [[TMP20:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
2051 // CHECK10-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP6]]
2052 // CHECK10-NEXT:    [[TMP22:%.*]] = load i32, ptr [[SVAR9]], align 4, !llvm.access.group [[ACC_GRP6]]
2053 // CHECK10-NEXT:    store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
2054 // CHECK10-NEXT:    [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
2055 // CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[VEC4]], i32 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]], i32 [[TMP23]]), !llvm.access.group [[ACC_GRP6]]
2056 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2057 // CHECK10:       omp.inner.for.inc:
2058 // CHECK10-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2059 // CHECK10-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]]
2060 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
2061 // CHECK10-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2062 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2063 // CHECK10:       omp.inner.for.end:
2064 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2065 // CHECK10:       omp.loop.exit:
2066 // CHECK10-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2067 // CHECK10-NEXT:    [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
2068 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]])
2069 // CHECK10-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2070 // CHECK10-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
2071 // CHECK10-NEXT:    br i1 [[TMP29]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2072 // CHECK10:       .omp.final.then:
2073 // CHECK10-NEXT:    store i32 2, ptr [[I]], align 4
2074 // CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2075 // CHECK10:       .omp.final.done:
2076 // CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
2077 // CHECK10-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
2078 // CHECK10-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2
2079 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2080 // CHECK10:       arraydestroy.body:
2081 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2082 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2083 // CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2084 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2085 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2086 // CHECK10:       arraydestroy.done12:
2087 // CHECK10-NEXT:    ret void
2088 //
2089 //
2090 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined
2091 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
2092 // CHECK10-NEXT:  entry:
2093 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2094 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2095 // CHECK10-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2096 // CHECK10-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2097 // CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2098 // CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2099 // CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2100 // CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2101 // CHECK10-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
2102 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2103 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2104 // CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2105 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2106 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2107 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2108 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2109 // CHECK10-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
2110 // CHECK10-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
2111 // CHECK10-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2112 // CHECK10-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
2113 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
2114 // CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2115 // CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2116 // CHECK10-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2117 // CHECK10-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2118 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2119 // CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2120 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2121 // CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2122 // CHECK10-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
2123 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2124 // CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2125 // CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2126 // CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2127 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2128 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2129 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2130 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2131 // CHECK10-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2132 // CHECK10-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2133 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2134 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2135 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)
2136 // CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
2137 // CHECK10-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2138 // CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
2139 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2140 // CHECK10:       omp.arraycpy.body:
2141 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2142 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2143 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2144 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2145 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2146 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
2147 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2148 // CHECK10:       omp.arraycpy.done4:
2149 // CHECK10-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4
2150 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false)
2151 // CHECK10-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
2152 // CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2153 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2154 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2155 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2156 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2157 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2158 // CHECK10:       cond.true:
2159 // CHECK10-NEXT:    br label [[COND_END:%.*]]
2160 // CHECK10:       cond.false:
2161 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2162 // CHECK10-NEXT:    br label [[COND_END]]
2163 // CHECK10:       cond.end:
2164 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2165 // CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2166 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2167 // CHECK10-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2168 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2169 // CHECK10:       omp.inner.for.cond:
2170 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
2171 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
2172 // CHECK10-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2173 // CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2174 // CHECK10:       omp.inner.for.cond.cleanup:
2175 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2176 // CHECK10:       omp.inner.for.body:
2177 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
2178 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
2179 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2180 // CHECK10-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
2181 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
2182 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
2183 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]
2184 // CHECK10-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
2185 // CHECK10-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]]
2186 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
2187 // CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]
2188 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]]
2189 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2190 // CHECK10:       omp.body.continue:
2191 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2192 // CHECK10:       omp.inner.for.inc:
2193 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
2194 // CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1
2195 // CHECK10-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
2196 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
2197 // CHECK10:       omp.inner.for.end:
2198 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2199 // CHECK10:       omp.loop.exit:
2200 // CHECK10-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2201 // CHECK10-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
2202 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
2203 // CHECK10-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2204 // CHECK10-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2205 // CHECK10-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2206 // CHECK10:       .omp.final.then:
2207 // CHECK10-NEXT:    store i32 2, ptr [[I]], align 4
2208 // CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2209 // CHECK10:       .omp.final.done:
2210 // CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2211 // CHECK10-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
2212 // CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2
2213 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2214 // CHECK10:       arraydestroy.body:
2215 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2216 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2217 // CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2218 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2219 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2220 // CHECK10:       arraydestroy.done11:
2221 // CHECK10-NEXT:    ret void
2222 //
2223 //
2224 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2225 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2226 // CHECK10-NEXT:  entry:
2227 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2228 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2229 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2230 // CHECK10-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2231 // CHECK10-NEXT:    ret void
2232 //
2233 //
2234 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2235 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat {
2236 // CHECK10-NEXT:  entry:
2237 // CHECK10-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2238 // CHECK10-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2239 // CHECK10-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2240 // CHECK10-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2241 // CHECK10-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2242 // CHECK10-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
2243 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2244 // CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2245 // CHECK10-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
2246 // CHECK10-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
2247 // CHECK10-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
2248 // CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2249 // CHECK10-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2250 // CHECK10-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2251 // CHECK10-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2252 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
2253 // CHECK10-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2254 // CHECK10-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2255 // CHECK10-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
2256 // CHECK10-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2257 // CHECK10-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
2258 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
2259 // CHECK10-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
2260 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
2261 // CHECK10-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
2262 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2263 // CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2264 // CHECK10-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
2265 // CHECK10-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2266 // CHECK10-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2267 // CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP6]], align 4
2268 // CHECK10-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2269 // CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 4
2270 // CHECK10-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2271 // CHECK10-NEXT:    store ptr null, ptr [[TMP8]], align 4
2272 // CHECK10-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2273 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 4
2274 // CHECK10-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2275 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 4
2276 // CHECK10-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2277 // CHECK10-NEXT:    store ptr null, ptr [[TMP11]], align 4
2278 // CHECK10-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2279 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 4
2280 // CHECK10-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2281 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 4
2282 // CHECK10-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2283 // CHECK10-NEXT:    store ptr null, ptr [[TMP14]], align 4
2284 // CHECK10-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2285 // CHECK10-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 4
2286 // CHECK10-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2287 // CHECK10-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 4
2288 // CHECK10-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2289 // CHECK10-NEXT:    store ptr null, ptr [[TMP17]], align 4
2290 // CHECK10-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2291 // CHECK10-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2292 // CHECK10-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2293 // CHECK10-NEXT:    store i32 2, ptr [[TMP20]], align 4
2294 // CHECK10-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2295 // CHECK10-NEXT:    store i32 4, ptr [[TMP21]], align 4
2296 // CHECK10-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2297 // CHECK10-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 4
2298 // CHECK10-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2299 // CHECK10-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
2300 // CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2301 // CHECK10-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP24]], align 4
2302 // CHECK10-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2303 // CHECK10-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP25]], align 4
2304 // CHECK10-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2305 // CHECK10-NEXT:    store ptr null, ptr [[TMP26]], align 4
2306 // CHECK10-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2307 // CHECK10-NEXT:    store ptr null, ptr [[TMP27]], align 4
2308 // CHECK10-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2309 // CHECK10-NEXT:    store i64 2, ptr [[TMP28]], align 8
2310 // CHECK10-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2311 // CHECK10-NEXT:    store i64 0, ptr [[TMP29]], align 8
2312 // CHECK10-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2313 // CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
2314 // CHECK10-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2315 // CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
2316 // CHECK10-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2317 // CHECK10-NEXT:    store i32 0, ptr [[TMP32]], align 4
2318 // CHECK10-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]])
2319 // CHECK10-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
2320 // CHECK10-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2321 // CHECK10:       omp_offload.failed:
2322 // CHECK10-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
2323 // CHECK10-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2324 // CHECK10:       omp_offload.cont:
2325 // CHECK10-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2326 // CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2327 // CHECK10-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2328 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2329 // CHECK10:       arraydestroy.body:
2330 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2331 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2332 // CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2333 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2334 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2335 // CHECK10:       arraydestroy.done2:
2336 // CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2337 // CHECK10-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
2338 // CHECK10-NEXT:    ret i32 [[TMP36]]
2339 //
2340 //
2341 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2342 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2343 // CHECK10-NEXT:  entry:
2344 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2345 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2346 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2347 // CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2348 // CHECK10-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
2349 // CHECK10-NEXT:    ret void
2350 //
2351 //
2352 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2353 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2354 // CHECK10-NEXT:  entry:
2355 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2356 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2357 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2358 // CHECK10-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2359 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2360 // CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2361 // CHECK10-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2362 // CHECK10-NEXT:    store float [[TMP0]], ptr [[F]], align 4
2363 // CHECK10-NEXT:    ret void
2364 //
2365 //
2366 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2367 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2368 // CHECK10-NEXT:  entry:
2369 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2370 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2371 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2372 // CHECK10-NEXT:    ret void
2373 //
2374 //
2375 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2376 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2377 // CHECK10-NEXT:  entry:
2378 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2379 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2380 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2381 // CHECK10-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2382 // CHECK10-NEXT:    ret void
2383 //
2384 //
2385 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2386 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2387 // CHECK10-NEXT:  entry:
2388 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2389 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2390 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2391 // CHECK10-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2392 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2393 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2394 // CHECK10-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2395 // CHECK10-NEXT:    ret void
2396 //
2397 //
2398 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48
2399 // CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2400 // CHECK10-NEXT:  entry:
2401 // CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2402 // CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2403 // CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2404 // CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2405 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2406 // CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2407 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2408 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2409 // CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2410 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2411 // CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2412 // CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2413 // CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2414 // CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2415 // CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])
2416 // CHECK10-NEXT:    ret void
2417 //
2418 //
2419 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined
2420 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2421 // CHECK10-NEXT:  entry:
2422 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2423 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2424 // CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
2425 // CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2426 // CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2427 // CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2428 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2429 // CHECK10-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2430 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2431 // CHECK10-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
2432 // CHECK10-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2433 // CHECK10-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2434 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2435 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2436 // CHECK10-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
2437 // CHECK10-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
2438 // CHECK10-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
2439 // CHECK10-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2440 // CHECK10-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 4
2441 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
2442 // CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2443 // CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2444 // CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2445 // CHECK10-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2446 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2447 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2448 // CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2449 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
2450 // CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2451 // CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2452 // CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2453 // CHECK10-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 4
2454 // CHECK10-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
2455 // CHECK10-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 4
2456 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2457 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2458 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2459 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2460 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
2461 // CHECK10-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 4
2462 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)
2463 // CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
2464 // CHECK10-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2465 // CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]
2466 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2467 // CHECK10:       omp.arraycpy.body:
2468 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2469 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2470 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2471 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2472 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2473 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2474 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
2475 // CHECK10:       omp.arraycpy.done6:
2476 // CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4
2477 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false)
2478 // CHECK10-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 4
2479 // CHECK10-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2480 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
2481 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2482 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2483 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
2484 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2485 // CHECK10:       cond.true:
2486 // CHECK10-NEXT:    br label [[COND_END:%.*]]
2487 // CHECK10:       cond.false:
2488 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2489 // CHECK10-NEXT:    br label [[COND_END]]
2490 // CHECK10:       cond.end:
2491 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2492 // CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2493 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2494 // CHECK10-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
2495 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2496 // CHECK10:       omp.inner.for.cond:
2497 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
2498 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
2499 // CHECK10-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2500 // CHECK10-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2501 // CHECK10:       omp.inner.for.cond.cleanup:
2502 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2503 // CHECK10:       omp.inner.for.body:
2504 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]]
2505 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
2506 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP15]]
2507 // CHECK10-NEXT:    store i32 [[TMP17]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]]
2508 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]]
2509 // CHECK10-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP15]]
2510 // CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[VEC4]], i32 [[TMP18]], ptr [[S_ARR5]], ptr [[TMP19]]), !llvm.access.group [[ACC_GRP15]]
2511 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2512 // CHECK10:       omp.inner.for.inc:
2513 // CHECK10-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
2514 // CHECK10-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]]
2515 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2516 // CHECK10-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
2517 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
2518 // CHECK10:       omp.inner.for.end:
2519 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2520 // CHECK10:       omp.loop.exit:
2521 // CHECK10-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2522 // CHECK10-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
2523 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])
2524 // CHECK10-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2525 // CHECK10-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2526 // CHECK10-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2527 // CHECK10:       .omp.final.then:
2528 // CHECK10-NEXT:    store i32 2, ptr [[I]], align 4
2529 // CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2530 // CHECK10:       .omp.final.done:
2531 // CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
2532 // CHECK10-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
2533 // CHECK10-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2
2534 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2535 // CHECK10:       arraydestroy.body:
2536 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2537 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2538 // CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2539 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2540 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2541 // CHECK10:       arraydestroy.done11:
2542 // CHECK10-NEXT:    ret void
2543 //
2544 //
2545 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined
2546 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2547 // CHECK10-NEXT:  entry:
2548 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2549 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2550 // CHECK10-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2551 // CHECK10-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2552 // CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2553 // CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2554 // CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2555 // CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2556 // CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2557 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2558 // CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2559 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2560 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2561 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2562 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2563 // CHECK10-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
2564 // CHECK10-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2565 // CHECK10-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2566 // CHECK10-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
2567 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
2568 // CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2569 // CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2570 // CHECK10-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2571 // CHECK10-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2572 // CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2573 // CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2574 // CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2575 // CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2576 // CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2577 // CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2578 // CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2579 // CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2580 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2581 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2582 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2583 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2584 // CHECK10-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2585 // CHECK10-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2586 // CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2587 // CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2588 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)
2589 // CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2590 // CHECK10-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2591 // CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
2592 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2593 // CHECK10:       omp.arraycpy.body:
2594 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2595 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2596 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2597 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2598 // CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2599 // CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
2600 // CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2601 // CHECK10:       omp.arraycpy.done4:
2602 // CHECK10-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4
2603 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false)
2604 // CHECK10-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
2605 // CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2606 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2607 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2608 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2609 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2610 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2611 // CHECK10:       cond.true:
2612 // CHECK10-NEXT:    br label [[COND_END:%.*]]
2613 // CHECK10:       cond.false:
2614 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2615 // CHECK10-NEXT:    br label [[COND_END]]
2616 // CHECK10:       cond.end:
2617 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2618 // CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2619 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2620 // CHECK10-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2621 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2622 // CHECK10:       omp.inner.for.cond:
2623 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
2624 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
2625 // CHECK10-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2626 // CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2627 // CHECK10:       omp.inner.for.cond.cleanup:
2628 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2629 // CHECK10:       omp.inner.for.body:
2630 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2631 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
2632 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2633 // CHECK10-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2634 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]
2635 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2636 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]
2637 // CHECK10-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]
2638 // CHECK10-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP18]]
2639 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2640 // CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]
2641 // CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]]
2642 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2643 // CHECK10:       omp.body.continue:
2644 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2645 // CHECK10:       omp.inner.for.inc:
2646 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2647 // CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1
2648 // CHECK10-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2649 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2650 // CHECK10:       omp.inner.for.end:
2651 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2652 // CHECK10:       omp.loop.exit:
2653 // CHECK10-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2654 // CHECK10-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
2655 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
2656 // CHECK10-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2657 // CHECK10-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2658 // CHECK10-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2659 // CHECK10:       .omp.final.then:
2660 // CHECK10-NEXT:    store i32 2, ptr [[I]], align 4
2661 // CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2662 // CHECK10:       .omp.final.done:
2663 // CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2664 // CHECK10-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2665 // CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2
2666 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2667 // CHECK10:       arraydestroy.body:
2668 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2669 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2670 // CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2671 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2672 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2673 // CHECK10:       arraydestroy.done11:
2674 // CHECK10-NEXT:    ret void
2675 //
2676 //
2677 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2678 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2679 // CHECK10-NEXT:  entry:
2680 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2681 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2682 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2683 // CHECK10-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2684 // CHECK10-NEXT:    ret void
2685 //
2686 //
2687 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2688 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2689 // CHECK10-NEXT:  entry:
2690 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2691 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2692 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2693 // CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2694 // CHECK10-NEXT:    store i32 0, ptr [[F]], align 4
2695 // CHECK10-NEXT:    ret void
2696 //
2697 //
2698 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2699 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2700 // CHECK10-NEXT:  entry:
2701 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2702 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2703 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2704 // CHECK10-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2705 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2706 // CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2707 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2708 // CHECK10-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2709 // CHECK10-NEXT:    ret void
2710 //
2711 //
2712 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2713 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2714 // CHECK10-NEXT:  entry:
2715 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2716 // CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2717 // CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2718 // CHECK10-NEXT:    ret void
2719 //
2720 //
2721 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2722 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] {
2723 // CHECK10-NEXT:  entry:
2724 // CHECK10-NEXT:    call void @__tgt_register_requires(i64 1)
2725 // CHECK10-NEXT:    ret void
2726 //
2727 //
2728 // CHECK12-LABEL: define {{[^@]+}}@main
2729 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
2730 // CHECK12-NEXT:  entry:
2731 // CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2732 // CHECK12-NEXT:    [[G:%.*]] = alloca double, align 8
2733 // CHECK12-NEXT:    [[G1:%.*]] = alloca ptr, align 8
2734 // CHECK12-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2735 // CHECK12-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2736 // CHECK12-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2737 // CHECK12-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2738 // CHECK12-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
2739 // CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2740 // CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2741 // CHECK12-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2742 // CHECK12-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2743 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2744 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2745 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2746 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
2747 // CHECK12-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2748 // CHECK12-NEXT:    store ptr [[G]], ptr [[G1]], align 8
2749 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2750 // CHECK12-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2751 // CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
2752 // CHECK12-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
2753 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
2754 // CHECK12-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1
2755 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
2756 // CHECK12-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
2757 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
2758 // CHECK12-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
2759 // CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8
2760 // CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
2761 // CHECK12-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 8
2762 // CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8
2763 // CHECK12-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 8
2764 // CHECK12-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2765 // CHECK12-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2766 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2767 // CHECK12-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2768 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2769 // CHECK12:       omp.inner.for.cond:
2770 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2771 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
2772 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2773 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2774 // CHECK12:       omp.inner.for.body:
2775 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2776 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2777 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2778 // CHECK12-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2779 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
2780 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2781 // CHECK12-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
2782 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
2783 // CHECK12-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
2784 // CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP2]]
2785 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2786 // CHECK12-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
2787 // CHECK12-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
2788 // CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]
2789 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2790 // CHECK12:       omp.body.continue:
2791 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2792 // CHECK12:       omp.inner.for.inc:
2793 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2794 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
2795 // CHECK12-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2796 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2797 // CHECK12:       omp.inner.for.end:
2798 // CHECK12-NEXT:    store i32 2, ptr [[I]], align 4
2799 // CHECK12-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
2800 // CHECK12-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
2801 // CHECK12-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2802 // CHECK12-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
2803 // CHECK12-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2804 // CHECK12:       arraydestroy.body:
2805 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2806 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2807 // CHECK12-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
2808 // CHECK12-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2809 // CHECK12-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2810 // CHECK12:       arraydestroy.done7:
2811 // CHECK12-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2812 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2813 // CHECK12-NEXT:    ret i32 [[TMP14]]
2814 //
2815 //
2816 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2817 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2818 // CHECK12-NEXT:  entry:
2819 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2820 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2821 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2822 // CHECK12-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2823 // CHECK12-NEXT:    ret void
2824 //
2825 //
2826 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2827 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2828 // CHECK12-NEXT:  entry:
2829 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2830 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2831 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2832 // CHECK12-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2833 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2834 // CHECK12-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2835 // CHECK12-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2836 // CHECK12-NEXT:    ret void
2837 //
2838 //
2839 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2840 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] comdat {
2841 // CHECK12-NEXT:  entry:
2842 // CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2843 // CHECK12-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2844 // CHECK12-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2845 // CHECK12-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2846 // CHECK12-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2847 // CHECK12-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
2848 // CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2849 // CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2850 // CHECK12-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2851 // CHECK12-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2852 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2853 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2854 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2855 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
2856 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2857 // CHECK12-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2858 // CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
2859 // CHECK12-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
2860 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
2861 // CHECK12-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
2862 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
2863 // CHECK12-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
2864 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
2865 // CHECK12-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
2866 // CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8
2867 // CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
2868 // CHECK12-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 8
2869 // CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8
2870 // CHECK12-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 8
2871 // CHECK12-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2872 // CHECK12-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2873 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2874 // CHECK12-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2875 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2876 // CHECK12:       omp.inner.for.cond:
2877 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
2878 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
2879 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2880 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2881 // CHECK12:       omp.inner.for.body:
2882 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2883 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2884 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2885 // CHECK12-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2886 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]]
2887 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2888 // CHECK12-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
2889 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
2890 // CHECK12-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
2891 // CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP6]]
2892 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2893 // CHECK12-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
2894 // CHECK12-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
2895 // CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
2896 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2897 // CHECK12:       omp.body.continue:
2898 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2899 // CHECK12:       omp.inner.for.inc:
2900 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2901 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
2902 // CHECK12-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2903 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2904 // CHECK12:       omp.inner.for.end:
2905 // CHECK12-NEXT:    store i32 2, ptr [[I]], align 4
2906 // CHECK12-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2907 // CHECK12-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2908 // CHECK12-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
2909 // CHECK12-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2910 // CHECK12:       arraydestroy.body:
2911 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2912 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2913 // CHECK12-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2914 // CHECK12-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2915 // CHECK12-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2916 // CHECK12:       arraydestroy.done7:
2917 // CHECK12-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2918 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2919 // CHECK12-NEXT:    ret i32 [[TMP14]]
2920 //
2921 //
2922 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2923 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2924 // CHECK12-NEXT:  entry:
2925 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2926 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2927 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2928 // CHECK12-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2929 // CHECK12-NEXT:    ret void
2930 //
2931 //
2932 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2933 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2934 // CHECK12-NEXT:  entry:
2935 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2936 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2937 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2938 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2939 // CHECK12-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
2940 // CHECK12-NEXT:    ret void
2941 //
2942 //
2943 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2944 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2945 // CHECK12-NEXT:  entry:
2946 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2947 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2948 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2949 // CHECK12-NEXT:    ret void
2950 //
2951 //
2952 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2953 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2954 // CHECK12-NEXT:  entry:
2955 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2956 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2957 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2958 // CHECK12-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2959 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2960 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2961 // CHECK12-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2962 // CHECK12-NEXT:    store float [[TMP0]], ptr [[F]], align 4
2963 // CHECK12-NEXT:    ret void
2964 //
2965 //
2966 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2967 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2968 // CHECK12-NEXT:  entry:
2969 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2970 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2971 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2972 // CHECK12-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2973 // CHECK12-NEXT:    ret void
2974 //
2975 //
2976 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2977 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2978 // CHECK12-NEXT:  entry:
2979 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2980 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2981 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2982 // CHECK12-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2983 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2984 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2985 // CHECK12-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
2986 // CHECK12-NEXT:    ret void
2987 //
2988 //
2989 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2990 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2991 // CHECK12-NEXT:  entry:
2992 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2993 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2994 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2995 // CHECK12-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2996 // CHECK12-NEXT:    ret void
2997 //
2998 //
2999 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3000 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3001 // CHECK12-NEXT:  entry:
3002 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3003 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3004 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3005 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
3006 // CHECK12-NEXT:    store i32 0, ptr [[F]], align 4
3007 // CHECK12-NEXT:    ret void
3008 //
3009 //
3010 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3011 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3012 // CHECK12-NEXT:  entry:
3013 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3014 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3015 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3016 // CHECK12-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3017 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3018 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
3019 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3020 // CHECK12-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
3021 // CHECK12-NEXT:    ret void
3022 //
3023 //
3024 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3025 // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3026 // CHECK12-NEXT:  entry:
3027 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3028 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3029 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3030 // CHECK12-NEXT:    ret void
3031 //
3032 //
3033 // CHECK14-LABEL: define {{[^@]+}}@main
3034 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] {
3035 // CHECK14-NEXT:  entry:
3036 // CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3037 // CHECK14-NEXT:    [[G:%.*]] = alloca double, align 8
3038 // CHECK14-NEXT:    [[G1:%.*]] = alloca ptr, align 4
3039 // CHECK14-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3040 // CHECK14-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
3041 // CHECK14-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
3042 // CHECK14-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3043 // CHECK14-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
3044 // CHECK14-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
3045 // CHECK14-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
3046 // CHECK14-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
3047 // CHECK14-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
3048 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3049 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3050 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3051 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
3052 // CHECK14-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3053 // CHECK14-NEXT:    store ptr [[G]], ptr [[G1]], align 4
3054 // CHECK14-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
3055 // CHECK14-NEXT:    store i32 0, ptr [[T_VAR]], align 4
3056 // CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
3057 // CHECK14-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
3058 // CHECK14-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
3059 // CHECK14-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1
3060 // CHECK14-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
3061 // CHECK14-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
3062 // CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
3063 // CHECK14-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
3064 // CHECK14-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4
3065 // CHECK14-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
3066 // CHECK14-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 4
3067 // CHECK14-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4
3068 // CHECK14-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 4
3069 // CHECK14-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3070 // CHECK14-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
3071 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3072 // CHECK14-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3073 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3074 // CHECK14:       omp.inner.for.cond:
3075 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
3076 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
3077 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3078 // CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3079 // CHECK14:       omp.inner.for.body:
3080 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
3081 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3082 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3083 // CHECK14-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
3084 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]]
3085 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
3086 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
3087 // CHECK14-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
3088 // CHECK14-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP3]]
3089 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
3090 // CHECK14-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
3091 // CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]
3092 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3093 // CHECK14:       omp.body.continue:
3094 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3095 // CHECK14:       omp.inner.for.inc:
3096 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
3097 // CHECK14-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
3098 // CHECK14-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
3099 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3100 // CHECK14:       omp.inner.for.end:
3101 // CHECK14-NEXT:    store i32 2, ptr [[I]], align 4
3102 // CHECK14-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
3103 // CHECK14-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
3104 // CHECK14-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
3105 // CHECK14-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
3106 // CHECK14-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3107 // CHECK14:       arraydestroy.body:
3108 // CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3109 // CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3110 // CHECK14-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
3111 // CHECK14-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3112 // CHECK14-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
3113 // CHECK14:       arraydestroy.done6:
3114 // CHECK14-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
3115 // CHECK14-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
3116 // CHECK14-NEXT:    ret i32 [[TMP14]]
3117 //
3118 //
3119 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3120 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3121 // CHECK14-NEXT:  entry:
3122 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3123 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3124 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3125 // CHECK14-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3126 // CHECK14-NEXT:    ret void
3127 //
3128 //
3129 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3130 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3131 // CHECK14-NEXT:  entry:
3132 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3133 // CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3134 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3135 // CHECK14-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
3136 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3137 // CHECK14-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
3138 // CHECK14-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
3139 // CHECK14-NEXT:    ret void
3140 //
3141 //
3142 // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3143 // CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat {
3144 // CHECK14-NEXT:  entry:
3145 // CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3146 // CHECK14-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3147 // CHECK14-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
3148 // CHECK14-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
3149 // CHECK14-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3150 // CHECK14-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
3151 // CHECK14-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
3152 // CHECK14-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
3153 // CHECK14-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
3154 // CHECK14-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
3155 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3156 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3157 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3158 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
3159 // CHECK14-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
3160 // CHECK14-NEXT:    store i32 0, ptr [[T_VAR]], align 4
3161 // CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
3162 // CHECK14-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
3163 // CHECK14-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
3164 // CHECK14-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
3165 // CHECK14-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
3166 // CHECK14-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
3167 // CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
3168 // CHECK14-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
3169 // CHECK14-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4
3170 // CHECK14-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
3171 // CHECK14-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 4
3172 // CHECK14-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4
3173 // CHECK14-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 4
3174 // CHECK14-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3175 // CHECK14-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
3176 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3177 // CHECK14-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3178 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3179 // CHECK14:       omp.inner.for.cond:
3180 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
3181 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
3182 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3183 // CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3184 // CHECK14:       omp.inner.for.body:
3185 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
3186 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3187 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3188 // CHECK14-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
3189 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]]
3190 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
3191 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
3192 // CHECK14-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
3193 // CHECK14-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP7]]
3194 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
3195 // CHECK14-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
3196 // CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]
3197 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3198 // CHECK14:       omp.body.continue:
3199 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3200 // CHECK14:       omp.inner.for.inc:
3201 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
3202 // CHECK14-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
3203 // CHECK14-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
3204 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
3205 // CHECK14:       omp.inner.for.end:
3206 // CHECK14-NEXT:    store i32 2, ptr [[I]], align 4
3207 // CHECK14-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3208 // CHECK14-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
3209 // CHECK14-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
3210 // CHECK14-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3211 // CHECK14:       arraydestroy.body:
3212 // CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3213 // CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3214 // CHECK14-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3215 // CHECK14-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3216 // CHECK14-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
3217 // CHECK14:       arraydestroy.done6:
3218 // CHECK14-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
3219 // CHECK14-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
3220 // CHECK14-NEXT:    ret i32 [[TMP14]]
3221 //
3222 //
3223 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3224 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3225 // CHECK14-NEXT:  entry:
3226 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3227 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3228 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3229 // CHECK14-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
3230 // CHECK14-NEXT:    ret void
3231 //
3232 //
3233 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3234 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3235 // CHECK14-NEXT:  entry:
3236 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3237 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3238 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3239 // CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3240 // CHECK14-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
3241 // CHECK14-NEXT:    ret void
3242 //
3243 //
3244 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3245 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3246 // CHECK14-NEXT:  entry:
3247 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3248 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3249 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3250 // CHECK14-NEXT:    ret void
3251 //
3252 //
3253 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3254 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3255 // CHECK14-NEXT:  entry:
3256 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3257 // CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3258 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3259 // CHECK14-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
3260 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3261 // CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3262 // CHECK14-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
3263 // CHECK14-NEXT:    store float [[TMP0]], ptr [[F]], align 4
3264 // CHECK14-NEXT:    ret void
3265 //
3266 //
3267 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3268 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3269 // CHECK14-NEXT:  entry:
3270 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3271 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3272 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3273 // CHECK14-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3274 // CHECK14-NEXT:    ret void
3275 //
3276 //
3277 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3278 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3279 // CHECK14-NEXT:  entry:
3280 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3281 // CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3282 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3283 // CHECK14-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3284 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3285 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3286 // CHECK14-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
3287 // CHECK14-NEXT:    ret void
3288 //
3289 //
3290 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3291 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3292 // CHECK14-NEXT:  entry:
3293 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3294 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3295 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3296 // CHECK14-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
3297 // CHECK14-NEXT:    ret void
3298 //
3299 //
3300 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3301 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3302 // CHECK14-NEXT:  entry:
3303 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3304 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3305 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3306 // CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
3307 // CHECK14-NEXT:    store i32 0, ptr [[F]], align 4
3308 // CHECK14-NEXT:    ret void
3309 //
3310 //
3311 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3312 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3313 // CHECK14-NEXT:  entry:
3314 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3315 // CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3316 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3317 // CHECK14-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3318 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3319 // CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
3320 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3321 // CHECK14-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
3322 // CHECK14-NEXT:    ret void
3323 //
3324 //
3325 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3326 // CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3327 // CHECK14-NEXT:  entry:
3328 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3329 // CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3330 // CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3331 // CHECK14-NEXT:    ret void
3332 //