clang/test/OpenMP/distribute_simd_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test host codegen.
   3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
   9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5
  11 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5| FileCheck %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5
  14 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
  20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  22 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
  23 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5
  24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
  25 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
  26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5
  27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
  28
  29 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)
  30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17
  32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17
  34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19
  36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19
  38 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5
  39 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21
  40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5
  41 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21
  42 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5
  43 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23
  44 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5
  45 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23
  46
  47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
  49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
  53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  55 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5
  56 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
  57 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5
  58 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
  59 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5
  60 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
  61 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5
  62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
  63
  64 // expected-no-diagnostics
  65 #ifndef HEADER
  66 #define HEADER
  67
  68
  69 void without_schedule_clause(float *a, float *b, float *c, float *d) {
  70   #pragma omp target
  71   #pragma omp teams
  72 #ifdef OMP5
  73   #pragma omp distribute simd simdlen(8) aligned(a) if(true)
  74 #else
  75   #pragma omp distribute simd simdlen(8) aligned(a)
  76 #endif // OMP5
  77   for (int i = 33; i < 32000000; i += 7) {
  78     a[i] = b[i] * c[i] * d[i];
  79   }
  80 }
  81
  82 // ... loop body ...
  83
  84
  85 void static_not_chunked(float *a, float *b, float *c, float *d) {
  86   #pragma omp target
  87   #pragma omp teams
  88 #ifdef OMP5
  89   #pragma omp distribute simd dist_schedule(static) safelen(32) if(simd: true) nontemporal(a, b)
  90 #else
  91   #pragma omp distribute simd dist_schedule(static) safelen(32)
  92 #endif // OMP5
  93   for (int i = 32000000; i > 33; i += -7) {
  94         a[i] = b[i] * c[i] * d[i];
  95   }
  96 }
  97
  98 // ... loop body ...
  99
 100
 101
 102 void static_chunked(float *a, float *b, float *c, float *d) {
 103   #pragma omp target
 104   #pragma omp teams
 105 #pragma omp distribute simd dist_schedule(static, 5)
 106   for (unsigned i = 131071; i <= 2147483647; i += 127) {
 107     a[i] = b[i] * c[i] * d[i];
 108   }
 109 }
 110
 111 // ... loop body ...
 112
 113 void test_precond() {
 114   char a = 0; char i;
 115   #pragma omp target
 116   #pragma omp teams
 117 #ifdef OMP5
 118   #pragma omp distribute simd linear(i) if(a) nontemporal(i)
 119 #else
 120   #pragma omp distribute simd linear(i)
 121 #endif // OMP5
 122   for(i = a; i < 10; ++i);
 123 }
 124
 125 // a is passed as a parameter to the outlined functions
 126 // ..many loads of %0..
 127
 128 // no templates for now, as these require special handling in target regions and/or declare target
 129
 130
 131 template <typename T>
 132 T ftemplate() {
 133   short aa = 0;
 134
 135 #pragma omp target
 136 #pragma omp teams
 137 #pragma omp distribute simd dist_schedule(static, aa)
 138   for (int i = 0; i < 100; i++) {
 139   }
 140   return T();
 141 }
 142
 143 int fint(void) { return ftemplate<int>(); }
 144
 145 #endif
 146
 147 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
 148 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
 149 // CHECK1-NEXT:  entry:
 150 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 151 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 152 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 153 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 154 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
 155 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
 156 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
 157 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 158 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 159 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 160 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 161 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 162 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 163 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 164 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 165 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 166 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 167 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 168 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
 169 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 170 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 8
 171 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 172 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 173 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 174 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
 175 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 176 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
 177 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 178 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
 179 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 180 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 8
 181 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 182 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 8
 183 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 184 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 185 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 186 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
 187 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 188 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
 189 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 190 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
 191 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 192 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 193 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 194 // CHECK1-NEXT:    store i32 2, ptr [[TMP18]], align 4
 195 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 196 // CHECK1-NEXT:    store i32 4, ptr [[TMP19]], align 4
 197 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 198 // CHECK1-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
 199 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 200 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
 201 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 202 // CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP22]], align 8
 203 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 204 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP23]], align 8
 205 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 206 // CHECK1-NEXT:    store ptr null, ptr [[TMP24]], align 8
 207 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 208 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
 209 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 210 // CHECK1-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
 211 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 212 // CHECK1-NEXT:    store i64 0, ptr [[TMP27]], align 8
 213 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 214 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
 215 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 216 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
 217 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 218 // CHECK1-NEXT:    store i32 0, ptr [[TMP30]], align 4
 219 // CHECK1-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]])
 220 // CHECK1-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
 221 // CHECK1-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 222 // CHECK1:       omp_offload.failed:
 223 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]]
 224 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 225 // CHECK1:       omp_offload.cont:
 226 // CHECK1-NEXT:    ret void
 227 //
 228 //
 229 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
 230 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
 231 // CHECK1-NEXT:  entry:
 232 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 233 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 234 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 235 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 236 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 237 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 238 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 239 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 240 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 241 // CHECK1-NEXT:    ret void
 242 //
 243 //
 244 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
 245 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 246 // CHECK1-NEXT:  entry:
 247 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 248 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 249 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 250 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 251 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 252 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 253 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 254 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 255 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 256 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 257 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 258 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 259 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 260 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 261 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 262 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 263 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 264 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 265 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 266 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 267 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 268 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 269 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 270 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8
 271 // CHECK1-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ]
 272 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 273 // CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 274 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 275 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 276 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 277 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 278 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 279 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 280 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
 281 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 282 // CHECK1:       cond.true:
 283 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 284 // CHECK1:       cond.false:
 285 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 286 // CHECK1-NEXT:    br label [[COND_END]]
 287 // CHECK1:       cond.end:
 288 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
 289 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 290 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 291 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
 292 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 293 // CHECK1:       omp.inner.for.cond:
 294 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
 295 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
 296 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
 297 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 298 // CHECK1:       omp.inner.for.body:
 299 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
 300 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
 301 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
 302 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
 303 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
 304 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
 305 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
 306 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
 307 // CHECK1-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
 308 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
 309 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
 310 // CHECK1-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
 311 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]]
 312 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP8]]
 313 // CHECK1-NEXT:    [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
 314 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
 315 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
 316 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
 317 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]]
 318 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
 319 // CHECK1-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
 320 // CHECK1-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
 321 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
 322 // CHECK1-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
 323 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]]
 324 // CHECK1-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]]
 325 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 326 // CHECK1:       omp.body.continue:
 327 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 328 // CHECK1:       omp.inner.for.inc:
 329 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
 330 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
 331 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
 332 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
 333 // CHECK1:       omp.inner.for.end:
 334 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 335 // CHECK1:       omp.loop.exit:
 336 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
 337 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 338 // CHECK1-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
 339 // CHECK1-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 340 // CHECK1:       .omp.final.then:
 341 // CHECK1-NEXT:    store i32 32000001, ptr [[I]], align 4
 342 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 343 // CHECK1:       .omp.final.done:
 344 // CHECK1-NEXT:    ret void
 345 //
 346 //
 347 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
 348 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 349 // CHECK1-NEXT:  entry:
 350 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 351 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 352 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 353 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 354 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
 355 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
 356 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
 357 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 358 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 359 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 360 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 361 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 362 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 363 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 364 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 365 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 366 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 367 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 368 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
 369 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 370 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 8
 371 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 372 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 373 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 374 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
 375 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 376 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
 377 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 378 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
 379 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 380 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 8
 381 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 382 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 8
 383 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 384 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 385 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 386 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
 387 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 388 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
 389 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 390 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
 391 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 392 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 393 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 394 // CHECK1-NEXT:    store i32 2, ptr [[TMP18]], align 4
 395 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 396 // CHECK1-NEXT:    store i32 4, ptr [[TMP19]], align 4
 397 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 398 // CHECK1-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
 399 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 400 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
 401 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 402 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP22]], align 8
 403 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 404 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8
 405 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 406 // CHECK1-NEXT:    store ptr null, ptr [[TMP24]], align 8
 407 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 408 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
 409 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 410 // CHECK1-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
 411 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 412 // CHECK1-NEXT:    store i64 0, ptr [[TMP27]], align 8
 413 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 414 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
 415 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 416 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
 417 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 418 // CHECK1-NEXT:    store i32 0, ptr [[TMP30]], align 4
 419 // CHECK1-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]])
 420 // CHECK1-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
 421 // CHECK1-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 422 // CHECK1:       omp_offload.failed:
 423 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
 424 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 425 // CHECK1:       omp_offload.cont:
 426 // CHECK1-NEXT:    ret void
 427 //
 428 //
 429 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
 430 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
 431 // CHECK1-NEXT:  entry:
 432 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 433 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 434 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 435 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 436 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 437 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 438 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 439 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 440 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 441 // CHECK1-NEXT:    ret void
 442 //
 443 //
 444 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
 445 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 446 // CHECK1-NEXT:  entry:
 447 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 448 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 449 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 450 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 451 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 452 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 453 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 454 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 455 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 456 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 457 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 458 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 459 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 460 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 461 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 462 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 463 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 464 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 465 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 466 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 467 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 468 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 469 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 470 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 471 // CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 472 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 473 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 474 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 475 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 476 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 477 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 478 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
 479 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 480 // CHECK1:       cond.true:
 481 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 482 // CHECK1:       cond.false:
 483 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 484 // CHECK1-NEXT:    br label [[COND_END]]
 485 // CHECK1:       cond.end:
 486 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 487 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 488 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 489 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 490 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 491 // CHECK1:       omp.inner.for.cond:
 492 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 493 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 494 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 495 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 496 // CHECK1:       omp.inner.for.body:
 497 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 498 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
 499 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
 500 // CHECK1-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
 501 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
 502 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 503 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
 504 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
 505 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 506 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
 507 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
 508 // CHECK1-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
 509 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
 510 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
 511 // CHECK1-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
 512 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
 513 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
 514 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
 515 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
 516 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
 517 // CHECK1-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
 518 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
 519 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
 520 // CHECK1-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
 521 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
 522 // CHECK1-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
 523 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 524 // CHECK1:       omp.body.continue:
 525 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 526 // CHECK1:       omp.inner.for.inc:
 527 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 528 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
 529 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 530 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
 531 // CHECK1:       omp.inner.for.end:
 532 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 533 // CHECK1:       omp.loop.exit:
 534 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
 535 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 536 // CHECK1-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
 537 // CHECK1-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 538 // CHECK1:       .omp.final.then:
 539 // CHECK1-NEXT:    store i32 32, ptr [[I]], align 4
 540 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 541 // CHECK1:       .omp.final.done:
 542 // CHECK1-NEXT:    ret void
 543 //
 544 //
 545 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
 546 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 547 // CHECK1-NEXT:  entry:
 548 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 549 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 550 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 551 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 552 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
 553 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
 554 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
 555 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 556 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 557 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 558 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 559 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 560 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 561 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 562 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 563 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 564 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 565 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 566 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
 567 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 568 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 8
 569 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 570 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 571 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 572 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
 573 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 574 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
 575 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 576 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
 577 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 578 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 8
 579 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 580 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 8
 581 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 582 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 583 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 584 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
 585 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 586 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
 587 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 588 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
 589 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 590 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 591 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 592 // CHECK1-NEXT:    store i32 2, ptr [[TMP18]], align 4
 593 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 594 // CHECK1-NEXT:    store i32 4, ptr [[TMP19]], align 4
 595 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 596 // CHECK1-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
 597 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 598 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
 599 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 600 // CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP22]], align 8
 601 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 602 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8
 603 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 604 // CHECK1-NEXT:    store ptr null, ptr [[TMP24]], align 8
 605 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 606 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
 607 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 608 // CHECK1-NEXT:    store i64 16908289, ptr [[TMP26]], align 8
 609 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 610 // CHECK1-NEXT:    store i64 0, ptr [[TMP27]], align 8
 611 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 612 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
 613 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 614 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
 615 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 616 // CHECK1-NEXT:    store i32 0, ptr [[TMP30]], align 4
 617 // CHECK1-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]])
 618 // CHECK1-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
 619 // CHECK1-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 620 // CHECK1:       omp_offload.failed:
 621 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
 622 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 623 // CHECK1:       omp_offload.cont:
 624 // CHECK1-NEXT:    ret void
 625 //
 626 //
 627 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
 628 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
 629 // CHECK1-NEXT:  entry:
 630 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 631 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 632 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 633 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 634 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 635 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 636 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 637 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 638 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 639 // CHECK1-NEXT:    ret void
 640 //
 641 //
 642 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
 643 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 644 // CHECK1-NEXT:  entry:
 645 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 646 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 647 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 648 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 649 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 650 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 651 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 652 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 653 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 654 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 655 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 656 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 657 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 658 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 659 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 660 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 661 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 662 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 663 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 664 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 665 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 666 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 667 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 668 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 669 // CHECK1-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
 670 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 671 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 672 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 673 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 674 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
 675 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 676 // CHECK1:       omp.dispatch.cond:
 677 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 678 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
 679 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 680 // CHECK1:       cond.true:
 681 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 682 // CHECK1:       cond.false:
 683 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 684 // CHECK1-NEXT:    br label [[COND_END]]
 685 // CHECK1:       cond.end:
 686 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 687 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 688 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 689 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 690 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 691 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 692 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
 693 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 694 // CHECK1:       omp.dispatch.body:
 695 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 696 // CHECK1:       omp.inner.for.cond:
 697 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
 698 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
 699 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
 700 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 701 // CHECK1:       omp.inner.for.body:
 702 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
 703 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
 704 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
 705 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 706 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP17]]
 707 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 708 // CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
 709 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
 710 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
 711 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP17]]
 712 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 713 // CHECK1-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
 714 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
 715 // CHECK1-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP17]]
 716 // CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
 717 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP17]]
 718 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 719 // CHECK1-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
 720 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
 721 // CHECK1-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]]
 722 // CHECK1-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
 723 // CHECK1-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP17]]
 724 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 725 // CHECK1-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
 726 // CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
 727 // CHECK1-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP17]]
 728 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 729 // CHECK1:       omp.body.continue:
 730 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 731 // CHECK1:       omp.inner.for.inc:
 732 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
 733 // CHECK1-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
 734 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
 735 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
 736 // CHECK1:       omp.inner.for.end:
 737 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 738 // CHECK1:       omp.dispatch.inc:
 739 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 740 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 741 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
 742 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
 743 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 744 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 745 // CHECK1-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
 746 // CHECK1-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
 747 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 748 // CHECK1:       omp.dispatch.end:
 749 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
 750 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 751 // CHECK1-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
 752 // CHECK1-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 753 // CHECK1:       .omp.final.then:
 754 // CHECK1-NEXT:    store i32 -2147483522, ptr [[I]], align 4
 755 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 756 // CHECK1:       .omp.final.done:
 757 // CHECK1-NEXT:    ret void
 758 //
 759 //
 760 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv
 761 // CHECK1-SAME: () #[[ATTR0]] {
 762 // CHECK1-NEXT:  entry:
 763 // CHECK1-NEXT:    [[A:%.*]] = alloca i8, align 1
 764 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
 765 // CHECK1-NEXT:    [[I_CASTED:%.*]] = alloca i64, align 8
 766 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 767 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
 768 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
 769 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
 770 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 771 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 772 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 773 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 774 // CHECK1-NEXT:    store i8 0, ptr [[A]], align 1
 775 // CHECK1-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 1
 776 // CHECK1-NEXT:    store i8 [[TMP0]], ptr [[I_CASTED]], align 1
 777 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[I_CASTED]], align 8
 778 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8, ptr [[A]], align 1
 779 // CHECK1-NEXT:    store i8 [[TMP2]], ptr [[A_CASTED]], align 1
 780 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8
 781 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 782 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP4]], align 8
 783 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 784 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
 785 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 786 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 787 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 788 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP7]], align 8
 789 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 790 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
 791 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 792 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
 793 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 794 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 795 // CHECK1-NEXT:    [[TMP12:%.*]] = load i8, ptr [[A]], align 1
 796 // CHECK1-NEXT:    store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1
 797 // CHECK1-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 798 // CHECK1-NEXT:    [[CONV:%.*]] = sext i8 [[TMP13]] to i32
 799 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
 800 // CHECK1-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
 801 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
 802 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 803 // CHECK1-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
 804 // CHECK1-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 805 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 806 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
 807 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[ADD4]] to i64
 808 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 809 // CHECK1-NEXT:    store i32 2, ptr [[TMP16]], align 4
 810 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 811 // CHECK1-NEXT:    store i32 2, ptr [[TMP17]], align 4
 812 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 813 // CHECK1-NEXT:    store ptr [[TMP10]], ptr [[TMP18]], align 8
 814 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 815 // CHECK1-NEXT:    store ptr [[TMP11]], ptr [[TMP19]], align 8
 816 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 817 // CHECK1-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP20]], align 8
 818 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 819 // CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP21]], align 8
 820 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 821 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
 822 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 823 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
 824 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 825 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP24]], align 8
 826 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 827 // CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 8
 828 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 829 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
 830 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 831 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
 832 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 833 // CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 4
 834 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]])
 835 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
 836 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 837 // CHECK1:       omp_offload.failed:
 838 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
 839 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 840 // CHECK1:       omp_offload.cont:
 841 // CHECK1-NEXT:    ret void
 842 //
 843 //
 844 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
 845 // CHECK1-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
 846 // CHECK1-NEXT:  entry:
 847 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca i64, align 8
 848 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 849 // CHECK1-NEXT:    store i64 [[I]], ptr [[I_ADDR]], align 8
 850 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 851 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
 852 // CHECK1-NEXT:    ret void
 853 //
 854 //
 855 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
 856 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
 857 // CHECK1-NEXT:  entry:
 858 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 859 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 860 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
 861 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 862 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 863 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 864 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 865 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 866 // CHECK1-NEXT:    [[I4:%.*]] = alloca i8, align 1
 867 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 868 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 869 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 870 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 871 // CHECK1-NEXT:    [[I6:%.*]] = alloca i8, align 1
 872 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 873 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 874 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
 875 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 876 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
 877 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 878 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
 879 // CHECK1-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
 880 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 881 // CHECK1-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
 882 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
 883 // CHECK1-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
 884 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
 885 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 886 // CHECK1-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
 887 // CHECK1-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 888 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 889 // CHECK1-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
 890 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 891 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
 892 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
 893 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 894 // CHECK1:       omp.precond.then:
 895 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 896 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 897 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
 898 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 899 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 900 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 901 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
 902 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 903 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 904 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 905 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
 906 // CHECK1-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 907 // CHECK1:       cond.true:
 908 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 909 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 910 // CHECK1:       cond.false:
 911 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 912 // CHECK1-NEXT:    br label [[COND_END]]
 913 // CHECK1:       cond.end:
 914 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
 915 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 916 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 917 // CHECK1-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
 918 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 919 // CHECK1:       omp.inner.for.cond:
 920 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
 921 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]
 922 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
 923 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 924 // CHECK1:       omp.inner.for.body:
 925 // CHECK1-NEXT:    [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP20]]
 926 // CHECK1-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
 927 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
 928 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
 929 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
 930 // CHECK1-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
 931 // CHECK1-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP20]]
 932 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 933 // CHECK1:       omp.body.continue:
 934 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 935 // CHECK1:       omp.inner.for.inc:
 936 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
 937 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
 938 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
 939 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
 940 // CHECK1:       omp.inner.for.end:
 941 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 942 // CHECK1:       omp.loop.exit:
 943 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 944 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
 945 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
 946 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 947 // CHECK1-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
 948 // CHECK1-NEXT:    br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 949 // CHECK1:       .omp.final.then:
 950 // CHECK1-NEXT:    [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 951 // CHECK1-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
 952 // CHECK1-NEXT:    [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 953 // CHECK1-NEXT:    [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
 954 // CHECK1-NEXT:    [[SUB15:%.*]] = sub i32 10, [[CONV14]]
 955 // CHECK1-NEXT:    [[SUB16:%.*]] = sub i32 [[SUB15]], 1
 956 // CHECK1-NEXT:    [[ADD17:%.*]] = add i32 [[SUB16]], 1
 957 // CHECK1-NEXT:    [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
 958 // CHECK1-NEXT:    [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
 959 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
 960 // CHECK1-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
 961 // CHECK1-NEXT:    store i8 [[CONV21]], ptr [[TMP0]], align 1
 962 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 963 // CHECK1:       .omp.final.done:
 964 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 965 // CHECK1:       omp.precond.end:
 966 // CHECK1-NEXT:    ret void
 967 //
 968 //
 969 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv
 970 // CHECK1-SAME: () #[[ATTR0]] {
 971 // CHECK1-NEXT:  entry:
 972 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
 973 // CHECK1-NEXT:    ret i32 [[CALL]]
 974 //
 975 //
 976 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
 977 // CHECK1-SAME: () #[[ATTR0]] comdat {
 978 // CHECK1-NEXT:  entry:
 979 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
 980 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 981 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
 982 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
 983 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
 984 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 985 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 986 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
 987 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA]], align 2
 988 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
 989 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 990 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 991 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP2]], align 8
 992 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 993 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP3]], align 8
 994 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 995 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 996 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 997 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 998 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 999 // CHECK1-NEXT:    store i32 2, ptr [[TMP7]], align 4
1000 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1001 // CHECK1-NEXT:    store i32 1, ptr [[TMP8]], align 4
1002 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1003 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 8
1004 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1005 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 8
1006 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1007 // CHECK1-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP11]], align 8
1008 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1009 // CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP12]], align 8
1010 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1011 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
1012 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1013 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
1014 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1015 // CHECK1-NEXT:    store i64 100, ptr [[TMP15]], align 8
1016 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1017 // CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8
1018 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1019 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
1020 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1021 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
1022 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1023 // CHECK1-NEXT:    store i32 0, ptr [[TMP19]], align 4
1024 // CHECK1-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]])
1025 // CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1026 // CHECK1-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1027 // CHECK1:       omp_offload.failed:
1028 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
1029 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1030 // CHECK1:       omp_offload.cont:
1031 // CHECK1-NEXT:    ret i32 0
1032 //
1033 //
1034 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
1035 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] {
1036 // CHECK1-NEXT:  entry:
1037 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1038 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1039 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
1040 // CHECK1-NEXT:    ret void
1041 //
1042 //
1043 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
1044 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
1045 // CHECK1-NEXT:  entry:
1046 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1047 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1048 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
1049 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1050 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1051 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1052 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1053 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1054 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1055 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1056 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1057 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1058 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
1059 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
1060 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1061 // CHECK1-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
1062 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1063 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1064 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
1065 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1066 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1067 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1068 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
1069 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1070 // CHECK1:       omp.dispatch.cond:
1071 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1072 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1073 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1074 // CHECK1:       cond.true:
1075 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1076 // CHECK1:       cond.false:
1077 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1078 // CHECK1-NEXT:    br label [[COND_END]]
1079 // CHECK1:       cond.end:
1080 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1081 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1082 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1083 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
1084 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1085 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1086 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1087 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1088 // CHECK1:       omp.dispatch.body:
1089 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1090 // CHECK1:       omp.inner.for.cond:
1091 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]
1092 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
1093 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1094 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1095 // CHECK1:       omp.inner.for.body:
1096 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
1097 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1098 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1099 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]]
1100 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1101 // CHECK1:       omp.body.continue:
1102 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1103 // CHECK1:       omp.inner.for.inc:
1104 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
1105 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
1106 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
1107 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
1108 // CHECK1:       omp.inner.for.end:
1109 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1110 // CHECK1:       omp.dispatch.inc:
1111 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1112 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1113 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1114 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
1115 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1116 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1117 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
1118 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
1119 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1120 // CHECK1:       omp.dispatch.end:
1121 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
1122 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1123 // CHECK1-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1124 // CHECK1-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1125 // CHECK1:       .omp.final.then:
1126 // CHECK1-NEXT:    store i32 100, ptr [[I]], align 4
1127 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1128 // CHECK1:       .omp.final.done:
1129 // CHECK1-NEXT:    ret void
1130 //
1131 //
1132 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1133 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
1134 // CHECK1-NEXT:  entry:
1135 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1136 // CHECK1-NEXT:    ret void
1137 //
1138 //
1139 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
1140 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1141 // CHECK3-NEXT:  entry:
1142 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1143 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1144 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1145 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1146 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
1147 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
1148 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
1149 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1150 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1151 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1152 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1153 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1154 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1155 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1156 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1157 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1158 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1159 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1160 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 4
1161 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1162 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 4
1163 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1164 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1165 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1166 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
1167 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1168 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 4
1169 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1170 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
1171 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1172 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 4
1173 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1174 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 4
1175 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1176 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
1177 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1178 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
1179 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1180 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
1181 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1182 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
1183 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1184 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1185 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1186 // CHECK3-NEXT:    store i32 2, ptr [[TMP18]], align 4
1187 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1188 // CHECK3-NEXT:    store i32 4, ptr [[TMP19]], align 4
1189 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1190 // CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
1191 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1192 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
1193 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1194 // CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP22]], align 4
1195 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1196 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP23]], align 4
1197 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1198 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4
1199 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1200 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
1201 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1202 // CHECK3-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
1203 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1204 // CHECK3-NEXT:    store i64 0, ptr [[TMP27]], align 8
1205 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1206 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
1207 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1208 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
1209 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1210 // CHECK3-NEXT:    store i32 0, ptr [[TMP30]], align 4
1211 // CHECK3-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]])
1212 // CHECK3-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1213 // CHECK3-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1214 // CHECK3:       omp_offload.failed:
1215 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]]
1216 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1217 // CHECK3:       omp_offload.cont:
1218 // CHECK3-NEXT:    ret void
1219 //
1220 //
1221 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
1222 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
1223 // CHECK3-NEXT:  entry:
1224 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1225 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1226 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1227 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1228 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1229 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1230 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1231 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1232 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1233 // CHECK3-NEXT:    ret void
1234 //
1235 //
1236 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
1237 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
1238 // CHECK3-NEXT:  entry:
1239 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1240 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1241 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1242 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1243 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1244 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1245 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1246 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1247 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1248 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1249 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1250 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1251 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1252 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1253 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1254 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1255 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1256 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1257 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1258 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1259 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1260 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1261 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1262 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4
1263 // CHECK3-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ]
1264 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1265 // CHECK3-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1266 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1267 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1268 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1269 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1270 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1271 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1272 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
1273 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1274 // CHECK3:       cond.true:
1275 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1276 // CHECK3:       cond.false:
1277 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1278 // CHECK3-NEXT:    br label [[COND_END]]
1279 // CHECK3:       cond.end:
1280 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
1281 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1282 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1283 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
1284 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1285 // CHECK3:       omp.inner.for.cond:
1286 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
1287 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
1288 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1289 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1290 // CHECK3:       omp.inner.for.body:
1291 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
1292 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
1293 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
1294 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1295 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP9]]
1296 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1297 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
1298 // CHECK3-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
1299 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP9]]
1300 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1301 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]]
1302 // CHECK3-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]]
1303 // CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
1304 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP9]]
1305 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1306 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]]
1307 // CHECK3-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP9]]
1308 // CHECK3-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
1309 // CHECK3-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP9]]
1310 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
1311 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]]
1312 // CHECK3-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]]
1313 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1314 // CHECK3:       omp.body.continue:
1315 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1316 // CHECK3:       omp.inner.for.inc:
1317 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
1318 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
1319 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
1320 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1321 // CHECK3:       omp.inner.for.end:
1322 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1323 // CHECK3:       omp.loop.exit:
1324 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
1325 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1326 // CHECK3-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1327 // CHECK3-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1328 // CHECK3:       .omp.final.then:
1329 // CHECK3-NEXT:    store i32 32000001, ptr [[I]], align 4
1330 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1331 // CHECK3:       .omp.final.done:
1332 // CHECK3-NEXT:    ret void
1333 //
1334 //
1335 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1336 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1337 // CHECK3-NEXT:  entry:
1338 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1339 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1340 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1341 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1342 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
1343 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
1344 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
1345 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1346 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1347 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1348 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1349 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1350 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1351 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1352 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1353 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1354 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1355 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1356 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 4
1357 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1358 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 4
1359 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1360 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1361 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1362 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
1363 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1364 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 4
1365 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1366 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
1367 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1368 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 4
1369 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1370 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 4
1371 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1372 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
1373 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1374 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
1375 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1376 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
1377 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1378 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
1379 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1380 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1381 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1382 // CHECK3-NEXT:    store i32 2, ptr [[TMP18]], align 4
1383 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1384 // CHECK3-NEXT:    store i32 4, ptr [[TMP19]], align 4
1385 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1386 // CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
1387 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1388 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
1389 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1390 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP22]], align 4
1391 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1392 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4
1393 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1394 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4
1395 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1396 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
1397 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1398 // CHECK3-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
1399 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1400 // CHECK3-NEXT:    store i64 0, ptr [[TMP27]], align 8
1401 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1402 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
1403 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1404 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
1405 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1406 // CHECK3-NEXT:    store i32 0, ptr [[TMP30]], align 4
1407 // CHECK3-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]])
1408 // CHECK3-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1409 // CHECK3-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1410 // CHECK3:       omp_offload.failed:
1411 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
1412 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1413 // CHECK3:       omp_offload.cont:
1414 // CHECK3-NEXT:    ret void
1415 //
1416 //
1417 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
1418 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
1419 // CHECK3-NEXT:  entry:
1420 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1421 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1422 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1423 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1424 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1425 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1426 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1427 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1428 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1429 // CHECK3-NEXT:    ret void
1430 //
1431 //
1432 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
1433 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
1434 // CHECK3-NEXT:  entry:
1435 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1436 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1437 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1438 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1439 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1440 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1441 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1442 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1443 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1444 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1445 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1446 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1447 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1448 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1449 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1450 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1451 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1452 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1453 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1454 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1455 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1456 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1457 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1458 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1459 // CHECK3-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1460 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1461 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1462 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1463 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1464 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1465 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1466 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
1467 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1468 // CHECK3:       cond.true:
1469 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1470 // CHECK3:       cond.false:
1471 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1472 // CHECK3-NEXT:    br label [[COND_END]]
1473 // CHECK3:       cond.end:
1474 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1475 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1476 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1477 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1478 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1479 // CHECK3:       omp.inner.for.cond:
1480 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1481 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1482 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1483 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1484 // CHECK3:       omp.inner.for.body:
1485 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1486 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
1487 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1488 // CHECK3-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
1489 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4
1490 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1491 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]]
1492 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1493 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4
1494 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1495 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]]
1496 // CHECK3-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
1497 // CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
1498 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4
1499 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
1500 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]]
1501 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
1502 // CHECK3-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
1503 // CHECK3-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4
1504 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
1505 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]]
1506 // CHECK3-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
1507 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1508 // CHECK3:       omp.body.continue:
1509 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1510 // CHECK3:       omp.inner.for.inc:
1511 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1512 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
1513 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1514 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1515 // CHECK3:       omp.inner.for.end:
1516 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1517 // CHECK3:       omp.loop.exit:
1518 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1519 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1520 // CHECK3-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1521 // CHECK3-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1522 // CHECK3:       .omp.final.then:
1523 // CHECK3-NEXT:    store i32 32, ptr [[I]], align 4
1524 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1525 // CHECK3:       .omp.final.done:
1526 // CHECK3-NEXT:    ret void
1527 //
1528 //
1529 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
1530 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1531 // CHECK3-NEXT:  entry:
1532 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1533 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1534 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1535 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1536 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
1537 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
1538 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
1539 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1540 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1541 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1542 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1543 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1544 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1545 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1546 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1547 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1548 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1549 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1550 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 4
1551 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1552 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 4
1553 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1554 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1555 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1556 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
1557 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1558 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 4
1559 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1560 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
1561 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1562 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 4
1563 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1564 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 4
1565 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1566 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
1567 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1568 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
1569 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1570 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
1571 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1572 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
1573 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1574 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1575 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1576 // CHECK3-NEXT:    store i32 2, ptr [[TMP18]], align 4
1577 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1578 // CHECK3-NEXT:    store i32 4, ptr [[TMP19]], align 4
1579 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1580 // CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
1581 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1582 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
1583 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1584 // CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP22]], align 4
1585 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1586 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4
1587 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1588 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4
1589 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1590 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
1591 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1592 // CHECK3-NEXT:    store i64 16908289, ptr [[TMP26]], align 8
1593 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1594 // CHECK3-NEXT:    store i64 0, ptr [[TMP27]], align 8
1595 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1596 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
1597 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1598 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
1599 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1600 // CHECK3-NEXT:    store i32 0, ptr [[TMP30]], align 4
1601 // CHECK3-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]])
1602 // CHECK3-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1603 // CHECK3-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1604 // CHECK3:       omp_offload.failed:
1605 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
1606 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1607 // CHECK3:       omp_offload.cont:
1608 // CHECK3-NEXT:    ret void
1609 //
1610 //
1611 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
1612 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
1613 // CHECK3-NEXT:  entry:
1614 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1615 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1616 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1617 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1618 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1619 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1620 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1621 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1622 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1623 // CHECK3-NEXT:    ret void
1624 //
1625 //
1626 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
1627 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
1628 // CHECK3-NEXT:  entry:
1629 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1630 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1631 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1632 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1633 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1634 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1635 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1636 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1637 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1638 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1639 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1640 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1641 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1642 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1643 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1644 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1645 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1646 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1647 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1648 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1649 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1650 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1651 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1652 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1653 // CHECK3-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
1654 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1655 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1656 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1657 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1658 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
1659 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1660 // CHECK3:       omp.dispatch.cond:
1661 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1662 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
1663 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1664 // CHECK3:       cond.true:
1665 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1666 // CHECK3:       cond.false:
1667 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1668 // CHECK3-NEXT:    br label [[COND_END]]
1669 // CHECK3:       cond.end:
1670 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1671 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1672 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1673 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1674 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1675 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1676 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
1677 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1678 // CHECK3:       omp.dispatch.body:
1679 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1680 // CHECK3:       omp.inner.for.cond:
1681 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
1682 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
1683 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
1684 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1685 // CHECK3:       omp.inner.for.body:
1686 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
1687 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
1688 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
1689 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1690 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP18]]
1691 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1692 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]]
1693 // CHECK3-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]
1694 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP18]]
1695 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1696 // CHECK3-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]]
1697 // CHECK3-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP18]]
1698 // CHECK3-NEXT:    [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
1699 // CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP18]]
1700 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1701 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]]
1702 // CHECK3-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP18]]
1703 // CHECK3-NEXT:    [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
1704 // CHECK3-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP18]]
1705 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1706 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]]
1707 // CHECK3-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]]
1708 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1709 // CHECK3:       omp.body.continue:
1710 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1711 // CHECK3:       omp.inner.for.inc:
1712 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
1713 // CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP25]], 1
1714 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
1715 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
1716 // CHECK3:       omp.inner.for.end:
1717 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1718 // CHECK3:       omp.dispatch.inc:
1719 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1720 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1721 // CHECK3-NEXT:    [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
1722 // CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4
1723 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1724 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1725 // CHECK3-NEXT:    [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
1726 // CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4
1727 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1728 // CHECK3:       omp.dispatch.end:
1729 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1730 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1731 // CHECK3-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
1732 // CHECK3-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1733 // CHECK3:       .omp.final.then:
1734 // CHECK3-NEXT:    store i32 -2147483522, ptr [[I]], align 4
1735 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1736 // CHECK3:       .omp.final.done:
1737 // CHECK3-NEXT:    ret void
1738 //
1739 //
1740 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv
1741 // CHECK3-SAME: () #[[ATTR0]] {
1742 // CHECK3-NEXT:  entry:
1743 // CHECK3-NEXT:    [[A:%.*]] = alloca i8, align 1
1744 // CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 1
1745 // CHECK3-NEXT:    [[I_CASTED:%.*]] = alloca i32, align 4
1746 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1747 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
1748 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
1749 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
1750 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1751 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1752 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1753 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1754 // CHECK3-NEXT:    store i8 0, ptr [[A]], align 1
1755 // CHECK3-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 1
1756 // CHECK3-NEXT:    store i8 [[TMP0]], ptr [[I_CASTED]], align 1
1757 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[I_CASTED]], align 4
1758 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8, ptr [[A]], align 1
1759 // CHECK3-NEXT:    store i8 [[TMP2]], ptr [[A_CASTED]], align 1
1760 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
1761 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1762 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP4]], align 4
1763 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1764 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
1765 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1766 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1767 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1768 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP7]], align 4
1769 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1770 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
1771 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1772 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
1773 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1774 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1775 // CHECK3-NEXT:    [[TMP12:%.*]] = load i8, ptr [[A]], align 1
1776 // CHECK3-NEXT:    store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1
1777 // CHECK3-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1778 // CHECK3-NEXT:    [[CONV:%.*]] = sext i8 [[TMP13]] to i32
1779 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
1780 // CHECK3-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
1781 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
1782 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1783 // CHECK3-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1784 // CHECK3-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1785 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1786 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
1787 // CHECK3-NEXT:    [[TMP15:%.*]] = zext i32 [[ADD4]] to i64
1788 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1789 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
1790 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1791 // CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 4
1792 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1793 // CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP18]], align 4
1794 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1795 // CHECK3-NEXT:    store ptr [[TMP11]], ptr [[TMP19]], align 4
1796 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1797 // CHECK3-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP20]], align 4
1798 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1799 // CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP21]], align 4
1800 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1801 // CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 4
1802 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1803 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
1804 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1805 // CHECK3-NEXT:    store i64 [[TMP15]], ptr [[TMP24]], align 8
1806 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1807 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8
1808 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1809 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
1810 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1811 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
1812 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1813 // CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 4
1814 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]])
1815 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1816 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1817 // CHECK3:       omp_offload.failed:
1818 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
1819 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1820 // CHECK3:       omp_offload.cont:
1821 // CHECK3-NEXT:    ret void
1822 //
1823 //
1824 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
1825 // CHECK3-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
1826 // CHECK3-NEXT:  entry:
1827 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca i32, align 4
1828 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1829 // CHECK3-NEXT:    store i32 [[I]], ptr [[I_ADDR]], align 4
1830 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1831 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
1832 // CHECK3-NEXT:    ret void
1833 //
1834 //
1835 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
1836 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
1837 // CHECK3-NEXT:  entry:
1838 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1839 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1840 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 4
1841 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1842 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1843 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1844 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1845 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1846 // CHECK3-NEXT:    [[I4:%.*]] = alloca i8, align 1
1847 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1848 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1849 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1850 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1851 // CHECK3-NEXT:    [[I6:%.*]] = alloca i8, align 1
1852 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1853 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1854 // CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 4
1855 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1856 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4
1857 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1858 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
1859 // CHECK3-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
1860 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1861 // CHECK3-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
1862 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
1863 // CHECK3-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
1864 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
1865 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1866 // CHECK3-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1867 // CHECK3-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1868 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1869 // CHECK3-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
1870 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1871 // CHECK3-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
1872 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
1873 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1874 // CHECK3:       omp.precond.then:
1875 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1876 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1877 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
1878 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1879 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1880 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1881 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1882 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1883 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1884 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1885 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
1886 // CHECK3-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1887 // CHECK3:       cond.true:
1888 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1889 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1890 // CHECK3:       cond.false:
1891 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1892 // CHECK3-NEXT:    br label [[COND_END]]
1893 // CHECK3:       cond.end:
1894 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1895 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1896 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1897 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
1898 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1899 // CHECK3:       omp.inner.for.cond:
1900 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
1901 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
1902 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1903 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1904 // CHECK3:       omp.inner.for.body:
1905 // CHECK3-NEXT:    [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]]
1906 // CHECK3-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
1907 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
1908 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1909 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
1910 // CHECK3-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
1911 // CHECK3-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP21]]
1912 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1913 // CHECK3:       omp.body.continue:
1914 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1915 // CHECK3:       omp.inner.for.inc:
1916 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
1917 // CHECK3-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
1918 // CHECK3-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
1919 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
1920 // CHECK3:       omp.inner.for.end:
1921 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1922 // CHECK3:       omp.loop.exit:
1923 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1924 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1925 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
1926 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1927 // CHECK3-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1928 // CHECK3-NEXT:    br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1929 // CHECK3:       .omp.final.then:
1930 // CHECK3-NEXT:    [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1931 // CHECK3-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
1932 // CHECK3-NEXT:    [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1933 // CHECK3-NEXT:    [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
1934 // CHECK3-NEXT:    [[SUB15:%.*]] = sub i32 10, [[CONV14]]
1935 // CHECK3-NEXT:    [[SUB16:%.*]] = sub i32 [[SUB15]], 1
1936 // CHECK3-NEXT:    [[ADD17:%.*]] = add i32 [[SUB16]], 1
1937 // CHECK3-NEXT:    [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
1938 // CHECK3-NEXT:    [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
1939 // CHECK3-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
1940 // CHECK3-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
1941 // CHECK3-NEXT:    store i8 [[CONV21]], ptr [[TMP0]], align 1
1942 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1943 // CHECK3:       .omp.final.done:
1944 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
1945 // CHECK3:       omp.precond.end:
1946 // CHECK3-NEXT:    ret void
1947 //
1948 //
1949 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv
1950 // CHECK3-SAME: () #[[ATTR0]] {
1951 // CHECK3-NEXT:  entry:
1952 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
1953 // CHECK3-NEXT:    ret i32 [[CALL]]
1954 //
1955 //
1956 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
1957 // CHECK3-SAME: () #[[ATTR0]] comdat {
1958 // CHECK3-NEXT:  entry:
1959 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
1960 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
1961 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
1962 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
1963 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
1964 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1965 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1966 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
1967 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA]], align 2
1968 // CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
1969 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
1970 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1971 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP2]], align 4
1972 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1973 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP3]], align 4
1974 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1975 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
1976 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1977 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1978 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1979 // CHECK3-NEXT:    store i32 2, ptr [[TMP7]], align 4
1980 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1981 // CHECK3-NEXT:    store i32 1, ptr [[TMP8]], align 4
1982 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1983 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 4
1984 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1985 // CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 4
1986 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1987 // CHECK3-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP11]], align 4
1988 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1989 // CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP12]], align 4
1990 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1991 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
1992 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1993 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4
1994 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1995 // CHECK3-NEXT:    store i64 100, ptr [[TMP15]], align 8
1996 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1997 // CHECK3-NEXT:    store i64 0, ptr [[TMP16]], align 8
1998 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1999 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
2000 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2001 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
2002 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2003 // CHECK3-NEXT:    store i32 0, ptr [[TMP19]], align 4
2004 // CHECK3-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]])
2005 // CHECK3-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2006 // CHECK3-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2007 // CHECK3:       omp_offload.failed:
2008 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
2009 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2010 // CHECK3:       omp_offload.cont:
2011 // CHECK3-NEXT:    ret i32 0
2012 //
2013 //
2014 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
2015 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] {
2016 // CHECK3-NEXT:  entry:
2017 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2018 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2019 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
2020 // CHECK3-NEXT:    ret void
2021 //
2022 //
2023 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
2024 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
2025 // CHECK3-NEXT:  entry:
2026 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2027 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2028 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
2029 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2030 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2031 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2032 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2033 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2034 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2035 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2036 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2037 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2038 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
2039 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
2040 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2041 // CHECK3-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
2042 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2043 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2044 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
2045 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2046 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2047 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2048 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
2049 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2050 // CHECK3:       omp.dispatch.cond:
2051 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2052 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2053 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2054 // CHECK3:       cond.true:
2055 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2056 // CHECK3:       cond.false:
2057 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2058 // CHECK3-NEXT:    br label [[COND_END]]
2059 // CHECK3:       cond.end:
2060 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2061 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2062 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2063 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2064 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2065 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2066 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2067 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2068 // CHECK3:       omp.dispatch.body:
2069 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2070 // CHECK3:       omp.inner.for.cond:
2071 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
2072 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
2073 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2074 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2075 // CHECK3:       omp.inner.for.body:
2076 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
2077 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
2078 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2079 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
2080 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2081 // CHECK3:       omp.body.continue:
2082 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2083 // CHECK3:       omp.inner.for.inc:
2084 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
2085 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
2086 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
2087 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
2088 // CHECK3:       omp.inner.for.end:
2089 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2090 // CHECK3:       omp.dispatch.inc:
2091 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2092 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2093 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
2094 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
2095 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2096 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2097 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
2098 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
2099 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
2100 // CHECK3:       omp.dispatch.end:
2101 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
2102 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2103 // CHECK3-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
2104 // CHECK3-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2105 // CHECK3:       .omp.final.then:
2106 // CHECK3-NEXT:    store i32 100, ptr [[I]], align 4
2107 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2108 // CHECK3:       .omp.final.done:
2109 // CHECK3-NEXT:    ret void
2110 //
2111 //
2112 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2113 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
2114 // CHECK3-NEXT:  entry:
2115 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
2116 // CHECK3-NEXT:    ret void
2117 //
2118 //
2119 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
2120 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2121 // CHECK5-NEXT:  entry:
2122 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2123 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2124 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2125 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2126 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
2127 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
2128 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
2129 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2130 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2131 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2132 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2133 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2134 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2135 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2136 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2137 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2138 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2139 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2140 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
2141 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2142 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 8
2143 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2144 // CHECK5-NEXT:    store ptr null, ptr [[TMP6]], align 8
2145 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2146 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
2147 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2148 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
2149 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2150 // CHECK5-NEXT:    store ptr null, ptr [[TMP9]], align 8
2151 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2152 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 8
2153 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2154 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 8
2155 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2156 // CHECK5-NEXT:    store ptr null, ptr [[TMP12]], align 8
2157 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2158 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
2159 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2160 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
2161 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2162 // CHECK5-NEXT:    store ptr null, ptr [[TMP15]], align 8
2163 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2164 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2165 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2166 // CHECK5-NEXT:    store i32 2, ptr [[TMP18]], align 4
2167 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2168 // CHECK5-NEXT:    store i32 4, ptr [[TMP19]], align 4
2169 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2170 // CHECK5-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
2171 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2172 // CHECK5-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
2173 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2174 // CHECK5-NEXT:    store ptr @.offload_sizes, ptr [[TMP22]], align 8
2175 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2176 // CHECK5-NEXT:    store ptr @.offload_maptypes, ptr [[TMP23]], align 8
2177 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2178 // CHECK5-NEXT:    store ptr null, ptr [[TMP24]], align 8
2179 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2180 // CHECK5-NEXT:    store ptr null, ptr [[TMP25]], align 8
2181 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2182 // CHECK5-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
2183 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2184 // CHECK5-NEXT:    store i64 0, ptr [[TMP27]], align 8
2185 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2186 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
2187 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2188 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
2189 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2190 // CHECK5-NEXT:    store i32 0, ptr [[TMP30]], align 4
2191 // CHECK5-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]])
2192 // CHECK5-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2193 // CHECK5-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2194 // CHECK5:       omp_offload.failed:
2195 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]]
2196 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2197 // CHECK5:       omp_offload.cont:
2198 // CHECK5-NEXT:    ret void
2199 //
2200 //
2201 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
2202 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
2203 // CHECK5-NEXT:  entry:
2204 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2205 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2206 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2207 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2208 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2209 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2210 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2211 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2212 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
2213 // CHECK5-NEXT:    ret void
2214 //
2215 //
2216 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
2217 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2218 // CHECK5-NEXT:  entry:
2219 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2220 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2221 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2222 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2223 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2224 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2225 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2226 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2227 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2228 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2229 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2230 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2231 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2232 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2233 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2234 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2235 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2236 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2237 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2238 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2239 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2240 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2241 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2242 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8
2243 // CHECK5-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ]
2244 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2245 // CHECK5-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
2246 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2247 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2248 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2249 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2250 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2251 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2252 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
2253 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2254 // CHECK5:       cond.true:
2255 // CHECK5-NEXT:    br label [[COND_END:%.*]]
2256 // CHECK5:       cond.false:
2257 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2258 // CHECK5-NEXT:    br label [[COND_END]]
2259 // CHECK5:       cond.end:
2260 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
2261 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2262 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2263 // CHECK5-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
2264 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2265 // CHECK5:       omp.inner.for.cond:
2266 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
2267 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
2268 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
2269 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2270 // CHECK5:       omp.inner.for.body:
2271 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
2272 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
2273 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
2274 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
2275 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
2276 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
2277 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
2278 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
2279 // CHECK5-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
2280 // CHECK5-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
2281 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
2282 // CHECK5-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
2283 // CHECK5-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]]
2284 // CHECK5-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP8]]
2285 // CHECK5-NEXT:    [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
2286 // CHECK5-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
2287 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
2288 // CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
2289 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]]
2290 // CHECK5-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
2291 // CHECK5-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
2292 // CHECK5-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
2293 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
2294 // CHECK5-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
2295 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]]
2296 // CHECK5-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]]
2297 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2298 // CHECK5:       omp.body.continue:
2299 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2300 // CHECK5:       omp.inner.for.inc:
2301 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
2302 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
2303 // CHECK5-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
2304 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2305 // CHECK5:       omp.inner.for.end:
2306 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2307 // CHECK5:       omp.loop.exit:
2308 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
2309 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2310 // CHECK5-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2311 // CHECK5-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2312 // CHECK5:       .omp.final.then:
2313 // CHECK5-NEXT:    store i32 32000001, ptr [[I]], align 4
2314 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2315 // CHECK5:       .omp.final.done:
2316 // CHECK5-NEXT:    ret void
2317 //
2318 //
2319 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
2320 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2321 // CHECK5-NEXT:  entry:
2322 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2323 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2324 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2325 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2326 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
2327 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
2328 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
2329 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2330 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2331 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2332 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2333 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2334 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2335 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2336 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2337 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2338 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2339 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2340 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
2341 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2342 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 8
2343 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2344 // CHECK5-NEXT:    store ptr null, ptr [[TMP6]], align 8
2345 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2346 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
2347 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2348 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
2349 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2350 // CHECK5-NEXT:    store ptr null, ptr [[TMP9]], align 8
2351 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2352 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 8
2353 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2354 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 8
2355 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2356 // CHECK5-NEXT:    store ptr null, ptr [[TMP12]], align 8
2357 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2358 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
2359 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2360 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
2361 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2362 // CHECK5-NEXT:    store ptr null, ptr [[TMP15]], align 8
2363 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2364 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2365 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2366 // CHECK5-NEXT:    store i32 2, ptr [[TMP18]], align 4
2367 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2368 // CHECK5-NEXT:    store i32 4, ptr [[TMP19]], align 4
2369 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2370 // CHECK5-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
2371 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2372 // CHECK5-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
2373 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2374 // CHECK5-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP22]], align 8
2375 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2376 // CHECK5-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8
2377 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2378 // CHECK5-NEXT:    store ptr null, ptr [[TMP24]], align 8
2379 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2380 // CHECK5-NEXT:    store ptr null, ptr [[TMP25]], align 8
2381 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2382 // CHECK5-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
2383 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2384 // CHECK5-NEXT:    store i64 0, ptr [[TMP27]], align 8
2385 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2386 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
2387 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2388 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
2389 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2390 // CHECK5-NEXT:    store i32 0, ptr [[TMP30]], align 4
2391 // CHECK5-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]])
2392 // CHECK5-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2393 // CHECK5-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2394 // CHECK5:       omp_offload.failed:
2395 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
2396 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2397 // CHECK5:       omp_offload.cont:
2398 // CHECK5-NEXT:    ret void
2399 //
2400 //
2401 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
2402 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
2403 // CHECK5-NEXT:  entry:
2404 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2405 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2406 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2407 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2408 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2409 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2410 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2411 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2412 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
2413 // CHECK5-NEXT:    ret void
2414 //
2415 //
2416 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
2417 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2418 // CHECK5-NEXT:  entry:
2419 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2420 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2421 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2422 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2423 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2424 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2425 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2426 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2427 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2428 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2429 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2430 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2431 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2432 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2433 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2434 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2435 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2436 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2437 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2438 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2439 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2440 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2441 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2442 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2443 // CHECK5-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
2444 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2445 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2446 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2447 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2448 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2449 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2450 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
2451 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2452 // CHECK5:       cond.true:
2453 // CHECK5-NEXT:    br label [[COND_END:%.*]]
2454 // CHECK5:       cond.false:
2455 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2456 // CHECK5-NEXT:    br label [[COND_END]]
2457 // CHECK5:       cond.end:
2458 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2459 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2460 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2461 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
2462 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2463 // CHECK5:       omp.inner.for.cond:
2464 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2465 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2466 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2467 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2468 // CHECK5:       omp.inner.for.body:
2469 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2470 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
2471 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
2472 // CHECK5-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
2473 // CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal !15
2474 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
2475 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
2476 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
2477 // CHECK5-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2478 // CHECK5-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
2479 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
2480 // CHECK5-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
2481 // CHECK5-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
2482 // CHECK5-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
2483 // CHECK5-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
2484 // CHECK5-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
2485 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
2486 // CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
2487 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
2488 // CHECK5-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
2489 // CHECK5-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
2490 // CHECK5-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal !15
2491 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
2492 // CHECK5-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
2493 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
2494 // CHECK5-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
2495 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2496 // CHECK5:       omp.body.continue:
2497 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2498 // CHECK5:       omp.inner.for.inc:
2499 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2500 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
2501 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2502 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
2503 // CHECK5:       omp.inner.for.end:
2504 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2505 // CHECK5:       omp.loop.exit:
2506 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
2507 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2508 // CHECK5-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2509 // CHECK5-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2510 // CHECK5:       .omp.final.then:
2511 // CHECK5-NEXT:    store i32 32, ptr [[I]], align 4
2512 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2513 // CHECK5:       .omp.final.done:
2514 // CHECK5-NEXT:    ret void
2515 //
2516 //
2517 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
2518 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2519 // CHECK5-NEXT:  entry:
2520 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2521 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2522 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2523 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2524 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
2525 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
2526 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
2527 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2528 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2529 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2530 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2531 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2532 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2533 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2534 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2535 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2536 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2537 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2538 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
2539 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2540 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 8
2541 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2542 // CHECK5-NEXT:    store ptr null, ptr [[TMP6]], align 8
2543 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2544 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
2545 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2546 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
2547 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2548 // CHECK5-NEXT:    store ptr null, ptr [[TMP9]], align 8
2549 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2550 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 8
2551 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2552 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 8
2553 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2554 // CHECK5-NEXT:    store ptr null, ptr [[TMP12]], align 8
2555 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2556 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8
2557 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2558 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8
2559 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2560 // CHECK5-NEXT:    store ptr null, ptr [[TMP15]], align 8
2561 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2562 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2563 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2564 // CHECK5-NEXT:    store i32 2, ptr [[TMP18]], align 4
2565 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2566 // CHECK5-NEXT:    store i32 4, ptr [[TMP19]], align 4
2567 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2568 // CHECK5-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8
2569 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2570 // CHECK5-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
2571 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2572 // CHECK5-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP22]], align 8
2573 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2574 // CHECK5-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8
2575 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2576 // CHECK5-NEXT:    store ptr null, ptr [[TMP24]], align 8
2577 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2578 // CHECK5-NEXT:    store ptr null, ptr [[TMP25]], align 8
2579 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2580 // CHECK5-NEXT:    store i64 16908289, ptr [[TMP26]], align 8
2581 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2582 // CHECK5-NEXT:    store i64 0, ptr [[TMP27]], align 8
2583 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2584 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
2585 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2586 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
2587 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2588 // CHECK5-NEXT:    store i32 0, ptr [[TMP30]], align 4
2589 // CHECK5-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]])
2590 // CHECK5-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2591 // CHECK5-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2592 // CHECK5:       omp_offload.failed:
2593 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
2594 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2595 // CHECK5:       omp_offload.cont:
2596 // CHECK5-NEXT:    ret void
2597 //
2598 //
2599 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
2600 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
2601 // CHECK5-NEXT:  entry:
2602 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2603 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2604 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2605 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2606 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2607 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2608 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2609 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2610 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
2611 // CHECK5-NEXT:    ret void
2612 //
2613 //
2614 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
2615 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2616 // CHECK5-NEXT:  entry:
2617 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2618 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2619 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2620 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2621 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2622 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2623 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2624 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2625 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2626 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2627 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2628 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2629 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2630 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2631 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2632 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2633 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2634 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2635 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2636 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2637 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2638 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2639 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2640 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2641 // CHECK5-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
2642 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2643 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2644 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2645 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2646 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
2647 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2648 // CHECK5:       omp.dispatch.cond:
2649 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2650 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
2651 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2652 // CHECK5:       cond.true:
2653 // CHECK5-NEXT:    br label [[COND_END:%.*]]
2654 // CHECK5:       cond.false:
2655 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2656 // CHECK5-NEXT:    br label [[COND_END]]
2657 // CHECK5:       cond.end:
2658 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2659 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2660 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2661 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
2662 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2663 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2664 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
2665 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2666 // CHECK5:       omp.dispatch.body:
2667 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2668 // CHECK5:       omp.inner.for.cond:
2669 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
2670 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
2671 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
2672 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2673 // CHECK5:       omp.inner.for.body:
2674 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2675 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
2676 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
2677 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2678 // CHECK5-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP18]]
2679 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2680 // CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
2681 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
2682 // CHECK5-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]
2683 // CHECK5-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP18]]
2684 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2685 // CHECK5-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
2686 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
2687 // CHECK5-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP18]]
2688 // CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
2689 // CHECK5-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP18]]
2690 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2691 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
2692 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
2693 // CHECK5-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]]
2694 // CHECK5-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
2695 // CHECK5-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP18]]
2696 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2697 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
2698 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
2699 // CHECK5-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP18]]
2700 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2701 // CHECK5:       omp.body.continue:
2702 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2703 // CHECK5:       omp.inner.for.inc:
2704 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2705 // CHECK5-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
2706 // CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2707 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2708 // CHECK5:       omp.inner.for.end:
2709 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2710 // CHECK5:       omp.dispatch.inc:
2711 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2712 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2713 // CHECK5-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
2714 // CHECK5-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
2715 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2716 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2717 // CHECK5-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
2718 // CHECK5-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
2719 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]]
2720 // CHECK5:       omp.dispatch.end:
2721 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
2722 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2723 // CHECK5-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
2724 // CHECK5-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2725 // CHECK5:       .omp.final.then:
2726 // CHECK5-NEXT:    store i32 -2147483522, ptr [[I]], align 4
2727 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2728 // CHECK5:       .omp.final.done:
2729 // CHECK5-NEXT:    ret void
2730 //
2731 //
2732 // CHECK5-LABEL: define {{[^@]+}}@_Z12test_precondv
2733 // CHECK5-SAME: () #[[ATTR0]] {
2734 // CHECK5-NEXT:  entry:
2735 // CHECK5-NEXT:    [[A:%.*]] = alloca i8, align 1
2736 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
2737 // CHECK5-NEXT:    [[I_CASTED:%.*]] = alloca i64, align 8
2738 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2739 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
2740 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
2741 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
2742 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2743 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2744 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2745 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2746 // CHECK5-NEXT:    store i8 0, ptr [[A]], align 1
2747 // CHECK5-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 1
2748 // CHECK5-NEXT:    store i8 [[TMP0]], ptr [[I_CASTED]], align 1
2749 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[I_CASTED]], align 8
2750 // CHECK5-NEXT:    [[TMP2:%.*]] = load i8, ptr [[A]], align 1
2751 // CHECK5-NEXT:    store i8 [[TMP2]], ptr [[A_CASTED]], align 1
2752 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8
2753 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2754 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP4]], align 8
2755 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2756 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
2757 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2758 // CHECK5-NEXT:    store ptr null, ptr [[TMP6]], align 8
2759 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2760 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[TMP7]], align 8
2761 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2762 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
2763 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2764 // CHECK5-NEXT:    store ptr null, ptr [[TMP9]], align 8
2765 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2766 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2767 // CHECK5-NEXT:    [[TMP12:%.*]] = load i8, ptr [[A]], align 1
2768 // CHECK5-NEXT:    store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1
2769 // CHECK5-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2770 // CHECK5-NEXT:    [[CONV:%.*]] = sext i8 [[TMP13]] to i32
2771 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
2772 // CHECK5-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
2773 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
2774 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2775 // CHECK5-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
2776 // CHECK5-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2777 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2778 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
2779 // CHECK5-NEXT:    [[TMP15:%.*]] = zext i32 [[ADD4]] to i64
2780 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2781 // CHECK5-NEXT:    store i32 2, ptr [[TMP16]], align 4
2782 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2783 // CHECK5-NEXT:    store i32 2, ptr [[TMP17]], align 4
2784 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2785 // CHECK5-NEXT:    store ptr [[TMP10]], ptr [[TMP18]], align 8
2786 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2787 // CHECK5-NEXT:    store ptr [[TMP11]], ptr [[TMP19]], align 8
2788 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2789 // CHECK5-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP20]], align 8
2790 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2791 // CHECK5-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP21]], align 8
2792 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2793 // CHECK5-NEXT:    store ptr null, ptr [[TMP22]], align 8
2794 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2795 // CHECK5-NEXT:    store ptr null, ptr [[TMP23]], align 8
2796 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2797 // CHECK5-NEXT:    store i64 [[TMP15]], ptr [[TMP24]], align 8
2798 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2799 // CHECK5-NEXT:    store i64 0, ptr [[TMP25]], align 8
2800 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2801 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
2802 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2803 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
2804 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2805 // CHECK5-NEXT:    store i32 0, ptr [[TMP28]], align 4
2806 // CHECK5-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]])
2807 // CHECK5-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2808 // CHECK5-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2809 // CHECK5:       omp_offload.failed:
2810 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
2811 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2812 // CHECK5:       omp_offload.cont:
2813 // CHECK5-NEXT:    ret void
2814 //
2815 //
2816 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
2817 // CHECK5-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
2818 // CHECK5-NEXT:  entry:
2819 // CHECK5-NEXT:    [[I_ADDR:%.*]] = alloca i64, align 8
2820 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2821 // CHECK5-NEXT:    store i64 [[I]], ptr [[I_ADDR]], align 8
2822 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2823 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
2824 // CHECK5-NEXT:    ret void
2825 //
2826 //
2827 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
2828 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
2829 // CHECK5-NEXT:  entry:
2830 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2831 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2832 // CHECK5-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
2833 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2834 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2835 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2836 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2837 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2838 // CHECK5-NEXT:    [[I4:%.*]] = alloca i8, align 1
2839 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2840 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2841 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2842 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2843 // CHECK5-NEXT:    [[I6:%.*]] = alloca i8, align 1
2844 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2845 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2846 // CHECK5-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
2847 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2848 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
2849 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2850 // CHECK5-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
2851 // CHECK5-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
2852 // CHECK5-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2853 // CHECK5-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
2854 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
2855 // CHECK5-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
2856 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
2857 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2858 // CHECK5-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
2859 // CHECK5-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2860 // CHECK5-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2861 // CHECK5-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
2862 // CHECK5-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2863 // CHECK5-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
2864 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
2865 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2866 // CHECK5:       omp.precond.then:
2867 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2868 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2869 // CHECK5-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
2870 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2871 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2872 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2873 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2874 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2875 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2876 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2877 // CHECK5-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
2878 // CHECK5-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2879 // CHECK5:       cond.true:
2880 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2881 // CHECK5-NEXT:    br label [[COND_END:%.*]]
2882 // CHECK5:       cond.false:
2883 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2884 // CHECK5-NEXT:    br label [[COND_END]]
2885 // CHECK5:       cond.end:
2886 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2887 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2888 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2889 // CHECK5-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
2890 // CHECK5-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1
2891 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
2892 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2893 // CHECK5:       omp_if.then:
2894 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2895 // CHECK5:       omp.inner.for.cond:
2896 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
2897 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
2898 // CHECK5-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2899 // CHECK5-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2900 // CHECK5:       omp.inner.for.body:
2901 // CHECK5-NEXT:    [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]]
2902 // CHECK5-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
2903 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
2904 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2905 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
2906 // CHECK5-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
2907 // CHECK5-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !15, !llvm.access.group [[ACC_GRP21]]
2908 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2909 // CHECK5:       omp.body.continue:
2910 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2911 // CHECK5:       omp.inner.for.inc:
2912 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
2913 // CHECK5-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
2914 // CHECK5-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
2915 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
2916 // CHECK5:       omp.inner.for.end:
2917 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
2918 // CHECK5:       omp_if.else:
2919 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND13:%.*]]
2920 // CHECK5:       omp.inner.for.cond13:
2921 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2922 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2923 // CHECK5-NEXT:    [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
2924 // CHECK5-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
2925 // CHECK5:       omp.inner.for.body15:
2926 // CHECK5-NEXT:    [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2927 // CHECK5-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
2928 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2929 // CHECK5-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
2930 // CHECK5-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
2931 // CHECK5-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
2932 // CHECK5-NEXT:    store i8 [[CONV19]], ptr [[I6]], align 1
2933 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE20:%.*]]
2934 // CHECK5:       omp.body.continue20:
2935 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC21:%.*]]
2936 // CHECK5:       omp.inner.for.inc21:
2937 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2938 // CHECK5-NEXT:    [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
2939 // CHECK5-NEXT:    store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4
2940 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]]
2941 // CHECK5:       omp.inner.for.end23:
2942 // CHECK5-NEXT:    br label [[OMP_IF_END]]
2943 // CHECK5:       omp_if.end:
2944 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2945 // CHECK5:       omp.loop.exit:
2946 // CHECK5-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2947 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
2948 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
2949 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2950 // CHECK5-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2951 // CHECK5-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2952 // CHECK5:       .omp.final.then:
2953 // CHECK5-NEXT:    [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2954 // CHECK5-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
2955 // CHECK5-NEXT:    [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2956 // CHECK5-NEXT:    [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
2957 // CHECK5-NEXT:    [[SUB26:%.*]] = sub i32 10, [[CONV25]]
2958 // CHECK5-NEXT:    [[SUB27:%.*]] = sub i32 [[SUB26]], 1
2959 // CHECK5-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
2960 // CHECK5-NEXT:    [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
2961 // CHECK5-NEXT:    [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
2962 // CHECK5-NEXT:    [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
2963 // CHECK5-NEXT:    [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
2964 // CHECK5-NEXT:    store i8 [[CONV32]], ptr [[TMP0]], align 1
2965 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2966 // CHECK5:       .omp.final.done:
2967 // CHECK5-NEXT:    br label [[OMP_PRECOND_END]]
2968 // CHECK5:       omp.precond.end:
2969 // CHECK5-NEXT:    ret void
2970 //
2971 //
2972 // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv
2973 // CHECK5-SAME: () #[[ATTR0]] {
2974 // CHECK5-NEXT:  entry:
2975 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
2976 // CHECK5-NEXT:    ret i32 [[CALL]]
2977 //
2978 //
2979 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
2980 // CHECK5-SAME: () #[[ATTR0]] comdat {
2981 // CHECK5-NEXT:  entry:
2982 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
2983 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2984 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
2985 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
2986 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
2987 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2988 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2989 // CHECK5-NEXT:    store i16 0, ptr [[AA]], align 2
2990 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA]], align 2
2991 // CHECK5-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2992 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
2993 // CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2994 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP2]], align 8
2995 // CHECK5-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2996 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP3]], align 8
2997 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2998 // CHECK5-NEXT:    store ptr null, ptr [[TMP4]], align 8
2999 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3000 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3001 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3002 // CHECK5-NEXT:    store i32 2, ptr [[TMP7]], align 4
3003 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3004 // CHECK5-NEXT:    store i32 1, ptr [[TMP8]], align 4
3005 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3006 // CHECK5-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 8
3007 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3008 // CHECK5-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 8
3009 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3010 // CHECK5-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP11]], align 8
3011 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3012 // CHECK5-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP12]], align 8
3013 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3014 // CHECK5-NEXT:    store ptr null, ptr [[TMP13]], align 8
3015 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3016 // CHECK5-NEXT:    store ptr null, ptr [[TMP14]], align 8
3017 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3018 // CHECK5-NEXT:    store i64 100, ptr [[TMP15]], align 8
3019 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3020 // CHECK5-NEXT:    store i64 0, ptr [[TMP16]], align 8
3021 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3022 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
3023 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3024 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
3025 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3026 // CHECK5-NEXT:    store i32 0, ptr [[TMP19]], align 4
3027 // CHECK5-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]])
3028 // CHECK5-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
3029 // CHECK5-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3030 // CHECK5:       omp_offload.failed:
3031 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
3032 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3033 // CHECK5:       omp_offload.cont:
3034 // CHECK5-NEXT:    ret i32 0
3035 //
3036 //
3037 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
3038 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] {
3039 // CHECK5-NEXT:  entry:
3040 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3041 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3042 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
3043 // CHECK5-NEXT:    ret void
3044 //
3045 //
3046 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
3047 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
3048 // CHECK5-NEXT:  entry:
3049 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3050 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3051 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
3052 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3053 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3054 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3055 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3056 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3057 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3058 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
3059 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3060 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3061 // CHECK5-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
3062 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
3063 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3064 // CHECK5-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
3065 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3066 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3067 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
3068 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3069 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3070 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
3071 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
3072 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
3073 // CHECK5:       omp.dispatch.cond:
3074 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3075 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
3076 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3077 // CHECK5:       cond.true:
3078 // CHECK5-NEXT:    br label [[COND_END:%.*]]
3079 // CHECK5:       cond.false:
3080 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3081 // CHECK5-NEXT:    br label [[COND_END]]
3082 // CHECK5:       cond.end:
3083 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3084 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3085 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3086 // CHECK5-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
3087 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3088 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3089 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3090 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3091 // CHECK5:       omp.dispatch.body:
3092 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3093 // CHECK5:       omp.inner.for.cond:
3094 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]]
3095 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]]
3096 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3097 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3098 // CHECK5:       omp.inner.for.body:
3099 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
3100 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3101 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3102 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]
3103 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3104 // CHECK5:       omp.body.continue:
3105 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3106 // CHECK5:       omp.inner.for.inc:
3107 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
3108 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
3109 // CHECK5-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
3110 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
3111 // CHECK5:       omp.inner.for.end:
3112 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3113 // CHECK5:       omp.dispatch.inc:
3114 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3115 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3116 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
3117 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
3118 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3119 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3120 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
3121 // CHECK5-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
3122 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]]
3123 // CHECK5:       omp.dispatch.end:
3124 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
3125 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3126 // CHECK5-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
3127 // CHECK5-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3128 // CHECK5:       .omp.final.then:
3129 // CHECK5-NEXT:    store i32 100, ptr [[I]], align 4
3130 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3131 // CHECK5:       .omp.final.done:
3132 // CHECK5-NEXT:    ret void
3133 //
3134 //
3135 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3136 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] {
3137 // CHECK5-NEXT:  entry:
3138 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
3139 // CHECK5-NEXT:    ret void
3140 //
3141 //
3142 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
3143 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
3144 // CHECK7-NEXT:  entry:
3145 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3146 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3147 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3148 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3149 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
3150 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
3151 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
3152 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3153 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3154 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3155 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3156 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3157 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3158 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3159 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3160 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3161 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3162 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3163 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 4
3164 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3165 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 4
3166 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3167 // CHECK7-NEXT:    store ptr null, ptr [[TMP6]], align 4
3168 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3169 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
3170 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3171 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 4
3172 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3173 // CHECK7-NEXT:    store ptr null, ptr [[TMP9]], align 4
3174 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3175 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 4
3176 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3177 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 4
3178 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3179 // CHECK7-NEXT:    store ptr null, ptr [[TMP12]], align 4
3180 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3181 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
3182 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3183 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
3184 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3185 // CHECK7-NEXT:    store ptr null, ptr [[TMP15]], align 4
3186 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3187 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3188 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3189 // CHECK7-NEXT:    store i32 2, ptr [[TMP18]], align 4
3190 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3191 // CHECK7-NEXT:    store i32 4, ptr [[TMP19]], align 4
3192 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3193 // CHECK7-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
3194 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3195 // CHECK7-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
3196 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3197 // CHECK7-NEXT:    store ptr @.offload_sizes, ptr [[TMP22]], align 4
3198 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3199 // CHECK7-NEXT:    store ptr @.offload_maptypes, ptr [[TMP23]], align 4
3200 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3201 // CHECK7-NEXT:    store ptr null, ptr [[TMP24]], align 4
3202 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3203 // CHECK7-NEXT:    store ptr null, ptr [[TMP25]], align 4
3204 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3205 // CHECK7-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
3206 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3207 // CHECK7-NEXT:    store i64 0, ptr [[TMP27]], align 8
3208 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3209 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
3210 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3211 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
3212 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3213 // CHECK7-NEXT:    store i32 0, ptr [[TMP30]], align 4
3214 // CHECK7-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]])
3215 // CHECK7-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3216 // CHECK7-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3217 // CHECK7:       omp_offload.failed:
3218 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]]
3219 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3220 // CHECK7:       omp_offload.cont:
3221 // CHECK7-NEXT:    ret void
3222 //
3223 //
3224 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
3225 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
3226 // CHECK7-NEXT:  entry:
3227 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3228 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3229 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3230 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3231 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3232 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3233 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3234 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3235 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
3236 // CHECK7-NEXT:    ret void
3237 //
3238 //
3239 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
3240 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3241 // CHECK7-NEXT:  entry:
3242 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3243 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3244 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3245 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3246 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3247 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3248 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3249 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3250 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3251 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3252 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3253 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3254 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
3255 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3256 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3257 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3258 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3259 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3260 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3261 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3262 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3263 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3264 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3265 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4
3266 // CHECK7-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ]
3267 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3268 // CHECK7-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
3269 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3270 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3271 // CHECK7-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3272 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
3273 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3274 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3275 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
3276 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3277 // CHECK7:       cond.true:
3278 // CHECK7-NEXT:    br label [[COND_END:%.*]]
3279 // CHECK7:       cond.false:
3280 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3281 // CHECK7-NEXT:    br label [[COND_END]]
3282 // CHECK7:       cond.end:
3283 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
3284 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3285 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3286 // CHECK7-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
3287 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3288 // CHECK7:       omp.inner.for.cond:
3289 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
3290 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
3291 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
3292 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3293 // CHECK7:       omp.inner.for.body:
3294 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
3295 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
3296 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
3297 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
3298 // CHECK7-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP9]]
3299 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
3300 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
3301 // CHECK7-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
3302 // CHECK7-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP9]]
3303 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
3304 // CHECK7-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]]
3305 // CHECK7-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]]
3306 // CHECK7-NEXT:    [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
3307 // CHECK7-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP9]]
3308 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
3309 // CHECK7-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]]
3310 // CHECK7-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP9]]
3311 // CHECK7-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
3312 // CHECK7-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP9]]
3313 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
3314 // CHECK7-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]]
3315 // CHECK7-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]]
3316 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3317 // CHECK7:       omp.body.continue:
3318 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3319 // CHECK7:       omp.inner.for.inc:
3320 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
3321 // CHECK7-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
3322 // CHECK7-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
3323 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
3324 // CHECK7:       omp.inner.for.end:
3325 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3326 // CHECK7:       omp.loop.exit:
3327 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
3328 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3329 // CHECK7-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
3330 // CHECK7-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3331 // CHECK7:       .omp.final.then:
3332 // CHECK7-NEXT:    store i32 32000001, ptr [[I]], align 4
3333 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3334 // CHECK7:       .omp.final.done:
3335 // CHECK7-NEXT:    ret void
3336 //
3337 //
3338 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
3339 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
3340 // CHECK7-NEXT:  entry:
3341 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3342 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3343 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3344 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3345 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
3346 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
3347 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
3348 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3349 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3350 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3351 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3352 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3353 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3354 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3355 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3356 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3357 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3358 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3359 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 4
3360 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3361 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 4
3362 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3363 // CHECK7-NEXT:    store ptr null, ptr [[TMP6]], align 4
3364 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3365 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
3366 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3367 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 4
3368 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3369 // CHECK7-NEXT:    store ptr null, ptr [[TMP9]], align 4
3370 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3371 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 4
3372 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3373 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 4
3374 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3375 // CHECK7-NEXT:    store ptr null, ptr [[TMP12]], align 4
3376 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3377 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
3378 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3379 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
3380 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3381 // CHECK7-NEXT:    store ptr null, ptr [[TMP15]], align 4
3382 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3383 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3384 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3385 // CHECK7-NEXT:    store i32 2, ptr [[TMP18]], align 4
3386 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3387 // CHECK7-NEXT:    store i32 4, ptr [[TMP19]], align 4
3388 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3389 // CHECK7-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
3390 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3391 // CHECK7-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
3392 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3393 // CHECK7-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP22]], align 4
3394 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3395 // CHECK7-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4
3396 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3397 // CHECK7-NEXT:    store ptr null, ptr [[TMP24]], align 4
3398 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3399 // CHECK7-NEXT:    store ptr null, ptr [[TMP25]], align 4
3400 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3401 // CHECK7-NEXT:    store i64 4571424, ptr [[TMP26]], align 8
3402 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3403 // CHECK7-NEXT:    store i64 0, ptr [[TMP27]], align 8
3404 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3405 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
3406 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3407 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
3408 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3409 // CHECK7-NEXT:    store i32 0, ptr [[TMP30]], align 4
3410 // CHECK7-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]])
3411 // CHECK7-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3412 // CHECK7-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3413 // CHECK7:       omp_offload.failed:
3414 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
3415 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3416 // CHECK7:       omp_offload.cont:
3417 // CHECK7-NEXT:    ret void
3418 //
3419 //
3420 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
3421 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
3422 // CHECK7-NEXT:  entry:
3423 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3424 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3425 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3426 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3427 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3428 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3429 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3430 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3431 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
3432 // CHECK7-NEXT:    ret void
3433 //
3434 //
3435 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
3436 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3437 // CHECK7-NEXT:  entry:
3438 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3439 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3440 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3441 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3442 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3443 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3444 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3445 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3446 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3447 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3448 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3449 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3450 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
3451 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3452 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3453 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3454 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3455 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3456 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3457 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3458 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3459 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3460 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3461 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3462 // CHECK7-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
3463 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3464 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3465 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3466 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3467 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3468 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3469 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
3470 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3471 // CHECK7:       cond.true:
3472 // CHECK7-NEXT:    br label [[COND_END:%.*]]
3473 // CHECK7:       cond.false:
3474 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3475 // CHECK7-NEXT:    br label [[COND_END]]
3476 // CHECK7:       cond.end:
3477 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3478 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3479 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3480 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3481 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3482 // CHECK7:       omp.inner.for.cond:
3483 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3484 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3485 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3486 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3487 // CHECK7:       omp.inner.for.body:
3488 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3489 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
3490 // CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
3491 // CHECK7-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
3492 // CHECK7-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal !16
3493 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
3494 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]]
3495 // CHECK7-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
3496 // CHECK7-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4
3497 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
3498 // CHECK7-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]]
3499 // CHECK7-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
3500 // CHECK7-NEXT:    [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
3501 // CHECK7-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4
3502 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
3503 // CHECK7-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]]
3504 // CHECK7-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
3505 // CHECK7-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
3506 // CHECK7-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal !16
3507 // CHECK7-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
3508 // CHECK7-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]]
3509 // CHECK7-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
3510 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3511 // CHECK7:       omp.body.continue:
3512 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3513 // CHECK7:       omp.inner.for.inc:
3514 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3515 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
3516 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
3517 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
3518 // CHECK7:       omp.inner.for.end:
3519 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3520 // CHECK7:       omp.loop.exit:
3521 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3522 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3523 // CHECK7-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
3524 // CHECK7-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3525 // CHECK7:       .omp.final.then:
3526 // CHECK7-NEXT:    store i32 32, ptr [[I]], align 4
3527 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3528 // CHECK7:       .omp.final.done:
3529 // CHECK7-NEXT:    ret void
3530 //
3531 //
3532 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
3533 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
3534 // CHECK7-NEXT:  entry:
3535 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3536 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3537 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3538 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3539 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
3540 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
3541 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
3542 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3543 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3544 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3545 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3546 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3547 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3548 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3549 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3550 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3551 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3552 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3553 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 4
3554 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3555 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP5]], align 4
3556 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3557 // CHECK7-NEXT:    store ptr null, ptr [[TMP6]], align 4
3558 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3559 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
3560 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3561 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 4
3562 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3563 // CHECK7-NEXT:    store ptr null, ptr [[TMP9]], align 4
3564 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3565 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP10]], align 4
3566 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3567 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP11]], align 4
3568 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3569 // CHECK7-NEXT:    store ptr null, ptr [[TMP12]], align 4
3570 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3571 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 4
3572 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3573 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 4
3574 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3575 // CHECK7-NEXT:    store ptr null, ptr [[TMP15]], align 4
3576 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3577 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3578 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3579 // CHECK7-NEXT:    store i32 2, ptr [[TMP18]], align 4
3580 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3581 // CHECK7-NEXT:    store i32 4, ptr [[TMP19]], align 4
3582 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3583 // CHECK7-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
3584 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3585 // CHECK7-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 4
3586 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3587 // CHECK7-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP22]], align 4
3588 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3589 // CHECK7-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4
3590 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3591 // CHECK7-NEXT:    store ptr null, ptr [[TMP24]], align 4
3592 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3593 // CHECK7-NEXT:    store ptr null, ptr [[TMP25]], align 4
3594 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3595 // CHECK7-NEXT:    store i64 16908289, ptr [[TMP26]], align 8
3596 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3597 // CHECK7-NEXT:    store i64 0, ptr [[TMP27]], align 8
3598 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3599 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
3600 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3601 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
3602 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3603 // CHECK7-NEXT:    store i32 0, ptr [[TMP30]], align 4
3604 // CHECK7-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]])
3605 // CHECK7-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3606 // CHECK7-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3607 // CHECK7:       omp_offload.failed:
3608 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]]
3609 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3610 // CHECK7:       omp_offload.cont:
3611 // CHECK7-NEXT:    ret void
3612 //
3613 //
3614 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
3615 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] {
3616 // CHECK7-NEXT:  entry:
3617 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3618 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3619 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3620 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3621 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3622 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3623 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3624 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3625 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
3626 // CHECK7-NEXT:    ret void
3627 //
3628 //
3629 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
3630 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3631 // CHECK7-NEXT:  entry:
3632 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3633 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3634 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3635 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3636 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3637 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3638 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3639 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3640 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3641 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3642 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3643 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3644 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
3645 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3646 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3647 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3648 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3649 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3650 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3651 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3652 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3653 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3654 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3655 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3656 // CHECK7-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
3657 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3658 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3659 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3660 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3661 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
3662 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
3663 // CHECK7:       omp.dispatch.cond:
3664 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3665 // CHECK7-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
3666 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3667 // CHECK7:       cond.true:
3668 // CHECK7-NEXT:    br label [[COND_END:%.*]]
3669 // CHECK7:       cond.false:
3670 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3671 // CHECK7-NEXT:    br label [[COND_END]]
3672 // CHECK7:       cond.end:
3673 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3674 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3675 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3676 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3677 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3678 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3679 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
3680 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3681 // CHECK7:       omp.dispatch.body:
3682 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3683 // CHECK7:       omp.inner.for.cond:
3684 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
3685 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
3686 // CHECK7-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
3687 // CHECK7-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3688 // CHECK7:       omp.inner.for.body:
3689 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
3690 // CHECK7-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
3691 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
3692 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
3693 // CHECK7-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP19]]
3694 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
3695 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]]
3696 // CHECK7-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]]
3697 // CHECK7-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP19]]
3698 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
3699 // CHECK7-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]]
3700 // CHECK7-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP19]]
3701 // CHECK7-NEXT:    [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
3702 // CHECK7-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP19]]
3703 // CHECK7-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
3704 // CHECK7-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]]
3705 // CHECK7-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP19]]
3706 // CHECK7-NEXT:    [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
3707 // CHECK7-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP19]]
3708 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
3709 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]]
3710 // CHECK7-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]]
3711 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3712 // CHECK7:       omp.body.continue:
3713 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3714 // CHECK7:       omp.inner.for.inc:
3715 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
3716 // CHECK7-NEXT:    [[ADD8:%.*]] = add i32 [[TMP25]], 1
3717 // CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
3718 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
3719 // CHECK7:       omp.inner.for.end:
3720 // CHECK7-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3721 // CHECK7:       omp.dispatch.inc:
3722 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3723 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3724 // CHECK7-NEXT:    [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
3725 // CHECK7-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4
3726 // CHECK7-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3727 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3728 // CHECK7-NEXT:    [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
3729 // CHECK7-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4
3730 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND]]
3731 // CHECK7:       omp.dispatch.end:
3732 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3733 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3734 // CHECK7-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
3735 // CHECK7-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3736 // CHECK7:       .omp.final.then:
3737 // CHECK7-NEXT:    store i32 -2147483522, ptr [[I]], align 4
3738 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3739 // CHECK7:       .omp.final.done:
3740 // CHECK7-NEXT:    ret void
3741 //
3742 //
3743 // CHECK7-LABEL: define {{[^@]+}}@_Z12test_precondv
3744 // CHECK7-SAME: () #[[ATTR0]] {
3745 // CHECK7-NEXT:  entry:
3746 // CHECK7-NEXT:    [[A:%.*]] = alloca i8, align 1
3747 // CHECK7-NEXT:    [[I:%.*]] = alloca i8, align 1
3748 // CHECK7-NEXT:    [[I_CASTED:%.*]] = alloca i32, align 4
3749 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3750 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
3751 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
3752 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
3753 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i8, align 1
3754 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3755 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3756 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3757 // CHECK7-NEXT:    store i8 0, ptr [[A]], align 1
3758 // CHECK7-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 1
3759 // CHECK7-NEXT:    store i8 [[TMP0]], ptr [[I_CASTED]], align 1
3760 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[I_CASTED]], align 4
3761 // CHECK7-NEXT:    [[TMP2:%.*]] = load i8, ptr [[A]], align 1
3762 // CHECK7-NEXT:    store i8 [[TMP2]], ptr [[A_CASTED]], align 1
3763 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
3764 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3765 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP4]], align 4
3766 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3767 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
3768 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3769 // CHECK7-NEXT:    store ptr null, ptr [[TMP6]], align 4
3770 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3771 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP7]], align 4
3772 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3773 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
3774 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3775 // CHECK7-NEXT:    store ptr null, ptr [[TMP9]], align 4
3776 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3777 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3778 // CHECK7-NEXT:    [[TMP12:%.*]] = load i8, ptr [[A]], align 1
3779 // CHECK7-NEXT:    store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1
3780 // CHECK7-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3781 // CHECK7-NEXT:    [[CONV:%.*]] = sext i8 [[TMP13]] to i32
3782 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
3783 // CHECK7-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
3784 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
3785 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3786 // CHECK7-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
3787 // CHECK7-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3788 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3789 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
3790 // CHECK7-NEXT:    [[TMP15:%.*]] = zext i32 [[ADD4]] to i64
3791 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3792 // CHECK7-NEXT:    store i32 2, ptr [[TMP16]], align 4
3793 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3794 // CHECK7-NEXT:    store i32 2, ptr [[TMP17]], align 4
3795 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3796 // CHECK7-NEXT:    store ptr [[TMP10]], ptr [[TMP18]], align 4
3797 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3798 // CHECK7-NEXT:    store ptr [[TMP11]], ptr [[TMP19]], align 4
3799 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3800 // CHECK7-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP20]], align 4
3801 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3802 // CHECK7-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP21]], align 4
3803 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3804 // CHECK7-NEXT:    store ptr null, ptr [[TMP22]], align 4
3805 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3806 // CHECK7-NEXT:    store ptr null, ptr [[TMP23]], align 4
3807 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3808 // CHECK7-NEXT:    store i64 [[TMP15]], ptr [[TMP24]], align 8
3809 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3810 // CHECK7-NEXT:    store i64 0, ptr [[TMP25]], align 8
3811 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3812 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
3813 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3814 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
3815 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3816 // CHECK7-NEXT:    store i32 0, ptr [[TMP28]], align 4
3817 // CHECK7-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]])
3818 // CHECK7-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3819 // CHECK7-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3820 // CHECK7:       omp_offload.failed:
3821 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
3822 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3823 // CHECK7:       omp_offload.cont:
3824 // CHECK7-NEXT:    ret void
3825 //
3826 //
3827 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
3828 // CHECK7-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
3829 // CHECK7-NEXT:  entry:
3830 // CHECK7-NEXT:    [[I_ADDR:%.*]] = alloca i32, align 4
3831 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3832 // CHECK7-NEXT:    store i32 [[I]], ptr [[I_ADDR]], align 4
3833 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3834 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
3835 // CHECK7-NEXT:    ret void
3836 //
3837 //
3838 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
3839 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
3840 // CHECK7-NEXT:  entry:
3841 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3842 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3843 // CHECK7-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 4
3844 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3845 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3846 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i8, align 1
3847 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3848 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3849 // CHECK7-NEXT:    [[I4:%.*]] = alloca i8, align 1
3850 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3851 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3852 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3853 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3854 // CHECK7-NEXT:    [[I6:%.*]] = alloca i8, align 1
3855 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3856 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3857 // CHECK7-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 4
3858 // CHECK7-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3859 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4
3860 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3861 // CHECK7-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
3862 // CHECK7-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
3863 // CHECK7-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3864 // CHECK7-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
3865 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
3866 // CHECK7-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
3867 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
3868 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3869 // CHECK7-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
3870 // CHECK7-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3871 // CHECK7-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3872 // CHECK7-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
3873 // CHECK7-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3874 // CHECK7-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
3875 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
3876 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3877 // CHECK7:       omp.precond.then:
3878 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3879 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3880 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
3881 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3882 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3883 // CHECK7-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3884 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
3885 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3886 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3887 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3888 // CHECK7-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
3889 // CHECK7-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3890 // CHECK7:       cond.true:
3891 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3892 // CHECK7-NEXT:    br label [[COND_END:%.*]]
3893 // CHECK7:       cond.false:
3894 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3895 // CHECK7-NEXT:    br label [[COND_END]]
3896 // CHECK7:       cond.end:
3897 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3898 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3899 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3900 // CHECK7-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
3901 // CHECK7-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1
3902 // CHECK7-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
3903 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3904 // CHECK7:       omp_if.then:
3905 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3906 // CHECK7:       omp.inner.for.cond:
3907 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
3908 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
3909 // CHECK7-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
3910 // CHECK7-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3911 // CHECK7:       omp.inner.for.body:
3912 // CHECK7-NEXT:    [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]]
3913 // CHECK7-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
3914 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
3915 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
3916 // CHECK7-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
3917 // CHECK7-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
3918 // CHECK7-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !16, !llvm.access.group [[ACC_GRP22]]
3919 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3920 // CHECK7:       omp.body.continue:
3921 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3922 // CHECK7:       omp.inner.for.inc:
3923 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
3924 // CHECK7-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
3925 // CHECK7-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
3926 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
3927 // CHECK7:       omp.inner.for.end:
3928 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
3929 // CHECK7:       omp_if.else:
3930 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND13:%.*]]
3931 // CHECK7:       omp.inner.for.cond13:
3932 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3933 // CHECK7-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3934 // CHECK7-NEXT:    [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
3935 // CHECK7-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
3936 // CHECK7:       omp.inner.for.body15:
3937 // CHECK7-NEXT:    [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3938 // CHECK7-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
3939 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3940 // CHECK7-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
3941 // CHECK7-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
3942 // CHECK7-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
3943 // CHECK7-NEXT:    store i8 [[CONV19]], ptr [[I6]], align 1
3944 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE20:%.*]]
3945 // CHECK7:       omp.body.continue20:
3946 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC21:%.*]]
3947 // CHECK7:       omp.inner.for.inc21:
3948 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3949 // CHECK7-NEXT:    [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
3950 // CHECK7-NEXT:    store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4
3951 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
3952 // CHECK7:       omp.inner.for.end23:
3953 // CHECK7-NEXT:    br label [[OMP_IF_END]]
3954 // CHECK7:       omp_if.end:
3955 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3956 // CHECK7:       omp.loop.exit:
3957 // CHECK7-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3958 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
3959 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
3960 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3961 // CHECK7-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3962 // CHECK7-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3963 // CHECK7:       .omp.final.then:
3964 // CHECK7-NEXT:    [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3965 // CHECK7-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
3966 // CHECK7-NEXT:    [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3967 // CHECK7-NEXT:    [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
3968 // CHECK7-NEXT:    [[SUB26:%.*]] = sub i32 10, [[CONV25]]
3969 // CHECK7-NEXT:    [[SUB27:%.*]] = sub i32 [[SUB26]], 1
3970 // CHECK7-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
3971 // CHECK7-NEXT:    [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
3972 // CHECK7-NEXT:    [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
3973 // CHECK7-NEXT:    [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
3974 // CHECK7-NEXT:    [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
3975 // CHECK7-NEXT:    store i8 [[CONV32]], ptr [[TMP0]], align 1
3976 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3977 // CHECK7:       .omp.final.done:
3978 // CHECK7-NEXT:    br label [[OMP_PRECOND_END]]
3979 // CHECK7:       omp.precond.end:
3980 // CHECK7-NEXT:    ret void
3981 //
3982 //
3983 // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv
3984 // CHECK7-SAME: () #[[ATTR0]] {
3985 // CHECK7-NEXT:  entry:
3986 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
3987 // CHECK7-NEXT:    ret i32 [[CALL]]
3988 //
3989 //
3990 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
3991 // CHECK7-SAME: () #[[ATTR0]] comdat {
3992 // CHECK7-NEXT:  entry:
3993 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
3994 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3995 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
3996 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
3997 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
3998 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3999 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
4000 // CHECK7-NEXT:    store i16 0, ptr [[AA]], align 2
4001 // CHECK7-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA]], align 2
4002 // CHECK7-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
4003 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4004 // CHECK7-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4005 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP2]], align 4
4006 // CHECK7-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4007 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP3]], align 4
4008 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4009 // CHECK7-NEXT:    store ptr null, ptr [[TMP4]], align 4
4010 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4011 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4012 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
4013 // CHECK7-NEXT:    store i32 2, ptr [[TMP7]], align 4
4014 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
4015 // CHECK7-NEXT:    store i32 1, ptr [[TMP8]], align 4
4016 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
4017 // CHECK7-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 4
4018 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
4019 // CHECK7-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 4
4020 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
4021 // CHECK7-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP11]], align 4
4022 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
4023 // CHECK7-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP12]], align 4
4024 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
4025 // CHECK7-NEXT:    store ptr null, ptr [[TMP13]], align 4
4026 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
4027 // CHECK7-NEXT:    store ptr null, ptr [[TMP14]], align 4
4028 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
4029 // CHECK7-NEXT:    store i64 100, ptr [[TMP15]], align 8
4030 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
4031 // CHECK7-NEXT:    store i64 0, ptr [[TMP16]], align 8
4032 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
4033 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
4034 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
4035 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
4036 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
4037 // CHECK7-NEXT:    store i32 0, ptr [[TMP19]], align 4
4038 // CHECK7-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]])
4039 // CHECK7-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
4040 // CHECK7-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4041 // CHECK7:       omp_offload.failed:
4042 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
4043 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4044 // CHECK7:       omp_offload.cont:
4045 // CHECK7-NEXT:    ret i32 0
4046 //
4047 //
4048 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
4049 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] {
4050 // CHECK7-NEXT:  entry:
4051 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4052 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4053 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
4054 // CHECK7-NEXT:    ret void
4055 //
4056 //
4057 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
4058 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
4059 // CHECK7-NEXT:  entry:
4060 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4061 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4062 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
4063 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4064 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4065 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4066 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4067 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4068 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4069 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
4070 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4071 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4072 // CHECK7-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
4073 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
4074 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4075 // CHECK7-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
4076 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4077 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4078 // CHECK7-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
4079 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4080 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4081 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
4082 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
4083 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4084 // CHECK7:       omp.dispatch.cond:
4085 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4086 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
4087 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4088 // CHECK7:       cond.true:
4089 // CHECK7-NEXT:    br label [[COND_END:%.*]]
4090 // CHECK7:       cond.false:
4091 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4092 // CHECK7-NEXT:    br label [[COND_END]]
4093 // CHECK7:       cond.end:
4094 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4095 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4096 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4097 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
4098 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4099 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4100 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4101 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4102 // CHECK7:       omp.dispatch.body:
4103 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4104 // CHECK7:       omp.inner.for.cond:
4105 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]
4106 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]
4107 // CHECK7-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4108 // CHECK7-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4109 // CHECK7:       omp.inner.for.body:
4110 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
4111 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
4112 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4113 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]]
4114 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4115 // CHECK7:       omp.body.continue:
4116 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4117 // CHECK7:       omp.inner.for.inc:
4118 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
4119 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
4120 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
4121 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
4122 // CHECK7:       omp.inner.for.end:
4123 // CHECK7-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4124 // CHECK7:       omp.dispatch.inc:
4125 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4126 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4127 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
4128 // CHECK7-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
4129 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4130 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4131 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
4132 // CHECK7-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
4133 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND]]
4134 // CHECK7:       omp.dispatch.end:
4135 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
4136 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4137 // CHECK7-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
4138 // CHECK7-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4139 // CHECK7:       .omp.final.then:
4140 // CHECK7-NEXT:    store i32 100, ptr [[I]], align 4
4141 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4142 // CHECK7:       .omp.final.done:
4143 // CHECK7-NEXT:    ret void
4144 //
4145 //
4146 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4147 // CHECK7-SAME: () #[[ATTR4:[0-9]+]] {
4148 // CHECK7-NEXT:  entry:
4149 // CHECK7-NEXT:    call void @__tgt_register_requires(i64 1)
4150 // CHECK7-NEXT:    ret void
4151 //
4152 //
4153 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4154 // CHECK9-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4155 // CHECK9-NEXT:  entry:
4156 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4157 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4158 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4159 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4160 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4161 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4162 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4163 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4164 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
4165 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4166 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4167 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4168 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4169 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4170 // CHECK9-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
4171 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4172 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4173 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4174 // CHECK9-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i64 16) ]
4175 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4176 // CHECK9:       omp.inner.for.cond:
4177 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
4178 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
4179 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4180 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4181 // CHECK9:       omp.inner.for.body:
4182 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
4183 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
4184 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4185 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4186 // CHECK9-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4187 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4188 // CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
4189 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]
4190 // CHECK9-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
4191 // CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4192 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4193 // CHECK9-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
4194 // CHECK9-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM1]]
4195 // CHECK9-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP2]]
4196 // CHECK9-NEXT:    [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
4197 // CHECK9-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4198 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4199 // CHECK9-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
4200 // CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM4]]
4201 // CHECK9-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP2]]
4202 // CHECK9-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
4203 // CHECK9-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4204 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4205 // CHECK9-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
4206 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM7]]
4207 // CHECK9-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]]
4208 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4209 // CHECK9:       omp.body.continue:
4210 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4211 // CHECK9:       omp.inner.for.inc:
4212 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
4213 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
4214 // CHECK9-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
4215 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4216 // CHECK9:       omp.inner.for.end:
4217 // CHECK9-NEXT:    store i32 32000001, ptr [[I]], align 4
4218 // CHECK9-NEXT:    ret void
4219 //
4220 //
4221 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4222 // CHECK9-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4223 // CHECK9-NEXT:  entry:
4224 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4225 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4226 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4227 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4228 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4229 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4230 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4231 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4232 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
4233 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4234 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4235 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4236 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4237 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4238 // CHECK9-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
4239 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4240 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4241 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4242 // CHECK9:       omp.inner.for.cond:
4243 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4244 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4245 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4246 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4247 // CHECK9:       omp.inner.for.body:
4248 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4249 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
4250 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4251 // CHECK9-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
4252 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4253 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4
4254 // CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
4255 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM]]
4256 // CHECK9-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4257 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4258 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4
4259 // CHECK9-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
4260 // CHECK9-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM1]]
4261 // CHECK9-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
4262 // CHECK9-NEXT:    [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4263 // CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4264 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
4265 // CHECK9-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
4266 // CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM4]]
4267 // CHECK9-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
4268 // CHECK9-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4269 // CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4270 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4
4271 // CHECK9-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
4272 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM7]]
4273 // CHECK9-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
4274 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4275 // CHECK9:       omp.body.continue:
4276 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4277 // CHECK9:       omp.inner.for.inc:
4278 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4279 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
4280 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
4281 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
4282 // CHECK9:       omp.inner.for.end:
4283 // CHECK9-NEXT:    store i32 32, ptr [[I]], align 4
4284 // CHECK9-NEXT:    ret void
4285 //
4286 //
4287 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4288 // CHECK9-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4289 // CHECK9-NEXT:  entry:
4290 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4291 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4292 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4293 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4294 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4295 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4296 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4297 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4298 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
4299 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4300 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4301 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4302 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4303 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4304 // CHECK9-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
4305 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4306 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4307 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4308 // CHECK9:       omp.inner.for.cond:
4309 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
4310 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
4311 // CHECK9-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
4312 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4313 // CHECK9:       omp.inner.for.body:
4314 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
4315 // CHECK9-NEXT:    [[MUL:%.*]] = mul i32 [[TMP3]], 127
4316 // CHECK9-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
4317 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
4318 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]]
4319 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
4320 // CHECK9-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
4321 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM]]
4322 // CHECK9-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
4323 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]]
4324 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
4325 // CHECK9-NEXT:    [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
4326 // CHECK9-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM1]]
4327 // CHECK9-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]]
4328 // CHECK9-NEXT:    [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4329 // CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]]
4330 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
4331 // CHECK9-NEXT:    [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
4332 // CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM4]]
4333 // CHECK9-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP9]]
4334 // CHECK9-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4335 // CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]]
4336 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
4337 // CHECK9-NEXT:    [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
4338 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM7]]
4339 // CHECK9-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP9]]
4340 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4341 // CHECK9:       omp.body.continue:
4342 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4343 // CHECK9:       omp.inner.for.inc:
4344 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
4345 // CHECK9-NEXT:    [[ADD9:%.*]] = add i32 [[TMP15]], 1
4346 // CHECK9-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
4347 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
4348 // CHECK9:       omp.inner.for.end:
4349 // CHECK9-NEXT:    store i32 -2147483522, ptr [[I]], align 4
4350 // CHECK9-NEXT:    ret void
4351 //
4352 //
4353 // CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv
4354 // CHECK9-SAME: () #[[ATTR0]] {
4355 // CHECK9-NEXT:  entry:
4356 // CHECK9-NEXT:    [[A:%.*]] = alloca i8, align 1
4357 // CHECK9-NEXT:    [[I:%.*]] = alloca i8, align 1
4358 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4359 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4360 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4361 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4362 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4363 // CHECK9-NEXT:    [[I4:%.*]] = alloca i8, align 1
4364 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4365 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i8, align 1
4366 // CHECK9-NEXT:    [[I6:%.*]] = alloca i8, align 1
4367 // CHECK9-NEXT:    [[I7:%.*]] = alloca i8, align 1
4368 // CHECK9-NEXT:    store i8 0, ptr [[A]], align 1
4369 // CHECK9-NEXT:    [[TMP0:%.*]] = load i8, ptr [[A]], align 1
4370 // CHECK9-NEXT:    store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1
4371 // CHECK9-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4372 // CHECK9-NEXT:    [[CONV:%.*]] = sext i8 [[TMP1]] to i32
4373 // CHECK9-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
4374 // CHECK9-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
4375 // CHECK9-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
4376 // CHECK9-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
4377 // CHECK9-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
4378 // CHECK9-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
4379 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4380 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4381 // CHECK9-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
4382 // CHECK9-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4383 // CHECK9-NEXT:    store i8 [[TMP3]], ptr [[I4]], align 1
4384 // CHECK9-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4385 // CHECK9-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
4386 // CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
4387 // CHECK9-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
4388 // CHECK9:       simd.if.then:
4389 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4390 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
4391 // CHECK9-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 1
4392 // CHECK9-NEXT:    store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1
4393 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4394 // CHECK9:       omp.inner.for.cond:
4395 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
4396 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
4397 // CHECK9-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4398 // CHECK9-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4399 // CHECK9:       omp.inner.for.body:
4400 // CHECK9-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP12]]
4401 // CHECK9-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
4402 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
4403 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
4404 // CHECK9-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
4405 // CHECK9-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
4406 // CHECK9-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP12]]
4407 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4408 // CHECK9:       omp.body.continue:
4409 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4410 // CHECK9:       omp.inner.for.inc:
4411 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
4412 // CHECK9-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
4413 // CHECK9-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
4414 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
4415 // CHECK9:       omp.inner.for.end:
4416 // CHECK9-NEXT:    [[TMP12:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4417 // CHECK9-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
4418 // CHECK9-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4419 // CHECK9-NEXT:    [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
4420 // CHECK9-NEXT:    [[SUB15:%.*]] = sub i32 10, [[CONV14]]
4421 // CHECK9-NEXT:    [[SUB16:%.*]] = sub i32 [[SUB15]], 1
4422 // CHECK9-NEXT:    [[ADD17:%.*]] = add i32 [[SUB16]], 1
4423 // CHECK9-NEXT:    [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
4424 // CHECK9-NEXT:    [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
4425 // CHECK9-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
4426 // CHECK9-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
4427 // CHECK9-NEXT:    store i8 [[CONV21]], ptr [[I]], align 1
4428 // CHECK9-NEXT:    br label [[SIMD_IF_END]]
4429 // CHECK9:       simd.if.end:
4430 // CHECK9-NEXT:    ret void
4431 //
4432 //
4433 // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv
4434 // CHECK9-SAME: () #[[ATTR0]] {
4435 // CHECK9-NEXT:  entry:
4436 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
4437 // CHECK9-NEXT:    ret i32 [[CALL]]
4438 //
4439 //
4440 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
4441 // CHECK9-SAME: () #[[ATTR0]] comdat {
4442 // CHECK9-NEXT:  entry:
4443 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
4444 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4445 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4446 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4447 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4448 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
4449 // CHECK9-NEXT:    store i16 0, ptr [[AA]], align 2
4450 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4451 // CHECK9-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
4452 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4453 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4454 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4455 // CHECK9:       omp.inner.for.cond:
4456 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
4457 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
4458 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4459 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4460 // CHECK9:       omp.inner.for.body:
4461 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
4462 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4463 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4464 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]
4465 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4466 // CHECK9:       omp.body.continue:
4467 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4468 // CHECK9:       omp.inner.for.inc:
4469 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
4470 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
4471 // CHECK9-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
4472 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
4473 // CHECK9:       omp.inner.for.end:
4474 // CHECK9-NEXT:    store i32 100, ptr [[I]], align 4
4475 // CHECK9-NEXT:    ret i32 0
4476 //
4477 //
4478 // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4479 // CHECK11-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4480 // CHECK11-NEXT:  entry:
4481 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
4482 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4483 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4484 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4485 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4486 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4487 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4488 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4489 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
4490 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
4491 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4492 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4493 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4494 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4495 // CHECK11-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
4496 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4497 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4498 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
4499 // CHECK11-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i32 16) ]
4500 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4501 // CHECK11:       omp.inner.for.cond:
4502 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
4503 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
4504 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4505 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4506 // CHECK11:       omp.inner.for.body:
4507 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
4508 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
4509 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4510 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
4511 // CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
4512 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
4513 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i32 [[TMP6]]
4514 // CHECK11-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
4515 // CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
4516 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
4517 // CHECK11-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i32 [[TMP9]]
4518 // CHECK11-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP3]]
4519 // CHECK11-NEXT:    [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
4520 // CHECK11-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
4521 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
4522 // CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i32 [[TMP12]]
4523 // CHECK11-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP3]]
4524 // CHECK11-NEXT:    [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
4525 // CHECK11-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
4526 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
4527 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]]
4528 // CHECK11-NEXT:    store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP3]]
4529 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4530 // CHECK11:       omp.body.continue:
4531 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4532 // CHECK11:       omp.inner.for.inc:
4533 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
4534 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
4535 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
4536 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4537 // CHECK11:       omp.inner.for.end:
4538 // CHECK11-NEXT:    store i32 32000001, ptr [[I]], align 4
4539 // CHECK11-NEXT:    ret void
4540 //
4541 //
4542 // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4543 // CHECK11-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4544 // CHECK11-NEXT:  entry:
4545 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
4546 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4547 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4548 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4549 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4550 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4551 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4552 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4553 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
4554 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
4555 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4556 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4557 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4558 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4559 // CHECK11-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
4560 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4561 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4562 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4563 // CHECK11:       omp.inner.for.cond:
4564 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4565 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4566 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4567 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4568 // CHECK11:       omp.inner.for.body:
4569 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4570 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
4571 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4572 // CHECK11-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
4573 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4574 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4
4575 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 [[TMP5]]
4576 // CHECK11-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4577 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4578 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4
4579 // CHECK11-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 [[TMP8]]
4580 // CHECK11-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4
4581 // CHECK11-NEXT:    [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
4582 // CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4583 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
4584 // CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 [[TMP11]]
4585 // CHECK11-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
4586 // CHECK11-NEXT:    [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
4587 // CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4
4588 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4
4589 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
4590 // CHECK11-NEXT:    store float [[MUL4]], ptr [[ARRAYIDX5]], align 4
4591 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4592 // CHECK11:       omp.body.continue:
4593 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4594 // CHECK11:       omp.inner.for.inc:
4595 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4596 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
4597 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
4598 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4599 // CHECK11:       omp.inner.for.end:
4600 // CHECK11-NEXT:    store i32 32, ptr [[I]], align 4
4601 // CHECK11-NEXT:    ret void
4602 //
4603 //
4604 // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4605 // CHECK11-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4606 // CHECK11-NEXT:  entry:
4607 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
4608 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4609 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4610 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4611 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4612 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4613 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4614 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4615 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
4616 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
4617 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4618 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4619 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4620 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4621 // CHECK11-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
4622 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4623 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4624 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4625 // CHECK11:       omp.inner.for.cond:
4626 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
4627 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
4628 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
4629 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4630 // CHECK11:       omp.inner.for.body:
4631 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4632 // CHECK11-NEXT:    [[MUL:%.*]] = mul i32 [[TMP3]], 127
4633 // CHECK11-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
4634 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4635 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
4636 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4637 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 [[TMP5]]
4638 // CHECK11-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
4639 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
4640 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4641 // CHECK11-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 [[TMP8]]
4642 // CHECK11-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP10]]
4643 // CHECK11-NEXT:    [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
4644 // CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
4645 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4646 // CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 [[TMP11]]
4647 // CHECK11-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP10]]
4648 // CHECK11-NEXT:    [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
4649 // CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
4650 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4651 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
4652 // CHECK11-NEXT:    store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP10]]
4653 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4654 // CHECK11:       omp.body.continue:
4655 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4656 // CHECK11:       omp.inner.for.inc:
4657 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4658 // CHECK11-NEXT:    [[ADD6:%.*]] = add i32 [[TMP15]], 1
4659 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4660 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4661 // CHECK11:       omp.inner.for.end:
4662 // CHECK11-NEXT:    store i32 -2147483522, ptr [[I]], align 4
4663 // CHECK11-NEXT:    ret void
4664 //
4665 //
4666 // CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv
4667 // CHECK11-SAME: () #[[ATTR0]] {
4668 // CHECK11-NEXT:  entry:
4669 // CHECK11-NEXT:    [[A:%.*]] = alloca i8, align 1
4670 // CHECK11-NEXT:    [[I:%.*]] = alloca i8, align 1
4671 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4672 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4673 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4674 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4675 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4676 // CHECK11-NEXT:    [[I4:%.*]] = alloca i8, align 1
4677 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4678 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i8, align 1
4679 // CHECK11-NEXT:    [[I6:%.*]] = alloca i8, align 1
4680 // CHECK11-NEXT:    [[I7:%.*]] = alloca i8, align 1
4681 // CHECK11-NEXT:    store i8 0, ptr [[A]], align 1
4682 // CHECK11-NEXT:    [[TMP0:%.*]] = load i8, ptr [[A]], align 1
4683 // CHECK11-NEXT:    store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1
4684 // CHECK11-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4685 // CHECK11-NEXT:    [[CONV:%.*]] = sext i8 [[TMP1]] to i32
4686 // CHECK11-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
4687 // CHECK11-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
4688 // CHECK11-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
4689 // CHECK11-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
4690 // CHECK11-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
4691 // CHECK11-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
4692 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4693 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4694 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
4695 // CHECK11-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4696 // CHECK11-NEXT:    store i8 [[TMP3]], ptr [[I4]], align 1
4697 // CHECK11-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4698 // CHECK11-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
4699 // CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
4700 // CHECK11-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
4701 // CHECK11:       simd.if.then:
4702 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4703 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
4704 // CHECK11-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 1
4705 // CHECK11-NEXT:    store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1
4706 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4707 // CHECK11:       omp.inner.for.cond:
4708 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
4709 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
4710 // CHECK11-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4711 // CHECK11-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4712 // CHECK11:       omp.inner.for.body:
4713 // CHECK11-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP13]]
4714 // CHECK11-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
4715 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
4716 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
4717 // CHECK11-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
4718 // CHECK11-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
4719 // CHECK11-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP13]]
4720 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4721 // CHECK11:       omp.body.continue:
4722 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4723 // CHECK11:       omp.inner.for.inc:
4724 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
4725 // CHECK11-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
4726 // CHECK11-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
4727 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
4728 // CHECK11:       omp.inner.for.end:
4729 // CHECK11-NEXT:    [[TMP12:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4730 // CHECK11-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
4731 // CHECK11-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4732 // CHECK11-NEXT:    [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
4733 // CHECK11-NEXT:    [[SUB15:%.*]] = sub i32 10, [[CONV14]]
4734 // CHECK11-NEXT:    [[SUB16:%.*]] = sub i32 [[SUB15]], 1
4735 // CHECK11-NEXT:    [[ADD17:%.*]] = add i32 [[SUB16]], 1
4736 // CHECK11-NEXT:    [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
4737 // CHECK11-NEXT:    [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
4738 // CHECK11-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
4739 // CHECK11-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
4740 // CHECK11-NEXT:    store i8 [[CONV21]], ptr [[I]], align 1
4741 // CHECK11-NEXT:    br label [[SIMD_IF_END]]
4742 // CHECK11:       simd.if.end:
4743 // CHECK11-NEXT:    ret void
4744 //
4745 //
4746 // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv
4747 // CHECK11-SAME: () #[[ATTR0]] {
4748 // CHECK11-NEXT:  entry:
4749 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
4750 // CHECK11-NEXT:    ret i32 [[CALL]]
4751 //
4752 //
4753 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
4754 // CHECK11-SAME: () #[[ATTR0]] comdat {
4755 // CHECK11-NEXT:  entry:
4756 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
4757 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4758 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4759 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4760 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4761 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
4762 // CHECK11-NEXT:    store i16 0, ptr [[AA]], align 2
4763 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4764 // CHECK11-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
4765 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4766 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4767 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4768 // CHECK11:       omp.inner.for.cond:
4769 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]
4770 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]]
4771 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4772 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4773 // CHECK11:       omp.inner.for.body:
4774 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]
4775 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4776 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4777 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]
4778 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4779 // CHECK11:       omp.body.continue:
4780 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4781 // CHECK11:       omp.inner.for.inc:
4782 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]
4783 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
4784 // CHECK11-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]
4785 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
4786 // CHECK11:       omp.inner.for.end:
4787 // CHECK11-NEXT:    store i32 100, ptr [[I]], align 4
4788 // CHECK11-NEXT:    ret i32 0
4789 //
4790 //
4791 // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4792 // CHECK13-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4793 // CHECK13-NEXT:  entry:
4794 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4795 // CHECK13-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4796 // CHECK13-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4797 // CHECK13-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4798 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4799 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4800 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4801 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4802 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
4803 // CHECK13-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4804 // CHECK13-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4805 // CHECK13-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4806 // CHECK13-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4807 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4808 // CHECK13-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
4809 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4810 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4811 // CHECK13-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4812 // CHECK13-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i64 16) ]
4813 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4814 // CHECK13:       omp.inner.for.cond:
4815 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
4816 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
4817 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4818 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4819 // CHECK13:       omp.inner.for.body:
4820 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
4821 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
4822 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4823 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4824 // CHECK13-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4825 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4826 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
4827 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]
4828 // CHECK13-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
4829 // CHECK13-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4830 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4831 // CHECK13-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
4832 // CHECK13-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM1]]
4833 // CHECK13-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP2]]
4834 // CHECK13-NEXT:    [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
4835 // CHECK13-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4836 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4837 // CHECK13-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
4838 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM4]]
4839 // CHECK13-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP2]]
4840 // CHECK13-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
4841 // CHECK13-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]]
4842 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
4843 // CHECK13-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
4844 // CHECK13-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM7]]
4845 // CHECK13-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]]
4846 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4847 // CHECK13:       omp.body.continue:
4848 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4849 // CHECK13:       omp.inner.for.inc:
4850 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
4851 // CHECK13-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
4852 // CHECK13-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
4853 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4854 // CHECK13:       omp.inner.for.end:
4855 // CHECK13-NEXT:    store i32 32000001, ptr [[I]], align 4
4856 // CHECK13-NEXT:    ret void
4857 //
4858 //
4859 // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4860 // CHECK13-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4861 // CHECK13-NEXT:  entry:
4862 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4863 // CHECK13-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4864 // CHECK13-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4865 // CHECK13-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4866 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4867 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4868 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4869 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4870 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
4871 // CHECK13-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4872 // CHECK13-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4873 // CHECK13-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4874 // CHECK13-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4875 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4876 // CHECK13-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
4877 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4878 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4879 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4880 // CHECK13:       omp.inner.for.cond:
4881 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4882 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4883 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4884 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4885 // CHECK13:       omp.inner.for.body:
4886 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4887 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
4888 // CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4889 // CHECK13-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
4890 // CHECK13-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nontemporal !7
4891 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4
4892 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
4893 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM]]
4894 // CHECK13-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4895 // CHECK13-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4896 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4
4897 // CHECK13-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
4898 // CHECK13-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM1]]
4899 // CHECK13-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
4900 // CHECK13-NEXT:    [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4901 // CHECK13-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4902 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
4903 // CHECK13-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
4904 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM4]]
4905 // CHECK13-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
4906 // CHECK13-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4907 // CHECK13-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nontemporal !7
4908 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4
4909 // CHECK13-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
4910 // CHECK13-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM7]]
4911 // CHECK13-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
4912 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4913 // CHECK13:       omp.body.continue:
4914 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4915 // CHECK13:       omp.inner.for.inc:
4916 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4917 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
4918 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
4919 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4920 // CHECK13:       omp.inner.for.end:
4921 // CHECK13-NEXT:    store i32 32, ptr [[I]], align 4
4922 // CHECK13-NEXT:    ret void
4923 //
4924 //
4925 // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4926 // CHECK13-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4927 // CHECK13-NEXT:  entry:
4928 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4929 // CHECK13-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4930 // CHECK13-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4931 // CHECK13-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4932 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4933 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4934 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4935 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4936 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
4937 // CHECK13-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4938 // CHECK13-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4939 // CHECK13-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4940 // CHECK13-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4941 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4942 // CHECK13-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
4943 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4944 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
4945 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4946 // CHECK13:       omp.inner.for.cond:
4947 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
4948 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
4949 // CHECK13-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
4950 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4951 // CHECK13:       omp.inner.for.body:
4952 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4953 // CHECK13-NEXT:    [[MUL:%.*]] = mul i32 [[TMP3]], 127
4954 // CHECK13-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
4955 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4956 // CHECK13-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]]
4957 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4958 // CHECK13-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
4959 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM]]
4960 // CHECK13-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
4961 // CHECK13-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]]
4962 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4963 // CHECK13-NEXT:    [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
4964 // CHECK13-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM1]]
4965 // CHECK13-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]]
4966 // CHECK13-NEXT:    [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4967 // CHECK13-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]]
4968 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4969 // CHECK13-NEXT:    [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
4970 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM4]]
4971 // CHECK13-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP10]]
4972 // CHECK13-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4973 // CHECK13-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]]
4974 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4975 // CHECK13-NEXT:    [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
4976 // CHECK13-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM7]]
4977 // CHECK13-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP10]]
4978 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4979 // CHECK13:       omp.body.continue:
4980 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4981 // CHECK13:       omp.inner.for.inc:
4982 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4983 // CHECK13-NEXT:    [[ADD9:%.*]] = add i32 [[TMP15]], 1
4984 // CHECK13-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4985 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4986 // CHECK13:       omp.inner.for.end:
4987 // CHECK13-NEXT:    store i32 -2147483522, ptr [[I]], align 4
4988 // CHECK13-NEXT:    ret void
4989 //
4990 //
4991 // CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv
4992 // CHECK13-SAME: () #[[ATTR0]] {
4993 // CHECK13-NEXT:  entry:
4994 // CHECK13-NEXT:    [[A:%.*]] = alloca i8, align 1
4995 // CHECK13-NEXT:    [[I:%.*]] = alloca i8, align 1
4996 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4997 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4998 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4999 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5000 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5001 // CHECK13-NEXT:    [[I4:%.*]] = alloca i8, align 1
5002 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5003 // CHECK13-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i8, align 1
5004 // CHECK13-NEXT:    [[I6:%.*]] = alloca i8, align 1
5005 // CHECK13-NEXT:    [[I7:%.*]] = alloca i8, align 1
5006 // CHECK13-NEXT:    store i8 0, ptr [[A]], align 1
5007 // CHECK13-NEXT:    [[TMP0:%.*]] = load i8, ptr [[A]], align 1
5008 // CHECK13-NEXT:    store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1
5009 // CHECK13-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5010 // CHECK13-NEXT:    [[CONV:%.*]] = sext i8 [[TMP1]] to i32
5011 // CHECK13-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
5012 // CHECK13-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
5013 // CHECK13-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
5014 // CHECK13-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5015 // CHECK13-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5016 // CHECK13-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
5017 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5018 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5019 // CHECK13-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
5020 // CHECK13-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5021 // CHECK13-NEXT:    store i8 [[TMP3]], ptr [[I4]], align 1
5022 // CHECK13-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5023 // CHECK13-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
5024 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5025 // CHECK13-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
5026 // CHECK13:       simd.if.then:
5027 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5028 // CHECK13-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
5029 // CHECK13-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 1
5030 // CHECK13-NEXT:    store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1
5031 // CHECK13-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
5032 // CHECK13-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
5033 // CHECK13-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5034 // CHECK13:       omp_if.then:
5035 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5036 // CHECK13:       omp.inner.for.cond:
5037 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
5038 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
5039 // CHECK13-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
5040 // CHECK13-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5041 // CHECK13:       omp.inner.for.body:
5042 // CHECK13-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP13]]
5043 // CHECK13-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
5044 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
5045 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5046 // CHECK13-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5047 // CHECK13-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5048 // CHECK13-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !7, !llvm.access.group [[ACC_GRP13]]
5049 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5050 // CHECK13:       omp.body.continue:
5051 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5052 // CHECK13:       omp.inner.for.inc:
5053 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
5054 // CHECK13-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
5055 // CHECK13-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
5056 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
5057 // CHECK13:       omp.inner.for.end:
5058 // CHECK13-NEXT:    br label [[OMP_IF_END:%.*]]
5059 // CHECK13:       omp_if.else:
5060 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND13:%.*]]
5061 // CHECK13:       omp.inner.for.cond13:
5062 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5063 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5064 // CHECK13-NEXT:    [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
5065 // CHECK13-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
5066 // CHECK13:       omp.inner.for.body15:
5067 // CHECK13-NEXT:    [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5068 // CHECK13-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
5069 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5070 // CHECK13-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
5071 // CHECK13-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
5072 // CHECK13-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
5073 // CHECK13-NEXT:    store i8 [[CONV19]], ptr [[I6]], align 1
5074 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE20:%.*]]
5075 // CHECK13:       omp.body.continue20:
5076 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC21:%.*]]
5077 // CHECK13:       omp.inner.for.inc21:
5078 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5079 // CHECK13-NEXT:    [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
5080 // CHECK13-NEXT:    store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4
5081 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]]
5082 // CHECK13:       omp.inner.for.end23:
5083 // CHECK13-NEXT:    br label [[OMP_IF_END]]
5084 // CHECK13:       omp_if.end:
5085 // CHECK13-NEXT:    [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5086 // CHECK13-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
5087 // CHECK13-NEXT:    [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5088 // CHECK13-NEXT:    [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
5089 // CHECK13-NEXT:    [[SUB26:%.*]] = sub i32 10, [[CONV25]]
5090 // CHECK13-NEXT:    [[SUB27:%.*]] = sub i32 [[SUB26]], 1
5091 // CHECK13-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
5092 // CHECK13-NEXT:    [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
5093 // CHECK13-NEXT:    [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
5094 // CHECK13-NEXT:    [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
5095 // CHECK13-NEXT:    [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
5096 // CHECK13-NEXT:    store i8 [[CONV32]], ptr [[I]], align 1
5097 // CHECK13-NEXT:    br label [[SIMD_IF_END]]
5098 // CHECK13:       simd.if.end:
5099 // CHECK13-NEXT:    ret void
5100 //
5101 //
5102 // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv
5103 // CHECK13-SAME: () #[[ATTR0]] {
5104 // CHECK13-NEXT:  entry:
5105 // CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
5106 // CHECK13-NEXT:    ret i32 [[CALL]]
5107 //
5108 //
5109 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
5110 // CHECK13-SAME: () #[[ATTR0]] comdat {
5111 // CHECK13-NEXT:  entry:
5112 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
5113 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5114 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5115 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5116 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5117 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
5118 // CHECK13-NEXT:    store i16 0, ptr [[AA]], align 2
5119 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5120 // CHECK13-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
5121 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5122 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
5123 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5124 // CHECK13:       omp.inner.for.cond:
5125 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
5126 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
5127 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5128 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5129 // CHECK13:       omp.inner.for.body:
5130 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
5131 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
5132 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5133 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
5134 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5135 // CHECK13:       omp.body.continue:
5136 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5137 // CHECK13:       omp.inner.for.inc:
5138 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
5139 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
5140 // CHECK13-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
5141 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
5142 // CHECK13:       omp.inner.for.end:
5143 // CHECK13-NEXT:    store i32 100, ptr [[I]], align 4
5144 // CHECK13-NEXT:    ret i32 0
5145 //
5146 //
5147 // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
5148 // CHECK15-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
5149 // CHECK15-NEXT:  entry:
5150 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
5151 // CHECK15-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
5152 // CHECK15-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
5153 // CHECK15-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
5154 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5155 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5156 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5157 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5158 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
5159 // CHECK15-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
5160 // CHECK15-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
5161 // CHECK15-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
5162 // CHECK15-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
5163 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5164 // CHECK15-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
5165 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5166 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
5167 // CHECK15-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
5168 // CHECK15-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i32 16) ]
5169 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5170 // CHECK15:       omp.inner.for.cond:
5171 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
5172 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
5173 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
5174 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5175 // CHECK15:       omp.inner.for.body:
5176 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
5177 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
5178 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
5179 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
5180 // CHECK15-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
5181 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
5182 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i32 [[TMP6]]
5183 // CHECK15-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
5184 // CHECK15-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
5185 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
5186 // CHECK15-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i32 [[TMP9]]
5187 // CHECK15-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP3]]
5188 // CHECK15-NEXT:    [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
5189 // CHECK15-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
5190 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
5191 // CHECK15-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i32 [[TMP12]]
5192 // CHECK15-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP3]]
5193 // CHECK15-NEXT:    [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
5194 // CHECK15-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]]
5195 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
5196 // CHECK15-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]]
5197 // CHECK15-NEXT:    store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP3]]
5198 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5199 // CHECK15:       omp.body.continue:
5200 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5201 // CHECK15:       omp.inner.for.inc:
5202 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
5203 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
5204 // CHECK15-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
5205 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
5206 // CHECK15:       omp.inner.for.end:
5207 // CHECK15-NEXT:    store i32 32000001, ptr [[I]], align 4
5208 // CHECK15-NEXT:    ret void
5209 //
5210 //
5211 // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
5212 // CHECK15-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
5213 // CHECK15-NEXT:  entry:
5214 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
5215 // CHECK15-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
5216 // CHECK15-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
5217 // CHECK15-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
5218 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5219 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5220 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5221 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5222 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
5223 // CHECK15-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
5224 // CHECK15-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
5225 // CHECK15-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
5226 // CHECK15-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
5227 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5228 // CHECK15-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
5229 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5230 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
5231 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5232 // CHECK15:       omp.inner.for.cond:
5233 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5234 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5235 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5236 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5237 // CHECK15:       omp.inner.for.body:
5238 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5239 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
5240 // CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
5241 // CHECK15-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
5242 // CHECK15-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nontemporal !8
5243 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4
5244 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 [[TMP5]]
5245 // CHECK15-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4
5246 // CHECK15-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4
5247 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4
5248 // CHECK15-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 [[TMP8]]
5249 // CHECK15-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4
5250 // CHECK15-NEXT:    [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
5251 // CHECK15-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4
5252 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
5253 // CHECK15-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 [[TMP11]]
5254 // CHECK15-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
5255 // CHECK15-NEXT:    [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
5256 // CHECK15-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nontemporal !8
5257 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4
5258 // CHECK15-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
5259 // CHECK15-NEXT:    store float [[MUL4]], ptr [[ARRAYIDX5]], align 4
5260 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5261 // CHECK15:       omp.body.continue:
5262 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5263 // CHECK15:       omp.inner.for.inc:
5264 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5265 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
5266 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
5267 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
5268 // CHECK15:       omp.inner.for.end:
5269 // CHECK15-NEXT:    store i32 32, ptr [[I]], align 4
5270 // CHECK15-NEXT:    ret void
5271 //
5272 //
5273 // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
5274 // CHECK15-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
5275 // CHECK15-NEXT:  entry:
5276 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
5277 // CHECK15-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
5278 // CHECK15-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
5279 // CHECK15-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
5280 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5281 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5282 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5283 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5284 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
5285 // CHECK15-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
5286 // CHECK15-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
5287 // CHECK15-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
5288 // CHECK15-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
5289 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5290 // CHECK15-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
5291 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5292 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
5293 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5294 // CHECK15:       omp.inner.for.cond:
5295 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
5296 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
5297 // CHECK15-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
5298 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5299 // CHECK15:       omp.inner.for.body:
5300 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
5301 // CHECK15-NEXT:    [[MUL:%.*]] = mul i32 [[TMP3]], 127
5302 // CHECK15-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
5303 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
5304 // CHECK15-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]]
5305 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
5306 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 [[TMP5]]
5307 // CHECK15-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
5308 // CHECK15-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]]
5309 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
5310 // CHECK15-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 [[TMP8]]
5311 // CHECK15-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP11]]
5312 // CHECK15-NEXT:    [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
5313 // CHECK15-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]]
5314 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
5315 // CHECK15-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 [[TMP11]]
5316 // CHECK15-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP11]]
5317 // CHECK15-NEXT:    [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
5318 // CHECK15-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]]
5319 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
5320 // CHECK15-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
5321 // CHECK15-NEXT:    store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP11]]
5322 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5323 // CHECK15:       omp.body.continue:
5324 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5325 // CHECK15:       omp.inner.for.inc:
5326 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
5327 // CHECK15-NEXT:    [[ADD6:%.*]] = add i32 [[TMP15]], 1
5328 // CHECK15-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
5329 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
5330 // CHECK15:       omp.inner.for.end:
5331 // CHECK15-NEXT:    store i32 -2147483522, ptr [[I]], align 4
5332 // CHECK15-NEXT:    ret void
5333 //
5334 //
5335 // CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv
5336 // CHECK15-SAME: () #[[ATTR0]] {
5337 // CHECK15-NEXT:  entry:
5338 // CHECK15-NEXT:    [[A:%.*]] = alloca i8, align 1
5339 // CHECK15-NEXT:    [[I:%.*]] = alloca i8, align 1
5340 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i8, align 1
5341 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5342 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5343 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5344 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5345 // CHECK15-NEXT:    [[I4:%.*]] = alloca i8, align 1
5346 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5347 // CHECK15-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i8, align 1
5348 // CHECK15-NEXT:    [[I6:%.*]] = alloca i8, align 1
5349 // CHECK15-NEXT:    [[I7:%.*]] = alloca i8, align 1
5350 // CHECK15-NEXT:    store i8 0, ptr [[A]], align 1
5351 // CHECK15-NEXT:    [[TMP0:%.*]] = load i8, ptr [[A]], align 1
5352 // CHECK15-NEXT:    store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1
5353 // CHECK15-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5354 // CHECK15-NEXT:    [[CONV:%.*]] = sext i8 [[TMP1]] to i32
5355 // CHECK15-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
5356 // CHECK15-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
5357 // CHECK15-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
5358 // CHECK15-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5359 // CHECK15-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5360 // CHECK15-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
5361 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5362 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5363 // CHECK15-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
5364 // CHECK15-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5365 // CHECK15-NEXT:    store i8 [[TMP3]], ptr [[I4]], align 1
5366 // CHECK15-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5367 // CHECK15-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
5368 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5369 // CHECK15-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
5370 // CHECK15:       simd.if.then:
5371 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5372 // CHECK15-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
5373 // CHECK15-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 1
5374 // CHECK15-NEXT:    store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1
5375 // CHECK15-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
5376 // CHECK15-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
5377 // CHECK15-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5378 // CHECK15:       omp_if.then:
5379 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5380 // CHECK15:       omp.inner.for.cond:
5381 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
5382 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
5383 // CHECK15-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
5384 // CHECK15-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5385 // CHECK15:       omp.inner.for.body:
5386 // CHECK15-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP14]]
5387 // CHECK15-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
5388 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
5389 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5390 // CHECK15-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5391 // CHECK15-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5392 // CHECK15-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !8, !llvm.access.group [[ACC_GRP14]]
5393 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5394 // CHECK15:       omp.body.continue:
5395 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5396 // CHECK15:       omp.inner.for.inc:
5397 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
5398 // CHECK15-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
5399 // CHECK15-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
5400 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
5401 // CHECK15:       omp.inner.for.end:
5402 // CHECK15-NEXT:    br label [[OMP_IF_END:%.*]]
5403 // CHECK15:       omp_if.else:
5404 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND13:%.*]]
5405 // CHECK15:       omp.inner.for.cond13:
5406 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5407 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5408 // CHECK15-NEXT:    [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
5409 // CHECK15-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
5410 // CHECK15:       omp.inner.for.body15:
5411 // CHECK15-NEXT:    [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5412 // CHECK15-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
5413 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5414 // CHECK15-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
5415 // CHECK15-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
5416 // CHECK15-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
5417 // CHECK15-NEXT:    store i8 [[CONV19]], ptr [[I6]], align 1
5418 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE20:%.*]]
5419 // CHECK15:       omp.body.continue20:
5420 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC21:%.*]]
5421 // CHECK15:       omp.inner.for.inc21:
5422 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5423 // CHECK15-NEXT:    [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
5424 // CHECK15-NEXT:    store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4
5425 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]]
5426 // CHECK15:       omp.inner.for.end23:
5427 // CHECK15-NEXT:    br label [[OMP_IF_END]]
5428 // CHECK15:       omp_if.end:
5429 // CHECK15-NEXT:    [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5430 // CHECK15-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
5431 // CHECK15-NEXT:    [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5432 // CHECK15-NEXT:    [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
5433 // CHECK15-NEXT:    [[SUB26:%.*]] = sub i32 10, [[CONV25]]
5434 // CHECK15-NEXT:    [[SUB27:%.*]] = sub i32 [[SUB26]], 1
5435 // CHECK15-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
5436 // CHECK15-NEXT:    [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
5437 // CHECK15-NEXT:    [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
5438 // CHECK15-NEXT:    [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
5439 // CHECK15-NEXT:    [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
5440 // CHECK15-NEXT:    store i8 [[CONV32]], ptr [[I]], align 1
5441 // CHECK15-NEXT:    br label [[SIMD_IF_END]]
5442 // CHECK15:       simd.if.end:
5443 // CHECK15-NEXT:    ret void
5444 //
5445 //
5446 // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv
5447 // CHECK15-SAME: () #[[ATTR0]] {
5448 // CHECK15-NEXT:  entry:
5449 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
5450 // CHECK15-NEXT:    ret i32 [[CALL]]
5451 //
5452 //
5453 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
5454 // CHECK15-SAME: () #[[ATTR0]] comdat {
5455 // CHECK15-NEXT:  entry:
5456 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
5457 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5458 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5459 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5460 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5461 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
5462 // CHECK15-NEXT:    store i16 0, ptr [[AA]], align 2
5463 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5464 // CHECK15-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
5465 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5466 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
5467 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5468 // CHECK15:       omp.inner.for.cond:
5469 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
5470 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
5471 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5472 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5473 // CHECK15:       omp.inner.for.body:
5474 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
5475 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
5476 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5477 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
5478 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5479 // CHECK15:       omp.body.continue:
5480 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5481 // CHECK15:       omp.inner.for.inc:
5482 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
5483 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
5484 // CHECK15-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
5485 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
5486 // CHECK15:       omp.inner.for.end:
5487 // CHECK15-NEXT:    store i32 100, ptr [[I]], align 4
5488 // CHECK15-NEXT:    ret i32 0
5489 //
5490 //
5491 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
5492 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
5493 // CHECK17-NEXT:  entry:
5494 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
5495 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5496 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5497 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5498 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
5499 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
5500 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5501 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5502 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5503 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
5504 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
5505 // CHECK17-NEXT:    ret void
5506 //
5507 //
5508 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
5509 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
5510 // CHECK17-NEXT:  entry:
5511 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5512 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5513 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5514 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5515 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5516 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
5517 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5518 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5519 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5520 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5521 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5522 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5523 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5524 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5525 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5526 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5527 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5528 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5529 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
5530 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
5531 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5532 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
5533 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
5534 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8
5535 // CHECK17-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ]
5536 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5537 // CHECK17-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
5538 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5539 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5540 // CHECK17-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5541 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
5542 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5543 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5544 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
5545 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5546 // CHECK17:       cond.true:
5547 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5548 // CHECK17:       cond.false:
5549 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5550 // CHECK17-NEXT:    br label [[COND_END]]
5551 // CHECK17:       cond.end:
5552 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
5553 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5554 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5555 // CHECK17-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
5556 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5557 // CHECK17:       omp.inner.for.cond:
5558 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
5559 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
5560 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
5561 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5562 // CHECK17:       omp.inner.for.body:
5563 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
5564 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
5565 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
5566 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
5567 // CHECK17-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP9]]
5568 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
5569 // CHECK17-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
5570 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
5571 // CHECK17-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
5572 // CHECK17-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP9]]
5573 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
5574 // CHECK17-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
5575 // CHECK17-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]]
5576 // CHECK17-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP9]]
5577 // CHECK17-NEXT:    [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
5578 // CHECK17-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP9]]
5579 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
5580 // CHECK17-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
5581 // CHECK17-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]]
5582 // CHECK17-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]]
5583 // CHECK17-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
5584 // CHECK17-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP9]]
5585 // CHECK17-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
5586 // CHECK17-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
5587 // CHECK17-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]]
5588 // CHECK17-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP9]]
5589 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5590 // CHECK17:       omp.body.continue:
5591 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5592 // CHECK17:       omp.inner.for.inc:
5593 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
5594 // CHECK17-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
5595 // CHECK17-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
5596 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
5597 // CHECK17:       omp.inner.for.end:
5598 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5599 // CHECK17:       omp.loop.exit:
5600 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
5601 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5602 // CHECK17-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
5603 // CHECK17-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5604 // CHECK17:       .omp.final.then:
5605 // CHECK17-NEXT:    store i32 32000001, ptr [[I]], align 4
5606 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5607 // CHECK17:       .omp.final.done:
5608 // CHECK17-NEXT:    ret void
5609 //
5610 //
5611 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
5612 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
5613 // CHECK17-NEXT:  entry:
5614 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
5615 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5616 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5617 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5618 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
5619 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
5620 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5621 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5622 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5623 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
5624 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
5625 // CHECK17-NEXT:    ret void
5626 //
5627 //
5628 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
5629 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
5630 // CHECK17-NEXT:  entry:
5631 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5632 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5633 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5634 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5635 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5636 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
5637 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5638 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5639 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5640 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5641 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5642 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5643 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5644 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5645 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5646 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5647 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5648 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5649 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
5650 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
5651 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5652 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
5653 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
5654 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5655 // CHECK17-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
5656 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5657 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5658 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5659 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
5660 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5661 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5662 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
5663 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5664 // CHECK17:       cond.true:
5665 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5666 // CHECK17:       cond.false:
5667 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5668 // CHECK17-NEXT:    br label [[COND_END]]
5669 // CHECK17:       cond.end:
5670 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5671 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5672 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5673 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
5674 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5675 // CHECK17:       omp.inner.for.cond:
5676 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5677 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5678 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5679 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5680 // CHECK17:       omp.inner.for.body:
5681 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5682 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
5683 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
5684 // CHECK17-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
5685 // CHECK17-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
5686 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
5687 // CHECK17-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
5688 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
5689 // CHECK17-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
5690 // CHECK17-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
5691 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
5692 // CHECK17-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
5693 // CHECK17-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
5694 // CHECK17-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
5695 // CHECK17-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
5696 // CHECK17-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
5697 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
5698 // CHECK17-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
5699 // CHECK17-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
5700 // CHECK17-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
5701 // CHECK17-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
5702 // CHECK17-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
5703 // CHECK17-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
5704 // CHECK17-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
5705 // CHECK17-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
5706 // CHECK17-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
5707 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5708 // CHECK17:       omp.body.continue:
5709 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5710 // CHECK17:       omp.inner.for.inc:
5711 // CHECK17-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5712 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
5713 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
5714 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
5715 // CHECK17:       omp.inner.for.end:
5716 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5717 // CHECK17:       omp.loop.exit:
5718 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
5719 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5720 // CHECK17-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5721 // CHECK17-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5722 // CHECK17:       .omp.final.then:
5723 // CHECK17-NEXT:    store i32 32, ptr [[I]], align 4
5724 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5725 // CHECK17:       .omp.final.done:
5726 // CHECK17-NEXT:    ret void
5727 //
5728 //
5729 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
5730 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
5731 // CHECK17-NEXT:  entry:
5732 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
5733 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5734 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5735 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5736 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
5737 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
5738 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5739 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5740 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5741 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
5742 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
5743 // CHECK17-NEXT:    ret void
5744 //
5745 //
5746 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
5747 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
5748 // CHECK17-NEXT:  entry:
5749 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5750 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5751 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5752 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5753 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5754 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
5755 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5756 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5757 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5758 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5759 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5760 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5761 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5762 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5763 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5764 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5765 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5766 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5767 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
5768 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
5769 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5770 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
5771 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
5772 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5773 // CHECK17-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
5774 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5775 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5776 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5777 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
5778 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
5779 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
5780 // CHECK17:       omp.dispatch.cond:
5781 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5782 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
5783 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5784 // CHECK17:       cond.true:
5785 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5786 // CHECK17:       cond.false:
5787 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5788 // CHECK17-NEXT:    br label [[COND_END]]
5789 // CHECK17:       cond.end:
5790 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5791 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5792 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5793 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
5794 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5795 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5796 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
5797 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5798 // CHECK17:       omp.dispatch.body:
5799 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5800 // CHECK17:       omp.inner.for.cond:
5801 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
5802 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
5803 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
5804 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5805 // CHECK17:       omp.inner.for.body:
5806 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
5807 // CHECK17-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
5808 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
5809 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
5810 // CHECK17-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP18]]
5811 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
5812 // CHECK17-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
5813 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
5814 // CHECK17-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]
5815 // CHECK17-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP18]]
5816 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
5817 // CHECK17-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
5818 // CHECK17-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
5819 // CHECK17-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP18]]
5820 // CHECK17-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
5821 // CHECK17-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP18]]
5822 // CHECK17-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
5823 // CHECK17-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
5824 // CHECK17-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
5825 // CHECK17-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]]
5826 // CHECK17-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
5827 // CHECK17-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP18]]
5828 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
5829 // CHECK17-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
5830 // CHECK17-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
5831 // CHECK17-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP18]]
5832 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5833 // CHECK17:       omp.body.continue:
5834 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5835 // CHECK17:       omp.inner.for.inc:
5836 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
5837 // CHECK17-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
5838 // CHECK17-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
5839 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
5840 // CHECK17:       omp.inner.for.end:
5841 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
5842 // CHECK17:       omp.dispatch.inc:
5843 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5844 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
5845 // CHECK17-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
5846 // CHECK17-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
5847 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5848 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
5849 // CHECK17-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
5850 // CHECK17-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
5851 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
5852 // CHECK17:       omp.dispatch.end:
5853 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
5854 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5855 // CHECK17-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
5856 // CHECK17-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5857 // CHECK17:       .omp.final.then:
5858 // CHECK17-NEXT:    store i32 -2147483522, ptr [[I]], align 4
5859 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5860 // CHECK17:       .omp.final.done:
5861 // CHECK17-NEXT:    ret void
5862 //
5863 //
5864 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
5865 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
5866 // CHECK17-NEXT:  entry:
5867 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
5868 // CHECK17-NEXT:    [[I_ADDR:%.*]] = alloca i64, align 8
5869 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5870 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
5871 // CHECK17-NEXT:    store i64 [[I]], ptr [[I_ADDR]], align 8
5872 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5873 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
5874 // CHECK17-NEXT:    ret void
5875 //
5876 //
5877 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
5878 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
5879 // CHECK17-NEXT:  entry:
5880 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5881 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5882 // CHECK17-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
5883 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
5884 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5885 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i8, align 1
5886 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5887 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5888 // CHECK17-NEXT:    [[I4:%.*]] = alloca i8, align 1
5889 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5890 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5891 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5892 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5893 // CHECK17-NEXT:    [[I6:%.*]] = alloca i8, align 1
5894 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5895 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5896 // CHECK17-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
5897 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
5898 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
5899 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
5900 // CHECK17-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
5901 // CHECK17-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
5902 // CHECK17-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5903 // CHECK17-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
5904 // CHECK17-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
5905 // CHECK17-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
5906 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
5907 // CHECK17-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5908 // CHECK17-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5909 // CHECK17-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
5910 // CHECK17-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5911 // CHECK17-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
5912 // CHECK17-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5913 // CHECK17-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
5914 // CHECK17-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5915 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5916 // CHECK17:       omp.precond.then:
5917 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5918 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5919 // CHECK17-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
5920 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5921 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5922 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5923 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
5924 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5925 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5926 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5927 // CHECK17-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
5928 // CHECK17-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5929 // CHECK17:       cond.true:
5930 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5931 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5932 // CHECK17:       cond.false:
5933 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5934 // CHECK17-NEXT:    br label [[COND_END]]
5935 // CHECK17:       cond.end:
5936 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
5937 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5938 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5939 // CHECK17-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
5940 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5941 // CHECK17:       omp.inner.for.cond:
5942 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
5943 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
5944 // CHECK17-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
5945 // CHECK17-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5946 // CHECK17:       omp.inner.for.body:
5947 // CHECK17-NEXT:    [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]]
5948 // CHECK17-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
5949 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
5950 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
5951 // CHECK17-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5952 // CHECK17-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5953 // CHECK17-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP21]]
5954 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5955 // CHECK17:       omp.body.continue:
5956 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5957 // CHECK17:       omp.inner.for.inc:
5958 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
5959 // CHECK17-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
5960 // CHECK17-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
5961 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
5962 // CHECK17:       omp.inner.for.end:
5963 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5964 // CHECK17:       omp.loop.exit:
5965 // CHECK17-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5966 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
5967 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
5968 // CHECK17-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5969 // CHECK17-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
5970 // CHECK17-NEXT:    br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5971 // CHECK17:       .omp.final.then:
5972 // CHECK17-NEXT:    [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5973 // CHECK17-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
5974 // CHECK17-NEXT:    [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
5975 // CHECK17-NEXT:    [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
5976 // CHECK17-NEXT:    [[SUB15:%.*]] = sub i32 10, [[CONV14]]
5977 // CHECK17-NEXT:    [[SUB16:%.*]] = sub i32 [[SUB15]], 1
5978 // CHECK17-NEXT:    [[ADD17:%.*]] = add i32 [[SUB16]], 1
5979 // CHECK17-NEXT:    [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
5980 // CHECK17-NEXT:    [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
5981 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
5982 // CHECK17-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
5983 // CHECK17-NEXT:    store i8 [[CONV21]], ptr [[TMP0]], align 1
5984 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5985 // CHECK17:       .omp.final.done:
5986 // CHECK17-NEXT:    br label [[OMP_PRECOND_END]]
5987 // CHECK17:       omp.precond.end:
5988 // CHECK17-NEXT:    ret void
5989 //
5990 //
5991 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
5992 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
5993 // CHECK17-NEXT:  entry:
5994 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
5995 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5996 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
5997 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5998 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
5999 // CHECK17-NEXT:    ret void
6000 //
6001 //
6002 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
6003 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
6004 // CHECK17-NEXT:  entry:
6005 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6006 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6007 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
6008 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6009 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6010 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6011 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6012 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6013 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6014 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
6015 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6016 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6017 // CHECK17-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
6018 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
6019 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6020 // CHECK17-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
6021 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6022 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6023 // CHECK17-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
6024 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6025 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6026 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
6027 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
6028 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6029 // CHECK17:       omp.dispatch.cond:
6030 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6031 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
6032 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6033 // CHECK17:       cond.true:
6034 // CHECK17-NEXT:    br label [[COND_END:%.*]]
6035 // CHECK17:       cond.false:
6036 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6037 // CHECK17-NEXT:    br label [[COND_END]]
6038 // CHECK17:       cond.end:
6039 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6040 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6041 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6042 // CHECK17-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
6043 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6044 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6045 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6046 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6047 // CHECK17:       omp.dispatch.body:
6048 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6049 // CHECK17:       omp.inner.for.cond:
6050 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
6051 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
6052 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6053 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6054 // CHECK17:       omp.inner.for.body:
6055 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
6056 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6057 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6058 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
6059 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6060 // CHECK17:       omp.body.continue:
6061 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6062 // CHECK17:       omp.inner.for.inc:
6063 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
6064 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
6065 // CHECK17-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
6066 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
6067 // CHECK17:       omp.inner.for.end:
6068 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
6069 // CHECK17:       omp.dispatch.inc:
6070 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6071 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6072 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
6073 // CHECK17-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
6074 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6075 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6076 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
6077 // CHECK17-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
6078 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
6079 // CHECK17:       omp.dispatch.end:
6080 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
6081 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6082 // CHECK17-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
6083 // CHECK17-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6084 // CHECK17:       .omp.final.then:
6085 // CHECK17-NEXT:    store i32 100, ptr [[I]], align 4
6086 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6087 // CHECK17:       .omp.final.done:
6088 // CHECK17-NEXT:    ret void
6089 //
6090 //
6091 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
6092 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
6093 // CHECK19-NEXT:  entry:
6094 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
6095 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6096 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6097 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6098 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6099 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
6100 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6101 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6102 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6103 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6104 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
6105 // CHECK19-NEXT:    ret void
6106 //
6107 //
6108 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
6109 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
6110 // CHECK19-NEXT:  entry:
6111 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6112 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6113 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6114 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6115 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6116 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6117 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6118 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6119 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6120 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6121 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6122 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6123 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
6124 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6125 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6126 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6127 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6128 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6129 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6130 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
6131 // CHECK19-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
6132 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
6133 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
6134 // CHECK19-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4
6135 // CHECK19-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ]
6136 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6137 // CHECK19-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
6138 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6139 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6140 // CHECK19-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6141 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
6142 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6143 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6144 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
6145 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6146 // CHECK19:       cond.true:
6147 // CHECK19-NEXT:    br label [[COND_END:%.*]]
6148 // CHECK19:       cond.false:
6149 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6150 // CHECK19-NEXT:    br label [[COND_END]]
6151 // CHECK19:       cond.end:
6152 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
6153 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6154 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6155 // CHECK19-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
6156 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6157 // CHECK19:       omp.inner.for.cond:
6158 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
6159 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
6160 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
6161 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6162 // CHECK19:       omp.inner.for.body:
6163 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
6164 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
6165 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
6166 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
6167 // CHECK19-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP10]]
6168 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
6169 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
6170 // CHECK19-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
6171 // CHECK19-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP10]]
6172 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
6173 // CHECK19-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]]
6174 // CHECK19-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]]
6175 // CHECK19-NEXT:    [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
6176 // CHECK19-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP10]]
6177 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
6178 // CHECK19-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]]
6179 // CHECK19-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]]
6180 // CHECK19-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
6181 // CHECK19-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP10]]
6182 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
6183 // CHECK19-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]]
6184 // CHECK19-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]]
6185 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6186 // CHECK19:       omp.body.continue:
6187 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6188 // CHECK19:       omp.inner.for.inc:
6189 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
6190 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
6191 // CHECK19-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
6192 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
6193 // CHECK19:       omp.inner.for.end:
6194 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6195 // CHECK19:       omp.loop.exit:
6196 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
6197 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6198 // CHECK19-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6199 // CHECK19-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6200 // CHECK19:       .omp.final.then:
6201 // CHECK19-NEXT:    store i32 32000001, ptr [[I]], align 4
6202 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6203 // CHECK19:       .omp.final.done:
6204 // CHECK19-NEXT:    ret void
6205 //
6206 //
6207 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
6208 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
6209 // CHECK19-NEXT:  entry:
6210 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
6211 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6212 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6213 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6214 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6215 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
6216 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6217 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6218 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6219 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6220 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
6221 // CHECK19-NEXT:    ret void
6222 //
6223 //
6224 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
6225 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
6226 // CHECK19-NEXT:  entry:
6227 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6228 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6229 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6230 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6231 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6232 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6233 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6234 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6235 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6236 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6237 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6238 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6239 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
6240 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6241 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6242 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6243 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6244 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6245 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6246 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
6247 // CHECK19-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
6248 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
6249 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
6250 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6251 // CHECK19-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
6252 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6253 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6254 // CHECK19-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6255 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
6256 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6257 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6258 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
6259 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6260 // CHECK19:       cond.true:
6261 // CHECK19-NEXT:    br label [[COND_END:%.*]]
6262 // CHECK19:       cond.false:
6263 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6264 // CHECK19-NEXT:    br label [[COND_END]]
6265 // CHECK19:       cond.end:
6266 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6267 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6268 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6269 // CHECK19-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
6270 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6271 // CHECK19:       omp.inner.for.cond:
6272 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6273 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6274 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6275 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6276 // CHECK19:       omp.inner.for.body:
6277 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6278 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
6279 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
6280 // CHECK19-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
6281 // CHECK19-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4
6282 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
6283 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]]
6284 // CHECK19-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
6285 // CHECK19-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4
6286 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
6287 // CHECK19-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]]
6288 // CHECK19-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
6289 // CHECK19-NEXT:    [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
6290 // CHECK19-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4
6291 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
6292 // CHECK19-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]]
6293 // CHECK19-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
6294 // CHECK19-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
6295 // CHECK19-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4
6296 // CHECK19-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
6297 // CHECK19-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]]
6298 // CHECK19-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
6299 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6300 // CHECK19:       omp.body.continue:
6301 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6302 // CHECK19:       omp.inner.for.inc:
6303 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6304 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
6305 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
6306 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
6307 // CHECK19:       omp.inner.for.end:
6308 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6309 // CHECK19:       omp.loop.exit:
6310 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
6311 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6312 // CHECK19-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
6313 // CHECK19-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6314 // CHECK19:       .omp.final.then:
6315 // CHECK19-NEXT:    store i32 32, ptr [[I]], align 4
6316 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6317 // CHECK19:       .omp.final.done:
6318 // CHECK19-NEXT:    ret void
6319 //
6320 //
6321 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
6322 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
6323 // CHECK19-NEXT:  entry:
6324 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
6325 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6326 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6327 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6328 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6329 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
6330 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6331 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6332 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6333 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6334 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
6335 // CHECK19-NEXT:    ret void
6336 //
6337 //
6338 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
6339 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
6340 // CHECK19-NEXT:  entry:
6341 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6342 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6343 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6344 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6345 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6346 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6347 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6348 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6349 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6350 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6351 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6352 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6353 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
6354 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6355 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6356 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6357 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6358 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6359 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6360 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
6361 // CHECK19-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
6362 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
6363 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
6364 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6365 // CHECK19-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
6366 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6367 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6368 // CHECK19-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6369 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
6370 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
6371 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6372 // CHECK19:       omp.dispatch.cond:
6373 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6374 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
6375 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6376 // CHECK19:       cond.true:
6377 // CHECK19-NEXT:    br label [[COND_END:%.*]]
6378 // CHECK19:       cond.false:
6379 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6380 // CHECK19-NEXT:    br label [[COND_END]]
6381 // CHECK19:       cond.end:
6382 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6383 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6384 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6385 // CHECK19-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
6386 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6387 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6388 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
6389 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6390 // CHECK19:       omp.dispatch.body:
6391 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6392 // CHECK19:       omp.inner.for.cond:
6393 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
6394 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
6395 // CHECK19-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
6396 // CHECK19-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6397 // CHECK19:       omp.inner.for.body:
6398 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
6399 // CHECK19-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
6400 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
6401 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
6402 // CHECK19-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP19]]
6403 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
6404 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]]
6405 // CHECK19-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]]
6406 // CHECK19-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP19]]
6407 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
6408 // CHECK19-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]]
6409 // CHECK19-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP19]]
6410 // CHECK19-NEXT:    [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
6411 // CHECK19-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP19]]
6412 // CHECK19-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
6413 // CHECK19-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]]
6414 // CHECK19-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP19]]
6415 // CHECK19-NEXT:    [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
6416 // CHECK19-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP19]]
6417 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
6418 // CHECK19-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]]
6419 // CHECK19-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]]
6420 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6421 // CHECK19:       omp.body.continue:
6422 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6423 // CHECK19:       omp.inner.for.inc:
6424 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
6425 // CHECK19-NEXT:    [[ADD8:%.*]] = add i32 [[TMP25]], 1
6426 // CHECK19-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
6427 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
6428 // CHECK19:       omp.inner.for.end:
6429 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
6430 // CHECK19:       omp.dispatch.inc:
6431 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6432 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6433 // CHECK19-NEXT:    [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
6434 // CHECK19-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4
6435 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6436 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6437 // CHECK19-NEXT:    [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
6438 // CHECK19-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4
6439 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
6440 // CHECK19:       omp.dispatch.end:
6441 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
6442 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6443 // CHECK19-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
6444 // CHECK19-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6445 // CHECK19:       .omp.final.then:
6446 // CHECK19-NEXT:    store i32 -2147483522, ptr [[I]], align 4
6447 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6448 // CHECK19:       .omp.final.done:
6449 // CHECK19-NEXT:    ret void
6450 //
6451 //
6452 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
6453 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
6454 // CHECK19-NEXT:  entry:
6455 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
6456 // CHECK19-NEXT:    [[I_ADDR:%.*]] = alloca i32, align 4
6457 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6458 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
6459 // CHECK19-NEXT:    store i32 [[I]], ptr [[I_ADDR]], align 4
6460 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6461 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
6462 // CHECK19-NEXT:    ret void
6463 //
6464 //
6465 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
6466 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
6467 // CHECK19-NEXT:  entry:
6468 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6469 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6470 // CHECK19-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 4
6471 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
6472 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6473 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i8, align 1
6474 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6475 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
6476 // CHECK19-NEXT:    [[I4:%.*]] = alloca i8, align 1
6477 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6478 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6479 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6480 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6481 // CHECK19-NEXT:    [[I6:%.*]] = alloca i8, align 1
6482 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6483 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6484 // CHECK19-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 4
6485 // CHECK19-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
6486 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4
6487 // CHECK19-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
6488 // CHECK19-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
6489 // CHECK19-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
6490 // CHECK19-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6491 // CHECK19-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
6492 // CHECK19-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
6493 // CHECK19-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
6494 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
6495 // CHECK19-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
6496 // CHECK19-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
6497 // CHECK19-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
6498 // CHECK19-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6499 // CHECK19-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
6500 // CHECK19-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6501 // CHECK19-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
6502 // CHECK19-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
6503 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
6504 // CHECK19:       omp.precond.then:
6505 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6506 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
6507 // CHECK19-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
6508 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6509 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6510 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6511 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
6512 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6513 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6514 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
6515 // CHECK19-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
6516 // CHECK19-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6517 // CHECK19:       cond.true:
6518 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
6519 // CHECK19-NEXT:    br label [[COND_END:%.*]]
6520 // CHECK19:       cond.false:
6521 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6522 // CHECK19-NEXT:    br label [[COND_END]]
6523 // CHECK19:       cond.end:
6524 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6525 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6526 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6527 // CHECK19-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
6528 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6529 // CHECK19:       omp.inner.for.cond:
6530 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
6531 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
6532 // CHECK19-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6533 // CHECK19-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6534 // CHECK19:       omp.inner.for.body:
6535 // CHECK19-NEXT:    [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]]
6536 // CHECK19-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
6537 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
6538 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
6539 // CHECK19-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
6540 // CHECK19-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
6541 // CHECK19-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP22]]
6542 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6543 // CHECK19:       omp.body.continue:
6544 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6545 // CHECK19:       omp.inner.for.inc:
6546 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
6547 // CHECK19-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
6548 // CHECK19-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
6549 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
6550 // CHECK19:       omp.inner.for.end:
6551 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6552 // CHECK19:       omp.loop.exit:
6553 // CHECK19-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6554 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
6555 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
6556 // CHECK19-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6557 // CHECK19-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
6558 // CHECK19-NEXT:    br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6559 // CHECK19:       .omp.final.then:
6560 // CHECK19-NEXT:    [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6561 // CHECK19-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
6562 // CHECK19-NEXT:    [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6563 // CHECK19-NEXT:    [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
6564 // CHECK19-NEXT:    [[SUB15:%.*]] = sub i32 10, [[CONV14]]
6565 // CHECK19-NEXT:    [[SUB16:%.*]] = sub i32 [[SUB15]], 1
6566 // CHECK19-NEXT:    [[ADD17:%.*]] = add i32 [[SUB16]], 1
6567 // CHECK19-NEXT:    [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
6568 // CHECK19-NEXT:    [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
6569 // CHECK19-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
6570 // CHECK19-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
6571 // CHECK19-NEXT:    store i8 [[CONV21]], ptr [[TMP0]], align 1
6572 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6573 // CHECK19:       .omp.final.done:
6574 // CHECK19-NEXT:    br label [[OMP_PRECOND_END]]
6575 // CHECK19:       omp.precond.end:
6576 // CHECK19-NEXT:    ret void
6577 //
6578 //
6579 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
6580 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
6581 // CHECK19-NEXT:  entry:
6582 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
6583 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6584 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
6585 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6586 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
6587 // CHECK19-NEXT:    ret void
6588 //
6589 //
6590 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
6591 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
6592 // CHECK19-NEXT:  entry:
6593 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6594 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6595 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
6596 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6597 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6598 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6599 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6600 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6601 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6602 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
6603 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6604 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6605 // CHECK19-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
6606 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
6607 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6608 // CHECK19-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
6609 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6610 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6611 // CHECK19-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
6612 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6613 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6614 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
6615 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
6616 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6617 // CHECK19:       omp.dispatch.cond:
6618 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6619 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
6620 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6621 // CHECK19:       cond.true:
6622 // CHECK19-NEXT:    br label [[COND_END:%.*]]
6623 // CHECK19:       cond.false:
6624 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6625 // CHECK19-NEXT:    br label [[COND_END]]
6626 // CHECK19:       cond.end:
6627 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6628 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6629 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6630 // CHECK19-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
6631 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6632 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6633 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6634 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6635 // CHECK19:       omp.dispatch.body:
6636 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6637 // CHECK19:       omp.inner.for.cond:
6638 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]
6639 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]
6640 // CHECK19-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6641 // CHECK19-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6642 // CHECK19:       omp.inner.for.body:
6643 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
6644 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6645 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6646 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]
6647 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6648 // CHECK19:       omp.body.continue:
6649 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6650 // CHECK19:       omp.inner.for.inc:
6651 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
6652 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
6653 // CHECK19-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
6654 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
6655 // CHECK19:       omp.inner.for.end:
6656 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
6657 // CHECK19:       omp.dispatch.inc:
6658 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6659 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6660 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
6661 // CHECK19-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
6662 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6663 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6664 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
6665 // CHECK19-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
6666 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
6667 // CHECK19:       omp.dispatch.end:
6668 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
6669 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6670 // CHECK19-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
6671 // CHECK19-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6672 // CHECK19:       .omp.final.then:
6673 // CHECK19-NEXT:    store i32 100, ptr [[I]], align 4
6674 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6675 // CHECK19:       .omp.final.done:
6676 // CHECK19-NEXT:    ret void
6677 //
6678 //
6679 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
6680 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
6681 // CHECK21-NEXT:  entry:
6682 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
6683 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
6684 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6685 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6686 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6687 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
6688 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
6689 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6690 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6691 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6692 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
6693 // CHECK21-NEXT:    ret void
6694 //
6695 //
6696 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
6697 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
6698 // CHECK21-NEXT:  entry:
6699 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6700 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6701 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
6702 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6703 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6704 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6705 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6706 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6707 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6708 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6709 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6710 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6711 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
6712 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6713 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6714 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
6715 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6716 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6717 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6718 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
6719 // CHECK21-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6720 // CHECK21-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6721 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
6722 // CHECK21-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8
6723 // CHECK21-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ]
6724 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6725 // CHECK21-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
6726 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6727 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6728 // CHECK21-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6729 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
6730 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6731 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6732 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
6733 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6734 // CHECK21:       cond.true:
6735 // CHECK21-NEXT:    br label [[COND_END:%.*]]
6736 // CHECK21:       cond.false:
6737 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6738 // CHECK21-NEXT:    br label [[COND_END]]
6739 // CHECK21:       cond.end:
6740 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
6741 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6742 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6743 // CHECK21-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
6744 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6745 // CHECK21:       omp.inner.for.cond:
6746 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
6747 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
6748 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
6749 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6750 // CHECK21:       omp.inner.for.body:
6751 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
6752 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
6753 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
6754 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
6755 // CHECK21-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP9]]
6756 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
6757 // CHECK21-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
6758 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
6759 // CHECK21-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
6760 // CHECK21-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP9]]
6761 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
6762 // CHECK21-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
6763 // CHECK21-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]]
6764 // CHECK21-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP9]]
6765 // CHECK21-NEXT:    [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
6766 // CHECK21-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP9]]
6767 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
6768 // CHECK21-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
6769 // CHECK21-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]]
6770 // CHECK21-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]]
6771 // CHECK21-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
6772 // CHECK21-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP9]]
6773 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
6774 // CHECK21-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
6775 // CHECK21-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]]
6776 // CHECK21-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP9]]
6777 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6778 // CHECK21:       omp.body.continue:
6779 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6780 // CHECK21:       omp.inner.for.inc:
6781 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
6782 // CHECK21-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
6783 // CHECK21-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
6784 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
6785 // CHECK21:       omp.inner.for.end:
6786 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6787 // CHECK21:       omp.loop.exit:
6788 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
6789 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6790 // CHECK21-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6791 // CHECK21-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6792 // CHECK21:       .omp.final.then:
6793 // CHECK21-NEXT:    store i32 32000001, ptr [[I]], align 4
6794 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6795 // CHECK21:       .omp.final.done:
6796 // CHECK21-NEXT:    ret void
6797 //
6798 //
6799 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
6800 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
6801 // CHECK21-NEXT:  entry:
6802 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
6803 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
6804 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6805 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6806 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6807 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
6808 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
6809 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6810 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6811 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6812 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
6813 // CHECK21-NEXT:    ret void
6814 //
6815 //
6816 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
6817 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
6818 // CHECK21-NEXT:  entry:
6819 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6820 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6821 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
6822 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6823 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6824 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6825 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6826 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6827 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6828 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6829 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6830 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6831 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
6832 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6833 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6834 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
6835 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6836 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6837 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6838 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
6839 // CHECK21-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6840 // CHECK21-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6841 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
6842 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6843 // CHECK21-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
6844 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6845 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6846 // CHECK21-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6847 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
6848 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6849 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6850 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
6851 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6852 // CHECK21:       cond.true:
6853 // CHECK21-NEXT:    br label [[COND_END:%.*]]
6854 // CHECK21:       cond.false:
6855 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6856 // CHECK21-NEXT:    br label [[COND_END]]
6857 // CHECK21:       cond.end:
6858 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6859 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6860 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6861 // CHECK21-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
6862 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6863 // CHECK21:       omp.inner.for.cond:
6864 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6865 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6866 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6867 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6868 // CHECK21:       omp.inner.for.body:
6869 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6870 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
6871 // CHECK21-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
6872 // CHECK21-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
6873 // CHECK21-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal !16
6874 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
6875 // CHECK21-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
6876 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
6877 // CHECK21-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
6878 // CHECK21-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
6879 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
6880 // CHECK21-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
6881 // CHECK21-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
6882 // CHECK21-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
6883 // CHECK21-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
6884 // CHECK21-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
6885 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
6886 // CHECK21-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
6887 // CHECK21-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
6888 // CHECK21-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
6889 // CHECK21-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
6890 // CHECK21-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal !16
6891 // CHECK21-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
6892 // CHECK21-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
6893 // CHECK21-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
6894 // CHECK21-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
6895 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6896 // CHECK21:       omp.body.continue:
6897 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6898 // CHECK21:       omp.inner.for.inc:
6899 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6900 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
6901 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
6902 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
6903 // CHECK21:       omp.inner.for.end:
6904 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6905 // CHECK21:       omp.loop.exit:
6906 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
6907 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6908 // CHECK21-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
6909 // CHECK21-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6910 // CHECK21:       .omp.final.then:
6911 // CHECK21-NEXT:    store i32 32, ptr [[I]], align 4
6912 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6913 // CHECK21:       .omp.final.done:
6914 // CHECK21-NEXT:    ret void
6915 //
6916 //
6917 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
6918 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
6919 // CHECK21-NEXT:  entry:
6920 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
6921 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
6922 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6923 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6924 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6925 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
6926 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
6927 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6928 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6929 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6930 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
6931 // CHECK21-NEXT:    ret void
6932 //
6933 //
6934 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
6935 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
6936 // CHECK21-NEXT:  entry:
6937 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6938 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6939 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
6940 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6941 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6942 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6943 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6944 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6945 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6946 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6947 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6948 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6949 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
6950 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6951 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6952 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
6953 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6954 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6955 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6956 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
6957 // CHECK21-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6958 // CHECK21-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6959 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
6960 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6961 // CHECK21-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
6962 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6963 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6964 // CHECK21-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6965 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
6966 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
6967 // CHECK21-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6968 // CHECK21:       omp.dispatch.cond:
6969 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6970 // CHECK21-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
6971 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6972 // CHECK21:       cond.true:
6973 // CHECK21-NEXT:    br label [[COND_END:%.*]]
6974 // CHECK21:       cond.false:
6975 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6976 // CHECK21-NEXT:    br label [[COND_END]]
6977 // CHECK21:       cond.end:
6978 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6979 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6980 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6981 // CHECK21-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
6982 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6983 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6984 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
6985 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6986 // CHECK21:       omp.dispatch.body:
6987 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6988 // CHECK21:       omp.inner.for.cond:
6989 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
6990 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
6991 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
6992 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6993 // CHECK21:       omp.inner.for.body:
6994 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
6995 // CHECK21-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
6996 // CHECK21-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
6997 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
6998 // CHECK21-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP19]]
6999 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
7000 // CHECK21-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
7001 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
7002 // CHECK21-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]]
7003 // CHECK21-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP19]]
7004 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
7005 // CHECK21-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
7006 // CHECK21-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
7007 // CHECK21-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP19]]
7008 // CHECK21-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
7009 // CHECK21-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP19]]
7010 // CHECK21-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
7011 // CHECK21-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
7012 // CHECK21-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
7013 // CHECK21-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]]
7014 // CHECK21-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
7015 // CHECK21-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP19]]
7016 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
7017 // CHECK21-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
7018 // CHECK21-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
7019 // CHECK21-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP19]]
7020 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7021 // CHECK21:       omp.body.continue:
7022 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7023 // CHECK21:       omp.inner.for.inc:
7024 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
7025 // CHECK21-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
7026 // CHECK21-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
7027 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
7028 // CHECK21:       omp.inner.for.end:
7029 // CHECK21-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7030 // CHECK21:       omp.dispatch.inc:
7031 // CHECK21-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7032 // CHECK21-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7033 // CHECK21-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
7034 // CHECK21-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
7035 // CHECK21-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7036 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7037 // CHECK21-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
7038 // CHECK21-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
7039 // CHECK21-NEXT:    br label [[OMP_DISPATCH_COND]]
7040 // CHECK21:       omp.dispatch.end:
7041 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
7042 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7043 // CHECK21-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
7044 // CHECK21-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7045 // CHECK21:       .omp.final.then:
7046 // CHECK21-NEXT:    store i32 -2147483522, ptr [[I]], align 4
7047 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7048 // CHECK21:       .omp.final.done:
7049 // CHECK21-NEXT:    ret void
7050 //
7051 //
7052 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
7053 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
7054 // CHECK21-NEXT:  entry:
7055 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
7056 // CHECK21-NEXT:    [[I_ADDR:%.*]] = alloca i64, align 8
7057 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7058 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
7059 // CHECK21-NEXT:    store i64 [[I]], ptr [[I_ADDR]], align 8
7060 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
7061 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
7062 // CHECK21-NEXT:    ret void
7063 //
7064 //
7065 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
7066 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
7067 // CHECK21-NEXT:  entry:
7068 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
7069 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
7070 // CHECK21-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
7071 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
7072 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7073 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i8, align 1
7074 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7075 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7076 // CHECK21-NEXT:    [[I4:%.*]] = alloca i8, align 1
7077 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7078 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7079 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7080 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7081 // CHECK21-NEXT:    [[I6:%.*]] = alloca i8, align 1
7082 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
7083 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
7084 // CHECK21-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
7085 // CHECK21-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
7086 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
7087 // CHECK21-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
7088 // CHECK21-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
7089 // CHECK21-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
7090 // CHECK21-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7091 // CHECK21-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
7092 // CHECK21-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
7093 // CHECK21-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
7094 // CHECK21-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
7095 // CHECK21-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
7096 // CHECK21-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7097 // CHECK21-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
7098 // CHECK21-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7099 // CHECK21-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
7100 // CHECK21-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7101 // CHECK21-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
7102 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7103 // CHECK21-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7104 // CHECK21:       omp.precond.then:
7105 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7106 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7107 // CHECK21-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
7108 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7109 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7110 // CHECK21-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
7111 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
7112 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7113 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7114 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7115 // CHECK21-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
7116 // CHECK21-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7117 // CHECK21:       cond.true:
7118 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7119 // CHECK21-NEXT:    br label [[COND_END:%.*]]
7120 // CHECK21:       cond.false:
7121 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7122 // CHECK21-NEXT:    br label [[COND_END]]
7123 // CHECK21:       cond.end:
7124 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7125 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7126 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7127 // CHECK21-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
7128 // CHECK21-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1
7129 // CHECK21-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
7130 // CHECK21-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7131 // CHECK21:       omp_if.then:
7132 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7133 // CHECK21:       omp.inner.for.cond:
7134 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
7135 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
7136 // CHECK21-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7137 // CHECK21-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7138 // CHECK21:       omp.inner.for.body:
7139 // CHECK21-NEXT:    [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]]
7140 // CHECK21-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
7141 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
7142 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7143 // CHECK21-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7144 // CHECK21-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7145 // CHECK21-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !16, !llvm.access.group [[ACC_GRP22]]
7146 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7147 // CHECK21:       omp.body.continue:
7148 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7149 // CHECK21:       omp.inner.for.inc:
7150 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
7151 // CHECK21-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
7152 // CHECK21-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
7153 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
7154 // CHECK21:       omp.inner.for.end:
7155 // CHECK21-NEXT:    br label [[OMP_IF_END:%.*]]
7156 // CHECK21:       omp_if.else:
7157 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND13:%.*]]
7158 // CHECK21:       omp.inner.for.cond13:
7159 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7160 // CHECK21-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7161 // CHECK21-NEXT:    [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
7162 // CHECK21-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
7163 // CHECK21:       omp.inner.for.body15:
7164 // CHECK21-NEXT:    [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7165 // CHECK21-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
7166 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7167 // CHECK21-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
7168 // CHECK21-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
7169 // CHECK21-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
7170 // CHECK21-NEXT:    store i8 [[CONV19]], ptr [[I6]], align 1
7171 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE20:%.*]]
7172 // CHECK21:       omp.body.continue20:
7173 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC21:%.*]]
7174 // CHECK21:       omp.inner.for.inc21:
7175 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7176 // CHECK21-NEXT:    [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
7177 // CHECK21-NEXT:    store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4
7178 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
7179 // CHECK21:       omp.inner.for.end23:
7180 // CHECK21-NEXT:    br label [[OMP_IF_END]]
7181 // CHECK21:       omp_if.end:
7182 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7183 // CHECK21:       omp.loop.exit:
7184 // CHECK21-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
7185 // CHECK21-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
7186 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
7187 // CHECK21-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7188 // CHECK21-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7189 // CHECK21-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7190 // CHECK21:       .omp.final.then:
7191 // CHECK21-NEXT:    [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7192 // CHECK21-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
7193 // CHECK21-NEXT:    [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7194 // CHECK21-NEXT:    [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
7195 // CHECK21-NEXT:    [[SUB26:%.*]] = sub i32 10, [[CONV25]]
7196 // CHECK21-NEXT:    [[SUB27:%.*]] = sub i32 [[SUB26]], 1
7197 // CHECK21-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
7198 // CHECK21-NEXT:    [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
7199 // CHECK21-NEXT:    [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
7200 // CHECK21-NEXT:    [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
7201 // CHECK21-NEXT:    [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
7202 // CHECK21-NEXT:    store i8 [[CONV32]], ptr [[TMP0]], align 1
7203 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7204 // CHECK21:       .omp.final.done:
7205 // CHECK21-NEXT:    br label [[OMP_PRECOND_END]]
7206 // CHECK21:       omp.precond.end:
7207 // CHECK21-NEXT:    ret void
7208 //
7209 //
7210 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
7211 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
7212 // CHECK21-NEXT:  entry:
7213 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
7214 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7215 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
7216 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
7217 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
7218 // CHECK21-NEXT:    ret void
7219 //
7220 //
7221 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
7222 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
7223 // CHECK21-NEXT:  entry:
7224 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
7225 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
7226 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
7227 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7228 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7229 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7230 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7231 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7232 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7233 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
7234 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
7235 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
7236 // CHECK21-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
7237 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
7238 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7239 // CHECK21-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
7240 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7241 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7242 // CHECK21-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
7243 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7244 // CHECK21-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
7245 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
7246 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
7247 // CHECK21-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7248 // CHECK21:       omp.dispatch.cond:
7249 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7250 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
7251 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7252 // CHECK21:       cond.true:
7253 // CHECK21-NEXT:    br label [[COND_END:%.*]]
7254 // CHECK21:       cond.false:
7255 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7256 // CHECK21-NEXT:    br label [[COND_END]]
7257 // CHECK21:       cond.end:
7258 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7259 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7260 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7261 // CHECK21-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
7262 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7263 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7264 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7265 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7266 // CHECK21:       omp.dispatch.body:
7267 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7268 // CHECK21:       omp.inner.for.cond:
7269 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]
7270 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]
7271 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7272 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7273 // CHECK21:       omp.inner.for.body:
7274 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
7275 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7276 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7277 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]]
7278 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7279 // CHECK21:       omp.body.continue:
7280 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7281 // CHECK21:       omp.inner.for.inc:
7282 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
7283 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7284 // CHECK21-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
7285 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
7286 // CHECK21:       omp.inner.for.end:
7287 // CHECK21-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7288 // CHECK21:       omp.dispatch.inc:
7289 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7290 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7291 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
7292 // CHECK21-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
7293 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7294 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7295 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
7296 // CHECK21-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
7297 // CHECK21-NEXT:    br label [[OMP_DISPATCH_COND]]
7298 // CHECK21:       omp.dispatch.end:
7299 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
7300 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7301 // CHECK21-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
7302 // CHECK21-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7303 // CHECK21:       .omp.final.then:
7304 // CHECK21-NEXT:    store i32 100, ptr [[I]], align 4
7305 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7306 // CHECK21:       .omp.final.done:
7307 // CHECK21-NEXT:    ret void
7308 //
7309 //
7310 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
7311 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
7312 // CHECK23-NEXT:  entry:
7313 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
7314 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7315 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7316 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7317 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7318 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
7319 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7320 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7321 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7322 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7323 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
7324 // CHECK23-NEXT:    ret void
7325 //
7326 //
7327 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined
7328 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
7329 // CHECK23-NEXT:  entry:
7330 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7331 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7332 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7333 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7334 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7335 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7336 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7337 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7338 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7339 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7340 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7341 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7342 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
7343 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7344 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7345 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7346 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7347 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7348 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7349 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
7350 // CHECK23-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7351 // CHECK23-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7352 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
7353 // CHECK23-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4
7354 // CHECK23-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ]
7355 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7356 // CHECK23-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
7357 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7358 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7359 // CHECK23-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7360 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
7361 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7362 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7363 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
7364 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7365 // CHECK23:       cond.true:
7366 // CHECK23-NEXT:    br label [[COND_END:%.*]]
7367 // CHECK23:       cond.false:
7368 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7369 // CHECK23-NEXT:    br label [[COND_END]]
7370 // CHECK23:       cond.end:
7371 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
7372 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7373 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7374 // CHECK23-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
7375 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7376 // CHECK23:       omp.inner.for.cond:
7377 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
7378 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
7379 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
7380 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7381 // CHECK23:       omp.inner.for.body:
7382 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
7383 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
7384 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
7385 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
7386 // CHECK23-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP10]]
7387 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
7388 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]]
7389 // CHECK23-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
7390 // CHECK23-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP10]]
7391 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
7392 // CHECK23-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]]
7393 // CHECK23-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]]
7394 // CHECK23-NEXT:    [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
7395 // CHECK23-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP10]]
7396 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
7397 // CHECK23-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]]
7398 // CHECK23-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]]
7399 // CHECK23-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
7400 // CHECK23-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP10]]
7401 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
7402 // CHECK23-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]]
7403 // CHECK23-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]]
7404 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7405 // CHECK23:       omp.body.continue:
7406 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7407 // CHECK23:       omp.inner.for.inc:
7408 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
7409 // CHECK23-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
7410 // CHECK23-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
7411 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
7412 // CHECK23:       omp.inner.for.end:
7413 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7414 // CHECK23:       omp.loop.exit:
7415 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
7416 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7417 // CHECK23-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
7418 // CHECK23-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7419 // CHECK23:       .omp.final.then:
7420 // CHECK23-NEXT:    store i32 32000001, ptr [[I]], align 4
7421 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7422 // CHECK23:       .omp.final.done:
7423 // CHECK23-NEXT:    ret void
7424 //
7425 //
7426 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
7427 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
7428 // CHECK23-NEXT:  entry:
7429 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
7430 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7431 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7432 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7433 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7434 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
7435 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7436 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7437 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7438 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7439 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
7440 // CHECK23-NEXT:    ret void
7441 //
7442 //
7443 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined
7444 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
7445 // CHECK23-NEXT:  entry:
7446 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7447 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7448 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7449 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7450 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7451 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7452 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7453 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7454 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7455 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7456 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7457 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7458 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
7459 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7460 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7461 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7462 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7463 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7464 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7465 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
7466 // CHECK23-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7467 // CHECK23-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7468 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
7469 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7470 // CHECK23-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
7471 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7472 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7473 // CHECK23-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7474 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
7475 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7476 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7477 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
7478 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7479 // CHECK23:       cond.true:
7480 // CHECK23-NEXT:    br label [[COND_END:%.*]]
7481 // CHECK23:       cond.false:
7482 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7483 // CHECK23-NEXT:    br label [[COND_END]]
7484 // CHECK23:       cond.end:
7485 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
7486 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7487 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7488 // CHECK23-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
7489 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7490 // CHECK23:       omp.inner.for.cond:
7491 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7492 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7493 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7494 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7495 // CHECK23:       omp.inner.for.body:
7496 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7497 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
7498 // CHECK23-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
7499 // CHECK23-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
7500 // CHECK23-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal !17
7501 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
7502 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]]
7503 // CHECK23-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
7504 // CHECK23-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4
7505 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
7506 // CHECK23-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]]
7507 // CHECK23-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
7508 // CHECK23-NEXT:    [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
7509 // CHECK23-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4
7510 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
7511 // CHECK23-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]]
7512 // CHECK23-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
7513 // CHECK23-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
7514 // CHECK23-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal !17
7515 // CHECK23-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
7516 // CHECK23-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]]
7517 // CHECK23-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
7518 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7519 // CHECK23:       omp.body.continue:
7520 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7521 // CHECK23:       omp.inner.for.inc:
7522 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7523 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
7524 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
7525 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
7526 // CHECK23:       omp.inner.for.end:
7527 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7528 // CHECK23:       omp.loop.exit:
7529 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
7530 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7531 // CHECK23-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
7532 // CHECK23-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7533 // CHECK23:       .omp.final.then:
7534 // CHECK23-NEXT:    store i32 32, ptr [[I]], align 4
7535 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7536 // CHECK23:       .omp.final.done:
7537 // CHECK23-NEXT:    ret void
7538 //
7539 //
7540 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
7541 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
7542 // CHECK23-NEXT:  entry:
7543 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
7544 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7545 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7546 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7547 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7548 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
7549 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7550 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7551 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7552 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7553 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
7554 // CHECK23-NEXT:    ret void
7555 //
7556 //
7557 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined
7558 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
7559 // CHECK23-NEXT:  entry:
7560 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7561 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7562 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7563 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7564 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7565 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7566 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7567 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7568 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7569 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7570 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7571 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7572 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
7573 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7574 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7575 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7576 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7577 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7578 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7579 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
7580 // CHECK23-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7581 // CHECK23-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7582 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
7583 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7584 // CHECK23-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
7585 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7586 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7587 // CHECK23-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7588 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
7589 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
7590 // CHECK23-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7591 // CHECK23:       omp.dispatch.cond:
7592 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7593 // CHECK23-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
7594 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7595 // CHECK23:       cond.true:
7596 // CHECK23-NEXT:    br label [[COND_END:%.*]]
7597 // CHECK23:       cond.false:
7598 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7599 // CHECK23-NEXT:    br label [[COND_END]]
7600 // CHECK23:       cond.end:
7601 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
7602 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7603 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7604 // CHECK23-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
7605 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7606 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7607 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
7608 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7609 // CHECK23:       omp.dispatch.body:
7610 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7611 // CHECK23:       omp.inner.for.cond:
7612 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
7613 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]
7614 // CHECK23-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
7615 // CHECK23-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7616 // CHECK23:       omp.inner.for.body:
7617 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
7618 // CHECK23-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
7619 // CHECK23-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
7620 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
7621 // CHECK23-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP20]]
7622 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
7623 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]]
7624 // CHECK23-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]]
7625 // CHECK23-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP20]]
7626 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
7627 // CHECK23-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]]
7628 // CHECK23-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP20]]
7629 // CHECK23-NEXT:    [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
7630 // CHECK23-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP20]]
7631 // CHECK23-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
7632 // CHECK23-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]]
7633 // CHECK23-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP20]]
7634 // CHECK23-NEXT:    [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
7635 // CHECK23-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP20]]
7636 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
7637 // CHECK23-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]]
7638 // CHECK23-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP20]]
7639 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7640 // CHECK23:       omp.body.continue:
7641 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7642 // CHECK23:       omp.inner.for.inc:
7643 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
7644 // CHECK23-NEXT:    [[ADD8:%.*]] = add i32 [[TMP25]], 1
7645 // CHECK23-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
7646 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
7647 // CHECK23:       omp.inner.for.end:
7648 // CHECK23-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7649 // CHECK23:       omp.dispatch.inc:
7650 // CHECK23-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7651 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7652 // CHECK23-NEXT:    [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
7653 // CHECK23-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4
7654 // CHECK23-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7655 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7656 // CHECK23-NEXT:    [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
7657 // CHECK23-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4
7658 // CHECK23-NEXT:    br label [[OMP_DISPATCH_COND]]
7659 // CHECK23:       omp.dispatch.end:
7660 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
7661 // CHECK23-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7662 // CHECK23-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
7663 // CHECK23-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7664 // CHECK23:       .omp.final.then:
7665 // CHECK23-NEXT:    store i32 -2147483522, ptr [[I]], align 4
7666 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7667 // CHECK23:       .omp.final.done:
7668 // CHECK23-NEXT:    ret void
7669 //
7670 //
7671 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
7672 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
7673 // CHECK23-NEXT:  entry:
7674 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
7675 // CHECK23-NEXT:    [[I_ADDR:%.*]] = alloca i32, align 4
7676 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7677 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
7678 // CHECK23-NEXT:    store i32 [[I]], ptr [[I_ADDR]], align 4
7679 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7680 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
7681 // CHECK23-NEXT:    ret void
7682 //
7683 //
7684 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined
7685 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
7686 // CHECK23-NEXT:  entry:
7687 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7688 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7689 // CHECK23-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 4
7690 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
7691 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7692 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i8, align 1
7693 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7694 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7695 // CHECK23-NEXT:    [[I4:%.*]] = alloca i8, align 1
7696 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7697 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7698 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7699 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7700 // CHECK23-NEXT:    [[I6:%.*]] = alloca i8, align 1
7701 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7702 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7703 // CHECK23-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 4
7704 // CHECK23-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
7705 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4
7706 // CHECK23-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
7707 // CHECK23-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
7708 // CHECK23-NEXT:    store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1
7709 // CHECK23-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7710 // CHECK23-NEXT:    [[CONV:%.*]] = sext i8 [[TMP3]] to i32
7711 // CHECK23-NEXT:    [[SUB:%.*]] = sub i32 10, [[CONV]]
7712 // CHECK23-NEXT:    [[SUB2:%.*]] = sub i32 [[SUB]], 1
7713 // CHECK23-NEXT:    [[ADD:%.*]] = add i32 [[SUB2]], 1
7714 // CHECK23-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
7715 // CHECK23-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7716 // CHECK23-NEXT:    store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4
7717 // CHECK23-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7718 // CHECK23-NEXT:    store i8 [[TMP4]], ptr [[I4]], align 1
7719 // CHECK23-NEXT:    [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7720 // CHECK23-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
7721 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7722 // CHECK23-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7723 // CHECK23:       omp.precond.then:
7724 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7725 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7726 // CHECK23-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
7727 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7728 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7729 // CHECK23-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7730 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
7731 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7732 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7733 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7734 // CHECK23-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
7735 // CHECK23-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7736 // CHECK23:       cond.true:
7737 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7738 // CHECK23-NEXT:    br label [[COND_END:%.*]]
7739 // CHECK23:       cond.false:
7740 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7741 // CHECK23-NEXT:    br label [[COND_END]]
7742 // CHECK23:       cond.end:
7743 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7744 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7745 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7746 // CHECK23-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
7747 // CHECK23-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1
7748 // CHECK23-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
7749 // CHECK23-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7750 // CHECK23:       omp_if.then:
7751 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7752 // CHECK23:       omp.inner.for.cond:
7753 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]
7754 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
7755 // CHECK23-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7756 // CHECK23-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7757 // CHECK23:       omp.inner.for.body:
7758 // CHECK23-NEXT:    [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP23]]
7759 // CHECK23-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
7760 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
7761 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7762 // CHECK23-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7763 // CHECK23-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7764 // CHECK23-NEXT:    store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !17, !llvm.access.group [[ACC_GRP23]]
7765 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7766 // CHECK23:       omp.body.continue:
7767 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7768 // CHECK23:       omp.inner.for.inc:
7769 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
7770 // CHECK23-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
7771 // CHECK23-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
7772 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
7773 // CHECK23:       omp.inner.for.end:
7774 // CHECK23-NEXT:    br label [[OMP_IF_END:%.*]]
7775 // CHECK23:       omp_if.else:
7776 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND13:%.*]]
7777 // CHECK23:       omp.inner.for.cond13:
7778 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7779 // CHECK23-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7780 // CHECK23-NEXT:    [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
7781 // CHECK23-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
7782 // CHECK23:       omp.inner.for.body15:
7783 // CHECK23-NEXT:    [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7784 // CHECK23-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
7785 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7786 // CHECK23-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
7787 // CHECK23-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
7788 // CHECK23-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
7789 // CHECK23-NEXT:    store i8 [[CONV19]], ptr [[I6]], align 1
7790 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE20:%.*]]
7791 // CHECK23:       omp.body.continue20:
7792 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC21:%.*]]
7793 // CHECK23:       omp.inner.for.inc21:
7794 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7795 // CHECK23-NEXT:    [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
7796 // CHECK23-NEXT:    store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4
7797 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]]
7798 // CHECK23:       omp.inner.for.end23:
7799 // CHECK23-NEXT:    br label [[OMP_IF_END]]
7800 // CHECK23:       omp_if.end:
7801 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7802 // CHECK23:       omp.loop.exit:
7803 // CHECK23-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7804 // CHECK23-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
7805 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
7806 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7807 // CHECK23-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7808 // CHECK23-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7809 // CHECK23:       .omp.final.then:
7810 // CHECK23-NEXT:    [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7811 // CHECK23-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
7812 // CHECK23-NEXT:    [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
7813 // CHECK23-NEXT:    [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
7814 // CHECK23-NEXT:    [[SUB26:%.*]] = sub i32 10, [[CONV25]]
7815 // CHECK23-NEXT:    [[SUB27:%.*]] = sub i32 [[SUB26]], 1
7816 // CHECK23-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
7817 // CHECK23-NEXT:    [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
7818 // CHECK23-NEXT:    [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
7819 // CHECK23-NEXT:    [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
7820 // CHECK23-NEXT:    [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
7821 // CHECK23-NEXT:    store i8 [[CONV32]], ptr [[TMP0]], align 1
7822 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7823 // CHECK23:       .omp.final.done:
7824 // CHECK23-NEXT:    br label [[OMP_PRECOND_END]]
7825 // CHECK23:       omp.precond.end:
7826 // CHECK23-NEXT:    ret void
7827 //
7828 //
7829 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
7830 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
7831 // CHECK23-NEXT:  entry:
7832 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
7833 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7834 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
7835 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7836 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
7837 // CHECK23-NEXT:    ret void
7838 //
7839 //
7840 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined
7841 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
7842 // CHECK23-NEXT:  entry:
7843 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7844 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7845 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
7846 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7847 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7848 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7849 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7850 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7851 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7852 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
7853 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7854 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7855 // CHECK23-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
7856 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
7857 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7858 // CHECK23-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
7859 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7860 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7861 // CHECK23-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
7862 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7863 // CHECK23-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7864 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
7865 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
7866 // CHECK23-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7867 // CHECK23:       omp.dispatch.cond:
7868 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7869 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
7870 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7871 // CHECK23:       cond.true:
7872 // CHECK23-NEXT:    br label [[COND_END:%.*]]
7873 // CHECK23:       cond.false:
7874 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7875 // CHECK23-NEXT:    br label [[COND_END]]
7876 // CHECK23:       cond.end:
7877 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7878 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7879 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7880 // CHECK23-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
7881 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7882 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7883 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7884 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7885 // CHECK23:       omp.dispatch.body:
7886 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7887 // CHECK23:       omp.inner.for.cond:
7888 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]
7889 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]
7890 // CHECK23-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7891 // CHECK23-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7892 // CHECK23:       omp.inner.for.body:
7893 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
7894 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7895 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7896 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]
7897 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7898 // CHECK23:       omp.body.continue:
7899 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7900 // CHECK23:       omp.inner.for.inc:
7901 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
7902 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7903 // CHECK23-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
7904 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
7905 // CHECK23:       omp.inner.for.end:
7906 // CHECK23-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7907 // CHECK23:       omp.dispatch.inc:
7908 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7909 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7910 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
7911 // CHECK23-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
7912 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7913 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7914 // CHECK23-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
7915 // CHECK23-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
7916 // CHECK23-NEXT:    br label [[OMP_DISPATCH_COND]]
7917 // CHECK23:       omp.dispatch.end:
7918 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
7919 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7920 // CHECK23-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
7921 // CHECK23-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7922 // CHECK23:       .omp.final.then:
7923 // CHECK23-NEXT:    store i32 100, ptr [[I]], align 4
7924 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7925 // CHECK23:       .omp.final.done:
7926 // CHECK23-NEXT:    ret void
7927 //