clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1  -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
  19 // RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11
  20 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  21 // RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11
  22
  23 // RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13
  24 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  25 // RUN: %clang_cc1  -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13
  26 // RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15
  27 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  28 // RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15
  29 // expected-no-diagnostics
  30 #ifndef HEADER
  31 #define HEADER
  32
  33 template <class T>
  34 struct S {
  35   T f;
  36   S(T a) : f(a) {}
  37   S() : f() {}
  38   operator T() { return T(); }
  39   ~S() {}
  40 };
  41
  42 template <typename T>
  43 T tmain() {
  44   S<T> test;
  45   T t_var = T();
  46   T vec[] = {1, 2};
  47   S<T> s_arr[] = {1, 2};
  48   S<T> &var = test;
  49   #pragma omp target
  50   #pragma omp teams
  51 #pragma omp distribute simd firstprivate(t_var, vec, s_arr, s_arr, var, var)
  52   for (int i = 0; i < 2; ++i) {
  53     vec[i] = t_var;
  54     s_arr[i] = var;
  55   }
  56   return T();
  57 }
  58
  59 int main() {
  60   static int svar;
  61   volatile double g;
  62   volatile double &g1 = g;
  63
  64   #ifdef LAMBDA
  65   [&]() {
  66     static float sfvar;
  67
  68     #pragma omp target
  69     #pragma omp teams
  70 #pragma omp distribute simd firstprivate(g, g1, svar, sfvar)
  71     for (int i = 0; i < 2; ++i) {
  72       // Private alloca's for conversion
  73
  74       // Actual private variables to be used in the body (tmp is used for the reference type)
  75
  76       // Store input parameter addresses into private alloca's for conversion
  77
  78
  79
  80       g += 1;
  81       g1 += 1;
  82       svar += 3;
  83       sfvar += 4.0;
  84
  85       // call inner lambda (use refs to private alloca's)
  86       [&]() {
  87         g += 2;
  88         g1 += 2;
  89         svar += 4;
  90         sfvar += 8.0;
  91
  92
  93
  94       }();
  95     }
  96   }();
  97   return 0;
  98   #else
  99   S<float> test;
 100   int t_var = 0;
 101   int vec[] = {1, 2};
 102   S<float> s_arr[] = {1, 2};
 103   S<float> &var = test;
 104
 105   #pragma omp target
 106   #pragma omp teams
 107   #pragma omp distribute simd firstprivate(t_var, vec, s_arr, s_arr, var, var, svar)
 108   for (int i = 0; i < 2; ++i) {
 109     vec[i] = t_var;
 110     s_arr[i] = var;
 111   }
 112   return tmain<int>();
 113   #endif
 114 }
 115
 116
 117
 118
 119 // discard omp loop variables
 120
 121
 122
 123 // init t_var
 124
 125 // init vec
 126
 127 // init s_arr
 128
 129
 130 // init var
 131
 132 // init svar
 133
 134
 135
 136 // Template
 137
 138
 139
 140 // discard omp loop variables
 141
 142
 143
 144 // init t_var
 145
 146 // init vec
 147
 148 // init s_arr
 149
 150
 151 // init var
 152
 153
 154
 155 #endif
 156 // CHECK1-LABEL: define {{[^@]+}}@main
 157 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 158 // CHECK1-NEXT:  entry:
 159 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 160 // CHECK1-NEXT:    [[G:%.*]] = alloca double, align 8
 161 // CHECK1-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 162 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
 163 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 164 // CHECK1-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 165 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 166 // CHECK1-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8
 167 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 168 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8
 169 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8
 170 // CHECK1-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
 171 // CHECK1-NEXT:    ret i32 0
 172 //
 173 //
 174 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68
 175 // CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {
 176 // CHECK1-NEXT:  entry:
 177 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
 178 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
 179 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 180 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8
 181 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 182 // CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
 183 // CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
 184 // CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 185 // CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 186 // CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
 187 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
 188 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])
 189 // CHECK1-NEXT:    ret void
 190 //
 191 //
 192 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined
 193 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {
 194 // CHECK1-NEXT:  entry:
 195 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 196 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 197 // CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 8
 198 // CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 8
 199 // CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 8
 200 // CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca ptr, align 8
 201 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 202 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 203 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 204 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 205 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 206 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 207 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 208 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 209 // CHECK1-NEXT:    [[G3:%.*]] = alloca double, align 8
 210 // CHECK1-NEXT:    [[G14:%.*]] = alloca double, align 8
 211 // CHECK1-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 8
 212 // CHECK1-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4
 213 // CHECK1-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4
 214 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 215 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
 216 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 217 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 218 // CHECK1-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 8
 219 // CHECK1-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 8
 220 // CHECK1-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8
 221 // CHECK1-NEXT:    store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
 222 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
 223 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8
 224 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8
 225 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8
 226 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 8
 227 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
 228 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 8
 229 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 230 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 231 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 232 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 233 // CHECK1-NEXT:    [[TMP5:%.*]] = load volatile double, ptr [[TMP0]], align 8
 234 // CHECK1-NEXT:    store double [[TMP5]], ptr [[G3]], align 8
 235 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8
 236 // CHECK1-NEXT:    [[TMP7:%.*]] = load volatile double, ptr [[TMP6]], align 8
 237 // CHECK1-NEXT:    store double [[TMP7]], ptr [[G14]], align 8
 238 // CHECK1-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 8
 239 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4
 240 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[SVAR6]], align 4
 241 // CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4
 242 // CHECK1-NEXT:    store float [[TMP9]], ptr [[SFVAR7]], align 4
 243 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 244 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 245 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 246 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 247 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
 248 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 249 // CHECK1:       cond.true:
 250 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 251 // CHECK1:       cond.false:
 252 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 253 // CHECK1-NEXT:    br label [[COND_END]]
 254 // CHECK1:       cond.end:
 255 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
 256 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 257 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 258 // CHECK1-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
 259 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 260 // CHECK1:       omp.inner.for.cond:
 261 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
 262 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
 263 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
 264 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 265 // CHECK1:       omp.inner.for.body:
 266 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 267 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
 268 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 269 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
 270 // CHECK1-NEXT:    [[TMP18:%.*]] = load double, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP4]]
 271 // CHECK1-NEXT:    [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00
 272 // CHECK1-NEXT:    store double [[ADD9]], ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP4]]
 273 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP4]]
 274 // CHECK1-NEXT:    [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 8, !llvm.access.group [[ACC_GRP4]]
 275 // CHECK1-NEXT:    [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00
 276 // CHECK1-NEXT:    store volatile double [[ADD10]], ptr [[TMP19]], align 8, !llvm.access.group [[ACC_GRP4]]
 277 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP4]]
 278 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3
 279 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP4]]
 280 // CHECK1-NEXT:    [[TMP22:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP4]]
 281 // CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP22]] to double
 282 // CHECK1-NEXT:    [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00
 283 // CHECK1-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
 284 // CHECK1-NEXT:    store float [[CONV13]], ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP4]]
 285 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 286 // CHECK1-NEXT:    store ptr [[G3]], ptr [[TMP23]], align 8, !llvm.access.group [[ACC_GRP4]]
 287 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
 288 // CHECK1-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP4]]
 289 // CHECK1-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP4]]
 290 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
 291 // CHECK1-NEXT:    store ptr [[SVAR6]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP4]]
 292 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
 293 // CHECK1-NEXT:    store ptr [[SFVAR7]], ptr [[TMP27]], align 8, !llvm.access.group [[ACC_GRP4]]
 294 // CHECK1-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]]
 295 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 296 // CHECK1:       omp.body.continue:
 297 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 298 // CHECK1:       omp.inner.for.inc:
 299 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 300 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1
 301 // CHECK1-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 302 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
 303 // CHECK1:       omp.inner.for.end:
 304 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 305 // CHECK1:       omp.loop.exit:
 306 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])
 307 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 308 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
 309 // CHECK1-NEXT:    br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 310 // CHECK1:       .omp.final.then:
 311 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 312 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 313 // CHECK1:       .omp.final.done:
 314 // CHECK1-NEXT:    ret void
 315 //
 316 //
 317 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 318 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
 319 // CHECK1-NEXT:  entry:
 320 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
 321 // CHECK1-NEXT:    ret void
 322 //
 323 //
 324 // CHECK3-LABEL: define {{[^@]+}}@main
 325 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 326 // CHECK3-NEXT:  entry:
 327 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 328 // CHECK3-NEXT:    [[G:%.*]] = alloca double, align 8
 329 // CHECK3-NEXT:    [[G1:%.*]] = alloca ptr, align 4
 330 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
 331 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 332 // CHECK3-NEXT:    store ptr [[G]], ptr [[G1]], align 4
 333 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 334 // CHECK3-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4
 335 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 336 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4
 337 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4
 338 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
 339 // CHECK3-NEXT:    ret i32 0
 340 //
 341 //
 342 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68
 343 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {
 344 // CHECK3-NEXT:  entry:
 345 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 346 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 347 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
 348 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4
 349 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 350 // CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8
 351 // CHECK3-NEXT:    [[G13:%.*]] = alloca double, align 8
 352 // CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
 353 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 354 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 355 // CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
 356 // CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 357 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 358 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 359 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 4
 360 // CHECK3-NEXT:    [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8
 361 // CHECK3-NEXT:    store double [[TMP2]], ptr [[G2]], align 8
 362 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
 363 // CHECK3-NEXT:    [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4
 364 // CHECK3-NEXT:    store double [[TMP4]], ptr [[G13]], align 8
 365 // CHECK3-NEXT:    store ptr [[G13]], ptr [[_TMP4]], align 4
 366 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4
 367 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])
 368 // CHECK3-NEXT:    ret void
 369 //
 370 //
 371 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined
 372 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {
 373 // CHECK3-NEXT:  entry:
 374 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 375 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 376 // CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4
 377 // CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4
 378 // CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 4
 379 // CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca ptr, align 4
 380 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 381 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
 382 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 383 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 384 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 385 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 386 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 387 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 388 // CHECK3-NEXT:    [[G3:%.*]] = alloca double, align 8
 389 // CHECK3-NEXT:    [[G14:%.*]] = alloca double, align 8
 390 // CHECK3-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 4
 391 // CHECK3-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4
 392 // CHECK3-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4
 393 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 394 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
 395 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 396 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 397 // CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4
 398 // CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4
 399 // CHECK3-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4
 400 // CHECK3-NEXT:    store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
 401 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
 402 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
 403 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4
 404 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4
 405 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 4
 406 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
 407 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 4
 408 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 409 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 410 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 411 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 412 // CHECK3-NEXT:    [[TMP5:%.*]] = load volatile double, ptr [[TMP0]], align 8
 413 // CHECK3-NEXT:    store double [[TMP5]], ptr [[G3]], align 8
 414 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4
 415 // CHECK3-NEXT:    [[TMP7:%.*]] = load volatile double, ptr [[TMP6]], align 4
 416 // CHECK3-NEXT:    store double [[TMP7]], ptr [[G14]], align 8
 417 // CHECK3-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 4
 418 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4
 419 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[SVAR6]], align 4
 420 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4
 421 // CHECK3-NEXT:    store float [[TMP9]], ptr [[SFVAR7]], align 4
 422 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 423 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 424 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 425 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 426 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
 427 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 428 // CHECK3:       cond.true:
 429 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 430 // CHECK3:       cond.false:
 431 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 432 // CHECK3-NEXT:    br label [[COND_END]]
 433 // CHECK3:       cond.end:
 434 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
 435 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 436 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 437 // CHECK3-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
 438 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 439 // CHECK3:       omp.inner.for.cond:
 440 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 441 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 442 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
 443 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 444 // CHECK3:       omp.inner.for.body:
 445 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 446 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
 447 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 448 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 449 // CHECK3-NEXT:    [[TMP18:%.*]] = load double, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP5]]
 450 // CHECK3-NEXT:    [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00
 451 // CHECK3-NEXT:    store double [[ADD9]], ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP5]]
 452 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4, !llvm.access.group [[ACC_GRP5]]
 453 // CHECK3-NEXT:    [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP5]]
 454 // CHECK3-NEXT:    [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00
 455 // CHECK3-NEXT:    store volatile double [[ADD10]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP5]]
 456 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP5]]
 457 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3
 458 // CHECK3-NEXT:    store i32 [[ADD11]], ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP5]]
 459 // CHECK3-NEXT:    [[TMP22:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP5]]
 460 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP22]] to double
 461 // CHECK3-NEXT:    [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00
 462 // CHECK3-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
 463 // CHECK3-NEXT:    store float [[CONV13]], ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP5]]
 464 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 465 // CHECK3-NEXT:    store ptr [[G3]], ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP5]]
 466 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
 467 // CHECK3-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 4, !llvm.access.group [[ACC_GRP5]]
 468 // CHECK3-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP5]]
 469 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
 470 // CHECK3-NEXT:    store ptr [[SVAR6]], ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP5]]
 471 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
 472 // CHECK3-NEXT:    store ptr [[SFVAR7]], ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP5]]
 473 // CHECK3-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group [[ACC_GRP5]]
 474 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 475 // CHECK3:       omp.body.continue:
 476 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 477 // CHECK3:       omp.inner.for.inc:
 478 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 479 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1
 480 // CHECK3-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 481 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 482 // CHECK3:       omp.inner.for.end:
 483 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 484 // CHECK3:       omp.loop.exit:
 485 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])
 486 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 487 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
 488 // CHECK3-NEXT:    br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 489 // CHECK3:       .omp.final.then:
 490 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 491 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 492 // CHECK3:       .omp.final.done:
 493 // CHECK3-NEXT:    ret void
 494 //
 495 //
 496 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 497 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
 498 // CHECK3-NEXT:  entry:
 499 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
 500 // CHECK3-NEXT:    ret void
 501 //
 502 //
 503 // CHECK5-LABEL: define {{[^@]+}}@main
 504 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
 505 // CHECK5-NEXT:  entry:
 506 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 507 // CHECK5-NEXT:    [[G:%.*]] = alloca double, align 8
 508 // CHECK5-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 509 // CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
 510 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 511 // CHECK5-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 512 // CHECK5-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 513 // CHECK5-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8
 514 // CHECK5-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 515 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8
 516 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8
 517 // CHECK5-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
 518 // CHECK5-NEXT:    ret i32 0
 519 //
 520 //
 521 // CHECK7-LABEL: define {{[^@]+}}@main
 522 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
 523 // CHECK7-NEXT:  entry:
 524 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 525 // CHECK7-NEXT:    [[G:%.*]] = alloca double, align 8
 526 // CHECK7-NEXT:    [[G1:%.*]] = alloca ptr, align 4
 527 // CHECK7-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
 528 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 529 // CHECK7-NEXT:    store ptr [[G]], ptr [[G1]], align 4
 530 // CHECK7-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 531 // CHECK7-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4
 532 // CHECK7-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
 533 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4
 534 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4
 535 // CHECK7-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
 536 // CHECK7-NEXT:    ret i32 0
 537 //
 538 //
 539 // CHECK9-LABEL: define {{[^@]+}}@main
 540 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
 541 // CHECK9-NEXT:  entry:
 542 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 543 // CHECK9-NEXT:    [[G:%.*]] = alloca double, align 8
 544 // CHECK9-NEXT:    [[G1:%.*]] = alloca ptr, align 8
 545 // CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 546 // CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 547 // CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 548 // CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 549 // CHECK9-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 550 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 551 // CHECK9-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 552 // CHECK9-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8
 553 // CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
 554 // CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
 555 // CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
 556 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 557 // CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 558 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 559 // CHECK9-NEXT:    store ptr [[G]], ptr [[G1]], align 8
 560 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 561 // CHECK9-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 562 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
 563 // CHECK9-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
 564 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
 565 // CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1
 566 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
 567 // CHECK9-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 568 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
 569 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
 570 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
 571 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
 572 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 573 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 574 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
 575 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
 576 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
 577 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
 578 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
 579 // CHECK9-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 580 // CHECK9-NEXT:    store i64 [[TMP2]], ptr [[TMP8]], align 8
 581 // CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 582 // CHECK9-NEXT:    store i64 [[TMP2]], ptr [[TMP9]], align 8
 583 // CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 584 // CHECK9-NEXT:    store ptr null, ptr [[TMP10]], align 8
 585 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 586 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[TMP11]], align 8
 587 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 588 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[TMP12]], align 8
 589 // CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 590 // CHECK9-NEXT:    store ptr null, ptr [[TMP13]], align 8
 591 // CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 592 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[TMP14]], align 8
 593 // CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 594 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[TMP15]], align 8
 595 // CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 596 // CHECK9-NEXT:    store ptr null, ptr [[TMP16]], align 8
 597 // CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 598 // CHECK9-NEXT:    store ptr [[TMP6]], ptr [[TMP17]], align 8
 599 // CHECK9-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 600 // CHECK9-NEXT:    store ptr [[TMP7]], ptr [[TMP18]], align 8
 601 // CHECK9-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 602 // CHECK9-NEXT:    store ptr null, ptr [[TMP19]], align 8
 603 // CHECK9-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 604 // CHECK9-NEXT:    store i64 [[TMP5]], ptr [[TMP20]], align 8
 605 // CHECK9-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 606 // CHECK9-NEXT:    store i64 [[TMP5]], ptr [[TMP21]], align 8
 607 // CHECK9-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 608 // CHECK9-NEXT:    store ptr null, ptr [[TMP22]], align 8
 609 // CHECK9-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 610 // CHECK9-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 611 // CHECK9-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 612 // CHECK9-NEXT:    store i32 2, ptr [[TMP25]], align 4
 613 // CHECK9-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 614 // CHECK9-NEXT:    store i32 5, ptr [[TMP26]], align 4
 615 // CHECK9-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 616 // CHECK9-NEXT:    store ptr [[TMP23]], ptr [[TMP27]], align 8
 617 // CHECK9-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 618 // CHECK9-NEXT:    store ptr [[TMP24]], ptr [[TMP28]], align 8
 619 // CHECK9-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 620 // CHECK9-NEXT:    store ptr @.offload_sizes, ptr [[TMP29]], align 8
 621 // CHECK9-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 622 // CHECK9-NEXT:    store ptr @.offload_maptypes, ptr [[TMP30]], align 8
 623 // CHECK9-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 624 // CHECK9-NEXT:    store ptr null, ptr [[TMP31]], align 8
 625 // CHECK9-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 626 // CHECK9-NEXT:    store ptr null, ptr [[TMP32]], align 8
 627 // CHECK9-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 628 // CHECK9-NEXT:    store i64 2, ptr [[TMP33]], align 8
 629 // CHECK9-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 630 // CHECK9-NEXT:    store i64 0, ptr [[TMP34]], align 8
 631 // CHECK9-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 632 // CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
 633 // CHECK9-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 634 // CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP36]], align 4
 635 // CHECK9-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 636 // CHECK9-NEXT:    store i32 0, ptr [[TMP37]], align 4
 637 // CHECK9-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, ptr [[KERNEL_ARGS]])
 638 // CHECK9-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
 639 // CHECK9-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 640 // CHECK9:       omp_offload.failed:
 641 // CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]
 642 // CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 643 // CHECK9:       omp_offload.cont:
 644 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 645 // CHECK9-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 646 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 647 // CHECK9-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 648 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 649 // CHECK9:       arraydestroy.body:
 650 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 651 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 652 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 653 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 654 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 655 // CHECK9:       arraydestroy.done2:
 656 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 657 // CHECK9-NEXT:    [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
 658 // CHECK9-NEXT:    ret i32 [[TMP41]]
 659 //
 660 //
 661 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 662 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 663 // CHECK9-NEXT:  entry:
 664 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 665 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 666 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 667 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 668 // CHECK9-NEXT:    ret void
 669 //
 670 //
 671 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 672 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 673 // CHECK9-NEXT:  entry:
 674 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 675 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 676 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 677 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 678 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 679 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 680 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 681 // CHECK9-NEXT:    ret void
 682 //
 683 //
 684 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105
 685 // CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
 686 // CHECK9-NEXT:  entry:
 687 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 688 // CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 689 // CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 690 // CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 691 // CHECK9-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8
 692 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 693 // CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 694 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 695 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 696 // CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 697 // CHECK9-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
 698 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 699 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 700 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 701 // CHECK9-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
 702 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 703 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])
 704 // CHECK9-NEXT:    ret void
 705 //
 706 //
 707 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined
 708 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {
 709 // CHECK9-NEXT:  entry:
 710 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 711 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 712 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
 713 // CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 714 // CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 715 // CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 716 // CHECK9-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 8
 717 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 718 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 719 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 720 // CHECK9-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 721 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 722 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 723 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 724 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 725 // CHECK9-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
 726 // CHECK9-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
 727 // CHECK9-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
 728 // CHECK9-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 729 // CHECK9-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 8
 730 // CHECK9-NEXT:    [[SVAR9:%.*]] = alloca i32, align 4
 731 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
 732 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 733 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 734 // CHECK9-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 735 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 736 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 737 // CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 738 // CHECK9-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8
 739 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
 740 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 741 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 742 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 743 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8
 744 // CHECK9-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 8
 745 // CHECK9-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
 746 // CHECK9-NEXT:    store ptr [[TMP5]], ptr [[_TMP1]], align 8
 747 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 748 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 749 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 750 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 751 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
 752 // CHECK9-NEXT:    store i32 [[TMP6]], ptr [[T_VAR3]], align 4
 753 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)
 754 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
 755 // CHECK9-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 756 // CHECK9-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]
 757 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 758 // CHECK9:       omp.arraycpy.body:
 759 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 760 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 761 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
 762 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 763 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 764 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
 765 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
 766 // CHECK9:       omp.arraycpy.done6:
 767 // CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
 768 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false)
 769 // CHECK9-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 8
 770 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4
 771 // CHECK9-NEXT:    store i32 [[TMP9]], ptr [[SVAR9]], align 4
 772 // CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 773 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 774 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 775 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 776 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
 777 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 778 // CHECK9:       cond.true:
 779 // CHECK9-NEXT:    br label [[COND_END:%.*]]
 780 // CHECK9:       cond.false:
 781 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 782 // CHECK9-NEXT:    br label [[COND_END]]
 783 // CHECK9:       cond.end:
 784 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
 785 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 786 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 787 // CHECK9-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
 788 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 789 // CHECK9:       omp.inner.for.cond:
 790 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 791 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 792 // CHECK9-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
 793 // CHECK9-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 794 // CHECK9:       omp.inner.for.cond.cleanup:
 795 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 796 // CHECK9:       omp.inner.for.body:
 797 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 798 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
 799 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 800 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 801 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP5]]
 802 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 803 // CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
 804 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
 805 // CHECK9-NEXT:    store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
 806 // CHECK9-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP5]]
 807 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 808 // CHECK9-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
 809 // CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
 810 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]]
 811 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 812 // CHECK9:       omp.body.continue:
 813 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 814 // CHECK9:       omp.inner.for.inc:
 815 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 816 // CHECK9-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP22]], 1
 817 // CHECK9-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 818 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 819 // CHECK9:       omp.inner.for.end:
 820 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 821 // CHECK9:       omp.loop.exit:
 822 // CHECK9-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 823 // CHECK9-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
 824 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP24]])
 825 // CHECK9-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 826 // CHECK9-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
 827 // CHECK9-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 828 // CHECK9:       .omp.final.then:
 829 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
 830 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 831 // CHECK9:       .omp.final.done:
 832 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
 833 // CHECK9-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
 834 // CHECK9-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2
 835 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 836 // CHECK9:       arraydestroy.body:
 837 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 838 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 839 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 840 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
 841 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
 842 // CHECK9:       arraydestroy.done15:
 843 // CHECK9-NEXT:    ret void
 844 //
 845 //
 846 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 847 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 848 // CHECK9-NEXT:  entry:
 849 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 850 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 851 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 852 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 853 // CHECK9-NEXT:    ret void
 854 //
 855 //
 856 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 857 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat {
 858 // CHECK9-NEXT:  entry:
 859 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 860 // CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 861 // CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 862 // CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 863 // CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 864 // CHECK9-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 865 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 866 // CHECK9-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 867 // CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
 868 // CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
 869 // CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
 870 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 871 // CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 872 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 873 // CHECK9-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 874 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 875 // CHECK9-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
 876 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
 877 // CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
 878 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
 879 // CHECK9-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 880 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
 881 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
 882 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
 883 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
 884 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 885 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 886 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
 887 // CHECK9-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
 888 // CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 889 // CHECK9-NEXT:    store i64 [[TMP2]], ptr [[TMP6]], align 8
 890 // CHECK9-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 891 // CHECK9-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8
 892 // CHECK9-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 893 // CHECK9-NEXT:    store ptr null, ptr [[TMP8]], align 8
 894 // CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 895 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 8
 896 // CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 897 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 8
 898 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 899 // CHECK9-NEXT:    store ptr null, ptr [[TMP11]], align 8
 900 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 901 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 8
 902 // CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 903 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 8
 904 // CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 905 // CHECK9-NEXT:    store ptr null, ptr [[TMP14]], align 8
 906 // CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 907 // CHECK9-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 8
 908 // CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 909 // CHECK9-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 8
 910 // CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 911 // CHECK9-NEXT:    store ptr null, ptr [[TMP17]], align 8
 912 // CHECK9-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 913 // CHECK9-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 914 // CHECK9-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 915 // CHECK9-NEXT:    store i32 2, ptr [[TMP20]], align 4
 916 // CHECK9-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 917 // CHECK9-NEXT:    store i32 4, ptr [[TMP21]], align 4
 918 // CHECK9-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 919 // CHECK9-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8
 920 // CHECK9-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 921 // CHECK9-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
 922 // CHECK9-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 923 // CHECK9-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP24]], align 8
 924 // CHECK9-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 925 // CHECK9-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP25]], align 8
 926 // CHECK9-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 927 // CHECK9-NEXT:    store ptr null, ptr [[TMP26]], align 8
 928 // CHECK9-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 929 // CHECK9-NEXT:    store ptr null, ptr [[TMP27]], align 8
 930 // CHECK9-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 931 // CHECK9-NEXT:    store i64 2, ptr [[TMP28]], align 8
 932 // CHECK9-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 933 // CHECK9-NEXT:    store i64 0, ptr [[TMP29]], align 8
 934 // CHECK9-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 935 // CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
 936 // CHECK9-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 937 // CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
 938 // CHECK9-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 939 // CHECK9-NEXT:    store i32 0, ptr [[TMP32]], align 4
 940 // CHECK9-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
 941 // CHECK9-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
 942 // CHECK9-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 943 // CHECK9:       omp_offload.failed:
 944 // CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
 945 // CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 946 // CHECK9:       omp_offload.cont:
 947 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 948 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 949 // CHECK9-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 950 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 951 // CHECK9:       arraydestroy.body:
 952 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 953 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 954 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 955 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 956 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 957 // CHECK9:       arraydestroy.done2:
 958 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 959 // CHECK9-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
 960 // CHECK9-NEXT:    ret i32 [[TMP36]]
 961 //
 962 //
 963 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 964 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 965 // CHECK9-NEXT:  entry:
 966 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 967 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 968 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 969 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 970 // CHECK9-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
 971 // CHECK9-NEXT:    ret void
 972 //
 973 //
 974 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 975 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 976 // CHECK9-NEXT:  entry:
 977 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 978 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 979 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 980 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 981 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 982 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 983 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 984 // CHECK9-NEXT:    store float [[TMP0]], ptr [[F]], align 4
 985 // CHECK9-NEXT:    ret void
 986 //
 987 //
 988 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 989 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 990 // CHECK9-NEXT:  entry:
 991 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 992 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 993 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 994 // CHECK9-NEXT:    ret void
 995 //
 996 //
 997 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 998 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 999 // CHECK9-NEXT:  entry:
1000 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1001 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1002 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1003 // CHECK9-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1004 // CHECK9-NEXT:    ret void
1005 //
1006 //
1007 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1008 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1009 // CHECK9-NEXT:  entry:
1010 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1011 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1012 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1013 // CHECK9-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1014 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1015 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1016 // CHECK9-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1017 // CHECK9-NEXT:    ret void
1018 //
1019 //
1020 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49
1021 // CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1022 // CHECK9-NEXT:  entry:
1023 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1024 // CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1025 // CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1026 // CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1027 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1028 // CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1029 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1030 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1031 // CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1032 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1033 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1034 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1035 // CHECK9-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1036 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1037 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])
1038 // CHECK9-NEXT:    ret void
1039 //
1040 //
1041 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined
1042 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1043 // CHECK9-NEXT:  entry:
1044 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1045 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1046 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1047 // CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1048 // CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1049 // CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1050 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1051 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1052 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1053 // CHECK9-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
1054 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1055 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1056 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1057 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1058 // CHECK9-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1059 // CHECK9-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1060 // CHECK9-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1061 // CHECK9-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1062 // CHECK9-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 8
1063 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
1064 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1065 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1066 // CHECK9-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1067 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1068 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1069 // CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1070 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1071 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1072 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1073 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1074 // CHECK9-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 8
1075 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
1076 // CHECK9-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 8
1077 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1078 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1079 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1080 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1081 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
1082 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 4
1083 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)
1084 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1085 // CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1086 // CHECK9-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]
1087 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1088 // CHECK9:       omp.arraycpy.body:
1089 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1090 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1091 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1092 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1093 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1094 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1095 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1096 // CHECK9:       omp.arraycpy.done6:
1097 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8
1098 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false)
1099 // CHECK9-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 8
1100 // CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1101 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1102 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1103 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1104 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
1105 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1106 // CHECK9:       cond.true:
1107 // CHECK9-NEXT:    br label [[COND_END:%.*]]
1108 // CHECK9:       cond.false:
1109 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1110 // CHECK9-NEXT:    br label [[COND_END]]
1111 // CHECK9:       cond.end:
1112 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1113 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1114 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1115 // CHECK9-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
1116 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1117 // CHECK9:       omp.inner.for.cond:
1118 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
1119 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
1120 // CHECK9-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1121 // CHECK9-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1122 // CHECK9:       omp.inner.for.cond.cleanup:
1123 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1124 // CHECK9:       omp.inner.for.body:
1125 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1126 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
1127 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1128 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1129 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP11]]
1130 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1131 // CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
1132 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
1133 // CHECK9-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
1134 // CHECK9-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP11]]
1135 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1136 // CHECK9-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
1137 // CHECK9-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
1138 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]]
1139 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1140 // CHECK9:       omp.body.continue:
1141 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1142 // CHECK9:       omp.inner.for.inc:
1143 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1144 // CHECK9-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
1145 // CHECK9-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1146 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
1147 // CHECK9:       omp.inner.for.end:
1148 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1149 // CHECK9:       omp.loop.exit:
1150 // CHECK9-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1151 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
1152 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
1153 // CHECK9-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1154 // CHECK9-NEXT:    [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
1155 // CHECK9-NEXT:    br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1156 // CHECK9:       .omp.final.then:
1157 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
1158 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1159 // CHECK9:       .omp.final.done:
1160 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
1161 // CHECK9-NEXT:    [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1162 // CHECK9-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2
1163 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1164 // CHECK9:       arraydestroy.body:
1165 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1166 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1167 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1168 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
1169 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
1170 // CHECK9:       arraydestroy.done14:
1171 // CHECK9-NEXT:    ret void
1172 //
1173 //
1174 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1175 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1176 // CHECK9-NEXT:  entry:
1177 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1178 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1179 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1180 // CHECK9-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1181 // CHECK9-NEXT:    ret void
1182 //
1183 //
1184 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1185 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1186 // CHECK9-NEXT:  entry:
1187 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1188 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1189 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1190 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1191 // CHECK9-NEXT:    store i32 0, ptr [[F]], align 4
1192 // CHECK9-NEXT:    ret void
1193 //
1194 //
1195 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1196 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1197 // CHECK9-NEXT:  entry:
1198 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1199 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1200 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1201 // CHECK9-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1202 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1203 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1204 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1205 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1206 // CHECK9-NEXT:    ret void
1207 //
1208 //
1209 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1210 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1211 // CHECK9-NEXT:  entry:
1212 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1213 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1214 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1215 // CHECK9-NEXT:    ret void
1216 //
1217 //
1218 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1219 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] {
1220 // CHECK9-NEXT:  entry:
1221 // CHECK9-NEXT:    call void @__tgt_register_requires(i64 1)
1222 // CHECK9-NEXT:    ret void
1223 //
1224 //
1225 // CHECK11-LABEL: define {{[^@]+}}@main
1226 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
1227 // CHECK11-NEXT:  entry:
1228 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1229 // CHECK11-NEXT:    [[G:%.*]] = alloca double, align 8
1230 // CHECK11-NEXT:    [[G1:%.*]] = alloca ptr, align 4
1231 // CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1232 // CHECK11-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1233 // CHECK11-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1234 // CHECK11-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1235 // CHECK11-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1236 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1237 // CHECK11-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1238 // CHECK11-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4
1239 // CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1240 // CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1241 // CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1242 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1243 // CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1244 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1245 // CHECK11-NEXT:    store ptr [[G]], ptr [[G1]], align 4
1246 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1247 // CHECK11-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1248 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
1249 // CHECK11-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1250 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
1251 // CHECK11-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1
1252 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
1253 // CHECK11-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1254 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1255 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
1256 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1257 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1258 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1259 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1260 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
1261 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
1262 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1263 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4
1264 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4
1265 // CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1266 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[TMP8]], align 4
1267 // CHECK11-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1268 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[TMP9]], align 4
1269 // CHECK11-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1270 // CHECK11-NEXT:    store ptr null, ptr [[TMP10]], align 4
1271 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1272 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[TMP11]], align 4
1273 // CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1274 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[TMP12]], align 4
1275 // CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1276 // CHECK11-NEXT:    store ptr null, ptr [[TMP13]], align 4
1277 // CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1278 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[TMP14]], align 4
1279 // CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1280 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[TMP15]], align 4
1281 // CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1282 // CHECK11-NEXT:    store ptr null, ptr [[TMP16]], align 4
1283 // CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1284 // CHECK11-NEXT:    store ptr [[TMP6]], ptr [[TMP17]], align 4
1285 // CHECK11-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1286 // CHECK11-NEXT:    store ptr [[TMP7]], ptr [[TMP18]], align 4
1287 // CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1288 // CHECK11-NEXT:    store ptr null, ptr [[TMP19]], align 4
1289 // CHECK11-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1290 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP20]], align 4
1291 // CHECK11-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1292 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP21]], align 4
1293 // CHECK11-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1294 // CHECK11-NEXT:    store ptr null, ptr [[TMP22]], align 4
1295 // CHECK11-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1296 // CHECK11-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1297 // CHECK11-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1298 // CHECK11-NEXT:    store i32 2, ptr [[TMP25]], align 4
1299 // CHECK11-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1300 // CHECK11-NEXT:    store i32 5, ptr [[TMP26]], align 4
1301 // CHECK11-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1302 // CHECK11-NEXT:    store ptr [[TMP23]], ptr [[TMP27]], align 4
1303 // CHECK11-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1304 // CHECK11-NEXT:    store ptr [[TMP24]], ptr [[TMP28]], align 4
1305 // CHECK11-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1306 // CHECK11-NEXT:    store ptr @.offload_sizes, ptr [[TMP29]], align 4
1307 // CHECK11-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1308 // CHECK11-NEXT:    store ptr @.offload_maptypes, ptr [[TMP30]], align 4
1309 // CHECK11-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1310 // CHECK11-NEXT:    store ptr null, ptr [[TMP31]], align 4
1311 // CHECK11-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1312 // CHECK11-NEXT:    store ptr null, ptr [[TMP32]], align 4
1313 // CHECK11-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1314 // CHECK11-NEXT:    store i64 2, ptr [[TMP33]], align 8
1315 // CHECK11-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1316 // CHECK11-NEXT:    store i64 0, ptr [[TMP34]], align 8
1317 // CHECK11-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1318 // CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
1319 // CHECK11-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1320 // CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP36]], align 4
1321 // CHECK11-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1322 // CHECK11-NEXT:    store i32 0, ptr [[TMP37]], align 4
1323 // CHECK11-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, ptr [[KERNEL_ARGS]])
1324 // CHECK11-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
1325 // CHECK11-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1326 // CHECK11:       omp_offload.failed:
1327 // CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]
1328 // CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1329 // CHECK11:       omp_offload.cont:
1330 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1331 // CHECK11-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1332 // CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1333 // CHECK11-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1334 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1335 // CHECK11:       arraydestroy.body:
1336 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1337 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1338 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1339 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1340 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1341 // CHECK11:       arraydestroy.done2:
1342 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1343 // CHECK11-NEXT:    [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
1344 // CHECK11-NEXT:    ret i32 [[TMP41]]
1345 //
1346 //
1347 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1348 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1349 // CHECK11-NEXT:  entry:
1350 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1351 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1352 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1353 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1354 // CHECK11-NEXT:    ret void
1355 //
1356 //
1357 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1358 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1359 // CHECK11-NEXT:  entry:
1360 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1361 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1362 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1363 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1364 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1365 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1366 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1367 // CHECK11-NEXT:    ret void
1368 //
1369 //
1370 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105
1371 // CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1372 // CHECK11-NEXT:  entry:
1373 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1374 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1375 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1376 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1377 // CHECK11-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4
1378 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1379 // CHECK11-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1380 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1381 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1382 // CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1383 // CHECK11-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
1384 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1385 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1386 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1387 // CHECK11-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
1388 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1389 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])
1390 // CHECK11-NEXT:    ret void
1391 //
1392 //
1393 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined
1394 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {
1395 // CHECK11-NEXT:  entry:
1396 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1397 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1398 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
1399 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1400 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1401 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1402 // CHECK11-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 4
1403 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1404 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1405 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1406 // CHECK11-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
1407 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1408 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1409 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1410 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1411 // CHECK11-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1412 // CHECK11-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1413 // CHECK11-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1414 // CHECK11-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1415 // CHECK11-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 4
1416 // CHECK11-NEXT:    [[SVAR9:%.*]] = alloca i32, align 4
1417 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
1418 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1419 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1420 // CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1421 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1422 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1423 // CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1424 // CHECK11-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4
1425 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
1426 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1427 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1428 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1429 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4
1430 // CHECK11-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 4
1431 // CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1432 // CHECK11-NEXT:    store ptr [[TMP5]], ptr [[_TMP1]], align 4
1433 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1434 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1435 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1436 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1437 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
1438 // CHECK11-NEXT:    store i32 [[TMP6]], ptr [[T_VAR3]], align 4
1439 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)
1440 // CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1441 // CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1442 // CHECK11-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]
1443 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1444 // CHECK11:       omp.arraycpy.body:
1445 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1446 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1447 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
1448 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1449 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1450 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
1451 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1452 // CHECK11:       omp.arraycpy.done6:
1453 // CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4
1454 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false)
1455 // CHECK11-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 4
1456 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4
1457 // CHECK11-NEXT:    store i32 [[TMP9]], ptr [[SVAR9]], align 4
1458 // CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1459 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
1460 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1461 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1462 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
1463 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1464 // CHECK11:       cond.true:
1465 // CHECK11-NEXT:    br label [[COND_END:%.*]]
1466 // CHECK11:       cond.false:
1467 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1468 // CHECK11-NEXT:    br label [[COND_END]]
1469 // CHECK11:       cond.end:
1470 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1471 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1472 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1473 // CHECK11-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
1474 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1475 // CHECK11:       omp.inner.for.cond:
1476 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1477 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1478 // CHECK11-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1479 // CHECK11-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1480 // CHECK11:       omp.inner.for.cond.cleanup:
1481 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1482 // CHECK11:       omp.inner.for.body:
1483 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1484 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1485 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1486 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1487 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]]
1488 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1489 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP19]]
1490 // CHECK11-NEXT:    store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
1491 // CHECK11-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP6]]
1492 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1493 // CHECK11-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP21]]
1494 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]]
1495 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1496 // CHECK11:       omp.body.continue:
1497 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1498 // CHECK11:       omp.inner.for.inc:
1499 // CHECK11-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1500 // CHECK11-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1
1501 // CHECK11-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1502 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1503 // CHECK11:       omp.inner.for.end:
1504 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1505 // CHECK11:       omp.loop.exit:
1506 // CHECK11-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1507 // CHECK11-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
1508 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP24]])
1509 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1510 // CHECK11-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1511 // CHECK11-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1512 // CHECK11:       .omp.final.then:
1513 // CHECK11-NEXT:    store i32 2, ptr [[I]], align 4
1514 // CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1515 // CHECK11:       .omp.final.done:
1516 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
1517 // CHECK11-NEXT:    [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1518 // CHECK11-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2
1519 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1520 // CHECK11:       arraydestroy.body:
1521 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1522 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1523 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1524 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
1525 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
1526 // CHECK11:       arraydestroy.done14:
1527 // CHECK11-NEXT:    ret void
1528 //
1529 //
1530 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1531 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1532 // CHECK11-NEXT:  entry:
1533 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1534 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1535 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1536 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1537 // CHECK11-NEXT:    ret void
1538 //
1539 //
1540 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1541 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat {
1542 // CHECK11-NEXT:  entry:
1543 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1544 // CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1545 // CHECK11-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1546 // CHECK11-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1547 // CHECK11-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1548 // CHECK11-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1549 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1550 // CHECK11-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1551 // CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
1552 // CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
1553 // CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
1554 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1555 // CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1556 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1557 // CHECK11-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1558 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1559 // CHECK11-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1560 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1561 // CHECK11-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
1562 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1563 // CHECK11-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1564 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1565 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
1566 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1567 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1568 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1569 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1570 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
1571 // CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1572 // CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1573 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[TMP6]], align 4
1574 // CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1575 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 4
1576 // CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1577 // CHECK11-NEXT:    store ptr null, ptr [[TMP8]], align 4
1578 // CHECK11-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1579 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 4
1580 // CHECK11-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1581 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 4
1582 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1583 // CHECK11-NEXT:    store ptr null, ptr [[TMP11]], align 4
1584 // CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1585 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 4
1586 // CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1587 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 4
1588 // CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1589 // CHECK11-NEXT:    store ptr null, ptr [[TMP14]], align 4
1590 // CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1591 // CHECK11-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 4
1592 // CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1593 // CHECK11-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 4
1594 // CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1595 // CHECK11-NEXT:    store ptr null, ptr [[TMP17]], align 4
1596 // CHECK11-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1597 // CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1598 // CHECK11-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1599 // CHECK11-NEXT:    store i32 2, ptr [[TMP20]], align 4
1600 // CHECK11-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1601 // CHECK11-NEXT:    store i32 4, ptr [[TMP21]], align 4
1602 // CHECK11-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1603 // CHECK11-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 4
1604 // CHECK11-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1605 // CHECK11-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
1606 // CHECK11-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1607 // CHECK11-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP24]], align 4
1608 // CHECK11-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1609 // CHECK11-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP25]], align 4
1610 // CHECK11-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1611 // CHECK11-NEXT:    store ptr null, ptr [[TMP26]], align 4
1612 // CHECK11-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1613 // CHECK11-NEXT:    store ptr null, ptr [[TMP27]], align 4
1614 // CHECK11-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1615 // CHECK11-NEXT:    store i64 2, ptr [[TMP28]], align 8
1616 // CHECK11-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1617 // CHECK11-NEXT:    store i64 0, ptr [[TMP29]], align 8
1618 // CHECK11-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1619 // CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
1620 // CHECK11-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1621 // CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
1622 // CHECK11-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1623 // CHECK11-NEXT:    store i32 0, ptr [[TMP32]], align 4
1624 // CHECK11-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
1625 // CHECK11-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1626 // CHECK11-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1627 // CHECK11:       omp_offload.failed:
1628 // CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
1629 // CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1630 // CHECK11:       omp_offload.cont:
1631 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1632 // CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1633 // CHECK11-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1634 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1635 // CHECK11:       arraydestroy.body:
1636 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1637 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1638 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1639 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1640 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1641 // CHECK11:       arraydestroy.done2:
1642 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1643 // CHECK11-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
1644 // CHECK11-NEXT:    ret i32 [[TMP36]]
1645 //
1646 //
1647 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1648 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1649 // CHECK11-NEXT:  entry:
1650 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1651 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1652 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1653 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1654 // CHECK11-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
1655 // CHECK11-NEXT:    ret void
1656 //
1657 //
1658 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1659 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1660 // CHECK11-NEXT:  entry:
1661 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1662 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1663 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1664 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1665 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1666 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1667 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1668 // CHECK11-NEXT:    store float [[TMP0]], ptr [[F]], align 4
1669 // CHECK11-NEXT:    ret void
1670 //
1671 //
1672 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1673 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1674 // CHECK11-NEXT:  entry:
1675 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1676 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1677 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1678 // CHECK11-NEXT:    ret void
1679 //
1680 //
1681 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1682 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1683 // CHECK11-NEXT:  entry:
1684 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1685 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1686 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1687 // CHECK11-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1688 // CHECK11-NEXT:    ret void
1689 //
1690 //
1691 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1692 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1693 // CHECK11-NEXT:  entry:
1694 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1695 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1696 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1697 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1698 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1699 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1700 // CHECK11-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1701 // CHECK11-NEXT:    ret void
1702 //
1703 //
1704 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49
1705 // CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1706 // CHECK11-NEXT:  entry:
1707 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1708 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1709 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1710 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1711 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1712 // CHECK11-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1713 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1714 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1715 // CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1716 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1717 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1718 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1719 // CHECK11-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
1720 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1721 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])
1722 // CHECK11-NEXT:    ret void
1723 //
1724 //
1725 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined
1726 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1727 // CHECK11-NEXT:  entry:
1728 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1729 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1730 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
1731 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1732 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1733 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1734 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1735 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1736 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1737 // CHECK11-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
1738 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1739 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1740 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1741 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1742 // CHECK11-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
1743 // CHECK11-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1744 // CHECK11-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1745 // CHECK11-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1746 // CHECK11-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 4
1747 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
1748 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1749 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1750 // CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1751 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1752 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1753 // CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1754 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
1755 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1756 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1757 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1758 // CHECK11-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 4
1759 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
1760 // CHECK11-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 4
1761 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1762 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1763 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1764 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1765 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
1766 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 4
1767 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)
1768 // CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1769 // CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1770 // CHECK11-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]
1771 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1772 // CHECK11:       omp.arraycpy.body:
1773 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1774 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1775 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
1776 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1777 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1778 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1779 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1780 // CHECK11:       omp.arraycpy.done6:
1781 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4
1782 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false)
1783 // CHECK11-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 4
1784 // CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1785 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1786 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1787 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1788 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
1789 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1790 // CHECK11:       cond.true:
1791 // CHECK11-NEXT:    br label [[COND_END:%.*]]
1792 // CHECK11:       cond.false:
1793 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1794 // CHECK11-NEXT:    br label [[COND_END]]
1795 // CHECK11:       cond.end:
1796 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1797 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1798 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1799 // CHECK11-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
1800 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1801 // CHECK11:       omp.inner.for.cond:
1802 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
1803 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
1804 // CHECK11-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1805 // CHECK11-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1806 // CHECK11:       omp.inner.for.cond.cleanup:
1807 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1808 // CHECK11:       omp.inner.for.body:
1809 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1810 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
1811 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1812 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1813 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP12]]
1814 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1815 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP17]]
1816 // CHECK11-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]]
1817 // CHECK11-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP12]]
1818 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1819 // CHECK11-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP19]]
1820 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]]
1821 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1822 // CHECK11:       omp.body.continue:
1823 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1824 // CHECK11:       omp.inner.for.inc:
1825 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1826 // CHECK11-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
1827 // CHECK11-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1828 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1829 // CHECK11:       omp.inner.for.end:
1830 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1831 // CHECK11:       omp.loop.exit:
1832 // CHECK11-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1833 // CHECK11-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
1834 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
1835 // CHECK11-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1836 // CHECK11-NEXT:    [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
1837 // CHECK11-NEXT:    br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1838 // CHECK11:       .omp.final.then:
1839 // CHECK11-NEXT:    store i32 2, ptr [[I]], align 4
1840 // CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1841 // CHECK11:       .omp.final.done:
1842 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
1843 // CHECK11-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1844 // CHECK11-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2
1845 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1846 // CHECK11:       arraydestroy.body:
1847 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1848 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1849 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1850 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
1851 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
1852 // CHECK11:       arraydestroy.done13:
1853 // CHECK11-NEXT:    ret void
1854 //
1855 //
1856 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1857 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1858 // CHECK11-NEXT:  entry:
1859 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1860 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1861 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1862 // CHECK11-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1863 // CHECK11-NEXT:    ret void
1864 //
1865 //
1866 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1867 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1868 // CHECK11-NEXT:  entry:
1869 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1870 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1871 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1872 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1873 // CHECK11-NEXT:    store i32 0, ptr [[F]], align 4
1874 // CHECK11-NEXT:    ret void
1875 //
1876 //
1877 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1878 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1879 // CHECK11-NEXT:  entry:
1880 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1881 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1882 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1883 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1884 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1885 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1886 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1887 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1888 // CHECK11-NEXT:    ret void
1889 //
1890 //
1891 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1892 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1893 // CHECK11-NEXT:  entry:
1894 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1895 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1896 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1897 // CHECK11-NEXT:    ret void
1898 //
1899 //
1900 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1901 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] {
1902 // CHECK11-NEXT:  entry:
1903 // CHECK11-NEXT:    call void @__tgt_register_requires(i64 1)
1904 // CHECK11-NEXT:    ret void
1905 //
1906 //
1907 // CHECK13-LABEL: define {{[^@]+}}@main
1908 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] {
1909 // CHECK13-NEXT:  entry:
1910 // CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1911 // CHECK13-NEXT:    [[G:%.*]] = alloca double, align 8
1912 // CHECK13-NEXT:    [[G1:%.*]] = alloca ptr, align 8
1913 // CHECK13-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1914 // CHECK13-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1915 // CHECK13-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1916 // CHECK13-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1917 // CHECK13-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
1918 // CHECK13-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1919 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1920 // CHECK13-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
1921 // CHECK13-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
1922 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1923 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1924 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1925 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
1926 // CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1927 // CHECK13-NEXT:    store ptr [[G]], ptr [[G1]], align 8
1928 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1929 // CHECK13-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1930 // CHECK13-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
1931 // CHECK13-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
1932 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
1933 // CHECK13-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1
1934 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
1935 // CHECK13-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
1936 // CHECK13-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
1937 // CHECK13-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
1938 // CHECK13-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8
1939 // CHECK13-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
1940 // CHECK13-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 8
1941 // CHECK13-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8
1942 // CHECK13-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 8
1943 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1944 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1945 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1946 // CHECK13-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1947 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1948 // CHECK13:       omp.inner.for.cond:
1949 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1950 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
1951 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1952 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1953 // CHECK13:       omp.inner.for.body:
1954 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1955 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1956 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1957 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1958 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1959 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1960 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
1961 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
1962 // CHECK13-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1963 // CHECK13-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP2]]
1964 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1965 // CHECK13-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
1966 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
1967 // CHECK13-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]
1968 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1969 // CHECK13:       omp.body.continue:
1970 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1971 // CHECK13:       omp.inner.for.inc:
1972 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1973 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
1974 // CHECK13-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1975 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1976 // CHECK13:       omp.inner.for.end:
1977 // CHECK13-NEXT:    store i32 2, ptr [[I]], align 4
1978 // CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1979 // CHECK13-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1980 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1981 // CHECK13-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1982 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1983 // CHECK13:       arraydestroy.body:
1984 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1985 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1986 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
1987 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1988 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1989 // CHECK13:       arraydestroy.done7:
1990 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1991 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
1992 // CHECK13-NEXT:    ret i32 [[TMP14]]
1993 //
1994 //
1995 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1996 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1997 // CHECK13-NEXT:  entry:
1998 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1999 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2000 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2001 // CHECK13-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2002 // CHECK13-NEXT:    ret void
2003 //
2004 //
2005 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2006 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2007 // CHECK13-NEXT:  entry:
2008 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2009 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2010 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2011 // CHECK13-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2012 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2013 // CHECK13-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2014 // CHECK13-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2015 // CHECK13-NEXT:    ret void
2016 //
2017 //
2018 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2019 // CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat {
2020 // CHECK13-NEXT:  entry:
2021 // CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2022 // CHECK13-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2023 // CHECK13-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2024 // CHECK13-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2025 // CHECK13-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2026 // CHECK13-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
2027 // CHECK13-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2028 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2029 // CHECK13-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2030 // CHECK13-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2031 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2032 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2033 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2034 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
2035 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2036 // CHECK13-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2037 // CHECK13-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
2038 // CHECK13-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
2039 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
2040 // CHECK13-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
2041 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
2042 // CHECK13-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
2043 // CHECK13-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
2044 // CHECK13-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
2045 // CHECK13-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8
2046 // CHECK13-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
2047 // CHECK13-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 8
2048 // CHECK13-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8
2049 // CHECK13-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 8
2050 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2051 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2052 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2053 // CHECK13-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2054 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2055 // CHECK13:       omp.inner.for.cond:
2056 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
2057 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
2058 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2059 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2060 // CHECK13:       omp.inner.for.body:
2061 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2062 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2063 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2064 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2065 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]]
2066 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2067 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
2068 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
2069 // CHECK13-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
2070 // CHECK13-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP6]]
2071 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2072 // CHECK13-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
2073 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
2074 // CHECK13-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
2075 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2076 // CHECK13:       omp.body.continue:
2077 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2078 // CHECK13:       omp.inner.for.inc:
2079 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2080 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
2081 // CHECK13-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2082 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2083 // CHECK13:       omp.inner.for.end:
2084 // CHECK13-NEXT:    store i32 2, ptr [[I]], align 4
2085 // CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2086 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2087 // CHECK13-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
2088 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2089 // CHECK13:       arraydestroy.body:
2090 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2091 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2092 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2093 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2094 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2095 // CHECK13:       arraydestroy.done7:
2096 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2097 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2098 // CHECK13-NEXT:    ret i32 [[TMP14]]
2099 //
2100 //
2101 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2102 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2103 // CHECK13-NEXT:  entry:
2104 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2105 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2106 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2107 // CHECK13-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2108 // CHECK13-NEXT:    ret void
2109 //
2110 //
2111 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2112 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2113 // CHECK13-NEXT:  entry:
2114 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2115 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2116 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2117 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2118 // CHECK13-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
2119 // CHECK13-NEXT:    ret void
2120 //
2121 //
2122 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2123 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2124 // CHECK13-NEXT:  entry:
2125 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2126 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2127 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2128 // CHECK13-NEXT:    ret void
2129 //
2130 //
2131 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2132 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2133 // CHECK13-NEXT:  entry:
2134 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2135 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2136 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2137 // CHECK13-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2138 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2139 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2140 // CHECK13-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2141 // CHECK13-NEXT:    store float [[TMP0]], ptr [[F]], align 4
2142 // CHECK13-NEXT:    ret void
2143 //
2144 //
2145 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2146 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2147 // CHECK13-NEXT:  entry:
2148 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2149 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2150 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2151 // CHECK13-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2152 // CHECK13-NEXT:    ret void
2153 //
2154 //
2155 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2156 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2157 // CHECK13-NEXT:  entry:
2158 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2159 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2160 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2161 // CHECK13-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2162 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2163 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2164 // CHECK13-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
2165 // CHECK13-NEXT:    ret void
2166 //
2167 //
2168 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2169 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2170 // CHECK13-NEXT:  entry:
2171 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2172 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2173 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2174 // CHECK13-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2175 // CHECK13-NEXT:    ret void
2176 //
2177 //
2178 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2179 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2180 // CHECK13-NEXT:  entry:
2181 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2182 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2183 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2184 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2185 // CHECK13-NEXT:    store i32 0, ptr [[F]], align 4
2186 // CHECK13-NEXT:    ret void
2187 //
2188 //
2189 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2190 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2191 // CHECK13-NEXT:  entry:
2192 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2193 // CHECK13-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2194 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2195 // CHECK13-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2196 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2197 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2198 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2199 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2200 // CHECK13-NEXT:    ret void
2201 //
2202 //
2203 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2204 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2205 // CHECK13-NEXT:  entry:
2206 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2207 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2208 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2209 // CHECK13-NEXT:    ret void
2210 //
2211 //
2212 // CHECK15-LABEL: define {{[^@]+}}@main
2213 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
2214 // CHECK15-NEXT:  entry:
2215 // CHECK15-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2216 // CHECK15-NEXT:    [[G:%.*]] = alloca double, align 8
2217 // CHECK15-NEXT:    [[G1:%.*]] = alloca ptr, align 4
2218 // CHECK15-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2219 // CHECK15-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2220 // CHECK15-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2221 // CHECK15-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2222 // CHECK15-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
2223 // CHECK15-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2224 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2225 // CHECK15-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
2226 // CHECK15-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2227 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2228 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2229 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2230 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
2231 // CHECK15-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2232 // CHECK15-NEXT:    store ptr [[G]], ptr [[G1]], align 4
2233 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2234 // CHECK15-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2235 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
2236 // CHECK15-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2237 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
2238 // CHECK15-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1
2239 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
2240 // CHECK15-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
2241 // CHECK15-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
2242 // CHECK15-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
2243 // CHECK15-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4
2244 // CHECK15-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
2245 // CHECK15-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 4
2246 // CHECK15-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4
2247 // CHECK15-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 4
2248 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2249 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2250 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2251 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2252 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2253 // CHECK15:       omp.inner.for.cond:
2254 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
2255 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
2256 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2257 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2258 // CHECK15:       omp.inner.for.body:
2259 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2260 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2261 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2262 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2263 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]]
2264 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2265 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
2266 // CHECK15-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
2267 // CHECK15-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP3]]
2268 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2269 // CHECK15-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
2270 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]
2271 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2272 // CHECK15:       omp.body.continue:
2273 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2274 // CHECK15:       omp.inner.for.inc:
2275 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2276 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
2277 // CHECK15-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2278 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2279 // CHECK15:       omp.inner.for.end:
2280 // CHECK15-NEXT:    store i32 2, ptr [[I]], align 4
2281 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
2282 // CHECK15-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
2283 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2284 // CHECK15-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2285 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2286 // CHECK15:       arraydestroy.body:
2287 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2288 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2289 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
2290 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2291 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2292 // CHECK15:       arraydestroy.done6:
2293 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2294 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2295 // CHECK15-NEXT:    ret i32 [[TMP14]]
2296 //
2297 //
2298 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2299 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2300 // CHECK15-NEXT:  entry:
2301 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2302 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2303 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2304 // CHECK15-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2305 // CHECK15-NEXT:    ret void
2306 //
2307 //
2308 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2309 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2310 // CHECK15-NEXT:  entry:
2311 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2312 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2313 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2314 // CHECK15-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2315 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2316 // CHECK15-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2317 // CHECK15-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2318 // CHECK15-NEXT:    ret void
2319 //
2320 //
2321 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2322 // CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat {
2323 // CHECK15-NEXT:  entry:
2324 // CHECK15-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2325 // CHECK15-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2326 // CHECK15-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2327 // CHECK15-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2328 // CHECK15-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2329 // CHECK15-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
2330 // CHECK15-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2331 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2332 // CHECK15-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
2333 // CHECK15-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2334 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2335 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2336 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2337 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
2338 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2339 // CHECK15-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2340 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
2341 // CHECK15-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2342 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2343 // CHECK15-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
2344 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2345 // CHECK15-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
2346 // CHECK15-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
2347 // CHECK15-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
2348 // CHECK15-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4
2349 // CHECK15-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
2350 // CHECK15-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 4
2351 // CHECK15-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4
2352 // CHECK15-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 4
2353 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2354 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2355 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2356 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2357 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2358 // CHECK15:       omp.inner.for.cond:
2359 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
2360 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
2361 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2362 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2363 // CHECK15:       omp.inner.for.body:
2364 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2365 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2366 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2367 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2368 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]]
2369 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2370 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
2371 // CHECK15-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
2372 // CHECK15-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP7]]
2373 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2374 // CHECK15-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
2375 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]
2376 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2377 // CHECK15:       omp.body.continue:
2378 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2379 // CHECK15:       omp.inner.for.inc:
2380 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2381 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
2382 // CHECK15-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2383 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
2384 // CHECK15:       omp.inner.for.end:
2385 // CHECK15-NEXT:    store i32 2, ptr [[I]], align 4
2386 // CHECK15-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2387 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2388 // CHECK15-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2389 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2390 // CHECK15:       arraydestroy.body:
2391 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2392 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2393 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2394 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2395 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2396 // CHECK15:       arraydestroy.done6:
2397 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2398 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2399 // CHECK15-NEXT:    ret i32 [[TMP14]]
2400 //
2401 //
2402 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2403 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2404 // CHECK15-NEXT:  entry:
2405 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2406 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2407 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2408 // CHECK15-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2409 // CHECK15-NEXT:    ret void
2410 //
2411 //
2412 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2413 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2414 // CHECK15-NEXT:  entry:
2415 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2416 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2417 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2418 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2419 // CHECK15-NEXT:    store float 0.000000e+00, ptr [[F]], align 4
2420 // CHECK15-NEXT:    ret void
2421 //
2422 //
2423 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2424 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2425 // CHECK15-NEXT:  entry:
2426 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2427 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2428 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2429 // CHECK15-NEXT:    ret void
2430 //
2431 //
2432 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2433 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2434 // CHECK15-NEXT:  entry:
2435 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2436 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2437 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2438 // CHECK15-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2439 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2440 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2441 // CHECK15-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2442 // CHECK15-NEXT:    store float [[TMP0]], ptr [[F]], align 4
2443 // CHECK15-NEXT:    ret void
2444 //
2445 //
2446 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2447 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2448 // CHECK15-NEXT:  entry:
2449 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2450 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2451 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2452 // CHECK15-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2453 // CHECK15-NEXT:    ret void
2454 //
2455 //
2456 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2457 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2458 // CHECK15-NEXT:  entry:
2459 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2460 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2461 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2462 // CHECK15-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2463 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2464 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2465 // CHECK15-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2466 // CHECK15-NEXT:    ret void
2467 //
2468 //
2469 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2470 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2471 // CHECK15-NEXT:  entry:
2472 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2473 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2474 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2475 // CHECK15-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2476 // CHECK15-NEXT:    ret void
2477 //
2478 //
2479 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2480 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2481 // CHECK15-NEXT:  entry:
2482 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2483 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2484 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2485 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2486 // CHECK15-NEXT:    store i32 0, ptr [[F]], align 4
2487 // CHECK15-NEXT:    ret void
2488 //
2489 //
2490 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2491 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2492 // CHECK15-NEXT:  entry:
2493 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2494 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2495 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2496 // CHECK15-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2497 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2498 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2499 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2500 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2501 // CHECK15-NEXT:    ret void
2502 //
2503 //
2504 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2505 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2506 // CHECK15-NEXT:  entry:
2507 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2508 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2509 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2510 // CHECK15-NEXT:    ret void
2511 //